int.isa revision 5222
12089SN/A// -*- mode:c++ -*- 22089SN/A 35222Sksewell@umich.edu// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved 45222Sksewell@umich.edu 55222Sksewell@umich.edu// This software is part of the M5 simulator. 65222Sksewell@umich.edu 75222Sksewell@umich.edu// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 85222Sksewell@umich.edu// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 95222Sksewell@umich.edu// TO THESE TERMS AND CONDITIONS. 105222Sksewell@umich.edu 115222Sksewell@umich.edu// Permission is granted to use, copy, create derivative works and 125222Sksewell@umich.edu// distribute this software and such derivative works for any purpose, 135222Sksewell@umich.edu// so long as (1) the copyright notice above, this grant of permission, 145222Sksewell@umich.edu// and the disclaimer below appear in all copies and derivative works 155222Sksewell@umich.edu// made, (2) the copyright notice above is augmented as appropriate to 165222Sksewell@umich.edu// reflect the addition of any new copyrightable work in a derivative 175222Sksewell@umich.edu// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3) 185222Sksewell@umich.edu// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any 195222Sksewell@umich.edu// advertising or publicity pertaining to the use or distribution of 205222Sksewell@umich.edu// this software without specific, written prior authorization. 215222Sksewell@umich.edu 225222Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND 235222Sksewell@umich.edu// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 245222Sksewell@umich.edu// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 255222Sksewell@umich.edu// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 265222Sksewell@umich.edu// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 275222Sksewell@umich.edu// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 285222Sksewell@umich.edu// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 295222Sksewell@umich.edu// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 305222Sksewell@umich.edu// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 315222Sksewell@umich.edu// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 325222Sksewell@umich.edu// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 335222Sksewell@umich.edu// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 345222Sksewell@umich.edu 355222Sksewell@umich.edu//Authors: Korey L. Sewell 362706Sksewell@umich.edu 372022SN/A//////////////////////////////////////////////////////////////////// 382022SN/A// 392022SN/A// Integer operate instructions 402022SN/A// 412022SN/Aoutput header {{ 422239SN/A#include <iostream> 434661Sksewell@umich.edu using namespace std; 442022SN/A /** 452022SN/A * Base class for integer operations. 462022SN/A */ 472041SN/A class IntOp : public MipsStaticInst 482022SN/A { 492022SN/A protected: 502022SN/A 512022SN/A /// Constructor 522089SN/A IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 532044SN/A MipsStaticInst(mnem, _machInst, __opClass) 542044SN/A { 552044SN/A } 562044SN/A 572044SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 582044SN/A }; 592044SN/A 602686Sksewell@umich.edu 612686Sksewell@umich.edu class HiLoOp: public IntOp 622686Sksewell@umich.edu { 632686Sksewell@umich.edu protected: 642686Sksewell@umich.edu 652686Sksewell@umich.edu /// Constructor 662686Sksewell@umich.edu HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 672686Sksewell@umich.edu IntOp(mnem, _machInst, __opClass) 682686Sksewell@umich.edu { 692686Sksewell@umich.edu } 702686Sksewell@umich.edu 712686Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 722686Sksewell@umich.edu }; 732686Sksewell@umich.edu 744661Sksewell@umich.edu class HiLoRsSelOp: public HiLoOp 752686Sksewell@umich.edu { 762686Sksewell@umich.edu protected: 772686Sksewell@umich.edu 782686Sksewell@umich.edu /// Constructor 794661Sksewell@umich.edu HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 802686Sksewell@umich.edu HiLoOp(mnem, _machInst, __opClass) 812686Sksewell@umich.edu { 822686Sksewell@umich.edu } 832686Sksewell@umich.edu 842686Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 852686Sksewell@umich.edu }; 862686Sksewell@umich.edu 874661Sksewell@umich.edu class HiLoRdSelOp: public HiLoOp 884661Sksewell@umich.edu { 894661Sksewell@umich.edu protected: 904661Sksewell@umich.edu 914661Sksewell@umich.edu /// Constructor 924661Sksewell@umich.edu HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 934661Sksewell@umich.edu HiLoOp(mnem, _machInst, __opClass) 944661Sksewell@umich.edu { 954661Sksewell@umich.edu } 964661Sksewell@umich.edu 974661Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 984661Sksewell@umich.edu }; 994661Sksewell@umich.edu 1004661Sksewell@umich.edu class HiLoRdSelValOp: public HiLoOp 1014661Sksewell@umich.edu { 1024661Sksewell@umich.edu protected: 1034661Sksewell@umich.edu 1044661Sksewell@umich.edu /// Constructor 1054661Sksewell@umich.edu HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 1064661Sksewell@umich.edu HiLoOp(mnem, _machInst, __opClass) 1074661Sksewell@umich.edu { 1084661Sksewell@umich.edu } 1094661Sksewell@umich.edu 1104661Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1114661Sksewell@umich.edu }; 1122686Sksewell@umich.edu 1132044SN/A class IntImmOp : public MipsStaticInst 1142044SN/A { 1152044SN/A protected: 1162239SN/A 1172495SN/A int16_t imm; 1182495SN/A int32_t sextImm; 1192495SN/A uint32_t zextImm; 1202044SN/A 1212044SN/A /// Constructor 1222089SN/A IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 1232495SN/A MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM), 1242495SN/A sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM) 1252022SN/A { 1262239SN/A //If Bit 15 is 1 then Sign Extend 1272495SN/A int32_t temp = sextImm & 0x00008000; 1285222Sksewell@umich.edu if (temp > 0 && mnemonic != "lui") { 1292495SN/A sextImm |= 0xFFFF0000; 1302239SN/A } 1312022SN/A } 1322022SN/A 1332022SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1342239SN/A 1352239SN/A 1362022SN/A }; 1372041SN/A 1382022SN/A}}; 1392022SN/A 1404661Sksewell@umich.edu// HiLo instruction class execute method template. 1412686Sksewell@umich.edudef template HiLoExecute {{ 1422686Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1432686Sksewell@umich.edu { 1442686Sksewell@umich.edu Fault fault = NoFault; 1452686Sksewell@umich.edu 1462686Sksewell@umich.edu %(fp_enable_check)s; 1472686Sksewell@umich.edu %(op_decl)s; 1482686Sksewell@umich.edu %(op_rd)s; 1492686Sksewell@umich.edu %(code)s; 1502686Sksewell@umich.edu 1512686Sksewell@umich.edu if(fault == NoFault) 1522686Sksewell@umich.edu { 1532686Sksewell@umich.edu %(op_wb)s; 1544661Sksewell@umich.edu } 1554661Sksewell@umich.edu return fault; 1564661Sksewell@umich.edu } 1574661Sksewell@umich.edu}}; 1584661Sksewell@umich.edu 1594661Sksewell@umich.edu// HiLoRsSel instruction class execute method template. 1604661Sksewell@umich.edudef template HiLoRsSelExecute {{ 1614661Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1624661Sksewell@umich.edu { 1634661Sksewell@umich.edu Fault fault = NoFault; 1644661Sksewell@umich.edu 1654661Sksewell@umich.edu %(op_decl)s; 1664661Sksewell@umich.edu 1674661Sksewell@umich.edu if( ACSRC > 0 && !isDspEnabled(xc) ) 1684661Sksewell@umich.edu { 1694661Sksewell@umich.edu fault = new DspStateDisabledFault(); 1704661Sksewell@umich.edu } 1714661Sksewell@umich.edu else 1724661Sksewell@umich.edu { 1734661Sksewell@umich.edu %(op_rd)s; 1744661Sksewell@umich.edu %(code)s; 1754661Sksewell@umich.edu } 1764661Sksewell@umich.edu 1774661Sksewell@umich.edu if(fault == NoFault) 1784661Sksewell@umich.edu { 1794661Sksewell@umich.edu %(op_wb)s; 1804661Sksewell@umich.edu } 1814661Sksewell@umich.edu return fault; 1824661Sksewell@umich.edu } 1834661Sksewell@umich.edu}}; 1844661Sksewell@umich.edu 1854661Sksewell@umich.edu// HiLoRdSel instruction class execute method template. 1864661Sksewell@umich.edudef template HiLoRdSelExecute {{ 1874661Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1884661Sksewell@umich.edu { 1894661Sksewell@umich.edu Fault fault = NoFault; 1904661Sksewell@umich.edu 1914661Sksewell@umich.edu %(op_decl)s; 1924661Sksewell@umich.edu 1934661Sksewell@umich.edu if( ACDST > 0 && !isDspEnabled(xc) ) 1944661Sksewell@umich.edu { 1954661Sksewell@umich.edu fault = new DspStateDisabledFault(); 1964661Sksewell@umich.edu } 1974661Sksewell@umich.edu else 1984661Sksewell@umich.edu { 1994661Sksewell@umich.edu %(op_rd)s; 2004661Sksewell@umich.edu %(code)s; 2014661Sksewell@umich.edu } 2024661Sksewell@umich.edu 2034661Sksewell@umich.edu if(fault == NoFault) 2044661Sksewell@umich.edu { 2054661Sksewell@umich.edu %(op_wb)s; 2062686Sksewell@umich.edu } 2072686Sksewell@umich.edu return fault; 2082686Sksewell@umich.edu } 2092686Sksewell@umich.edu}}; 2102686Sksewell@umich.edu 2112089SN/A//Outputs to decoder.cc 2122022SN/Aoutput decoder {{ 2132041SN/A std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2142022SN/A { 2152239SN/A std::stringstream ss; 2162239SN/A 2172239SN/A ccprintf(ss, "%-10s ", mnemonic); 2182239SN/A 2192239SN/A // just print the first dest... if there's a second one, 2202239SN/A // it's generally implicit 2212239SN/A if (_numDestRegs > 0) { 2222239SN/A printReg(ss, _destRegIdx[0]); 2232686Sksewell@umich.edu ss << ", "; 2242239SN/A } 2252239SN/A 2262239SN/A // just print the first two source regs... if there's 2272239SN/A // a third one, it's a read-modify-write dest (Rc), 2282239SN/A // e.g. for CMOVxx 2292239SN/A if (_numSrcRegs > 0) { 2302239SN/A printReg(ss, _srcRegIdx[0]); 2312239SN/A } 2322239SN/A 2332239SN/A if (_numSrcRegs > 1) { 2342686Sksewell@umich.edu ss << ", "; 2352239SN/A printReg(ss, _srcRegIdx[1]); 2362239SN/A } 2372239SN/A 2382239SN/A return ss.str(); 2392022SN/A } 2402041SN/A 2412686Sksewell@umich.edu std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2422686Sksewell@umich.edu { 2432686Sksewell@umich.edu std::stringstream ss; 2442686Sksewell@umich.edu 2452686Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 2462686Sksewell@umich.edu 2472686Sksewell@umich.edu //Destination Registers are implicit for HI/LO ops 2482686Sksewell@umich.edu if (_numSrcRegs > 0) { 2492686Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 2502686Sksewell@umich.edu } 2512686Sksewell@umich.edu 2522686Sksewell@umich.edu if (_numSrcRegs > 1) { 2532686Sksewell@umich.edu ss << ", "; 2542686Sksewell@umich.edu printReg(ss, _srcRegIdx[1]); 2552686Sksewell@umich.edu } 2562686Sksewell@umich.edu 2572686Sksewell@umich.edu return ss.str(); 2582686Sksewell@umich.edu } 2592686Sksewell@umich.edu 2604661Sksewell@umich.edu std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2614661Sksewell@umich.edu { 2624661Sksewell@umich.edu std::stringstream ss; 2634661Sksewell@umich.edu 2644661Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 2654661Sksewell@umich.edu 2664661Sksewell@umich.edu if (_numDestRegs > 0 && _destRegIdx[0] < 32) { 2674661Sksewell@umich.edu printReg(ss, _destRegIdx[0]); 2684661Sksewell@umich.edu } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) { 2694661Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 2704661Sksewell@umich.edu } 2714661Sksewell@umich.edu 2724661Sksewell@umich.edu return ss.str(); 2734661Sksewell@umich.edu } 2744661Sksewell@umich.edu 2754661Sksewell@umich.edu std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2764661Sksewell@umich.edu { 2774661Sksewell@umich.edu std::stringstream ss; 2784661Sksewell@umich.edu 2794661Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 2804661Sksewell@umich.edu 2814661Sksewell@umich.edu if (_numDestRegs > 0 && _destRegIdx[0] < 32) { 2824661Sksewell@umich.edu printReg(ss, _destRegIdx[0]); 2834661Sksewell@umich.edu } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) { 2844661Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 2854661Sksewell@umich.edu } 2864661Sksewell@umich.edu 2874661Sksewell@umich.edu return ss.str(); 2884661Sksewell@umich.edu } 2894661Sksewell@umich.edu 2904661Sksewell@umich.edu std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2912686Sksewell@umich.edu { 2922686Sksewell@umich.edu std::stringstream ss; 2932686Sksewell@umich.edu 2942686Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 2952686Sksewell@umich.edu 2962686Sksewell@umich.edu if (_numDestRegs > 0 && _destRegIdx[0] < 32) { 2972686Sksewell@umich.edu printReg(ss, _destRegIdx[0]); 2982686Sksewell@umich.edu } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) { 2992686Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 3002686Sksewell@umich.edu } 3012686Sksewell@umich.edu 3022686Sksewell@umich.edu return ss.str(); 3032686Sksewell@umich.edu } 3042686Sksewell@umich.edu 3052043SN/A std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 3062041SN/A { 3072239SN/A std::stringstream ss; 3082239SN/A 3092239SN/A ccprintf(ss, "%-10s ", mnemonic); 3102239SN/A 3112239SN/A if (_numDestRegs > 0) { 3122239SN/A printReg(ss, _destRegIdx[0]); 3132239SN/A } 3142239SN/A 3152686Sksewell@umich.edu ss << ", "; 3162239SN/A 3172239SN/A if (_numSrcRegs > 0) { 3182239SN/A printReg(ss, _srcRegIdx[0]); 3192686Sksewell@umich.edu ss << ", "; 3202239SN/A } 3212239SN/A 3225222Sksewell@umich.edu if( mnemonic == "lui") 3232686Sksewell@umich.edu ccprintf(ss, "0x%x ", sextImm); 3242239SN/A else 3252495SN/A ss << (int) sextImm; 3262239SN/A 3272239SN/A return ss.str(); 3282041SN/A } 3292239SN/A 3302022SN/A}}; 3312022SN/A 3322043SN/Adef format IntOp(code, *opt_flags) {{ 3333951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'IntOp', code, opt_flags) 3342686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3352686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3362750Sksewell@umich.edu decode_block = RegNopCheckDecode.subst(iop) 3372686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3382022SN/A}}; 3392022SN/A 3402686Sksewell@umich.edudef format IntImmOp(code, *opt_flags) {{ 3413951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags) 3422686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3432686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3442750Sksewell@umich.edu decode_block = ImmNopCheckDecode.subst(iop) 3452686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3462686Sksewell@umich.edu}}; 3472044SN/A 3484661Sksewell@umich.edudef format HiLoRsSelOp(code, *opt_flags) {{ 3494661Sksewell@umich.edu iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags) 3504661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3514661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3524661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3534661Sksewell@umich.edu exec_output = HiLoRsSelExecute.subst(iop) 3544661Sksewell@umich.edu}}; 3554661Sksewell@umich.edu 3564661Sksewell@umich.edudef format HiLoRdSelOp(code, *opt_flags) {{ 3574661Sksewell@umich.edu iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags) 3584661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3594661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3604661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3614661Sksewell@umich.edu exec_output = HiLoRdSelExecute.subst(iop) 3624661Sksewell@umich.edu}}; 3634661Sksewell@umich.edu 3644661Sksewell@umich.edudef format HiLoRdSelValOp(code, *opt_flags) {{ 3654661Sksewell@umich.edu 3664661Sksewell@umich.edu if '.sd' in code: 3674661Sksewell@umich.edu code = 'int64_t ' + code 3684661Sksewell@umich.edu elif '.ud' in code: 3694661Sksewell@umich.edu code = 'uint64_t ' + code 3704661Sksewell@umich.edu 3714661Sksewell@umich.edu code += 'HI_RD_SEL = val<63:32>;\n' 3724661Sksewell@umich.edu code += 'LO_RD_SEL = val<31:0>;\n' 3734661Sksewell@umich.edu 3744661Sksewell@umich.edu iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags) 3754661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3764661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3774661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3784661Sksewell@umich.edu exec_output = HiLoRdSelExecute.subst(iop) 3794661Sksewell@umich.edu}}; 3804661Sksewell@umich.edu 3812686Sksewell@umich.edudef format HiLoOp(code, *opt_flags) {{ 3823951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags) 3832686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3842686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3852750Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3862686Sksewell@umich.edu exec_output = HiLoExecute.subst(iop) 3872686Sksewell@umich.edu}}; 388