int.isa revision 10474
12089SN/A// -*- mode:c++ -*- 22089SN/A 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Korey Sewell 302706Sksewell@umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332022SN/A// Integer operate instructions 342022SN/A// 352022SN/Aoutput header {{ 362239SN/A#include <iostream> 374661Sksewell@umich.edu using namespace std; 382022SN/A /** 392022SN/A * Base class for integer operations. 402022SN/A */ 412041SN/A class IntOp : public MipsStaticInst 422022SN/A { 432022SN/A protected: 442022SN/A 452022SN/A /// Constructor 462089SN/A IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 472044SN/A MipsStaticInst(mnem, _machInst, __opClass) 482044SN/A { 492044SN/A } 502044SN/A 512044SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 522044SN/A }; 532044SN/A 542686Sksewell@umich.edu 552686Sksewell@umich.edu class HiLoOp: public IntOp 562686Sksewell@umich.edu { 572686Sksewell@umich.edu protected: 582686Sksewell@umich.edu 592686Sksewell@umich.edu /// Constructor 602686Sksewell@umich.edu HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 612686Sksewell@umich.edu IntOp(mnem, _machInst, __opClass) 622686Sksewell@umich.edu { 632686Sksewell@umich.edu } 642686Sksewell@umich.edu 652686Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 662686Sksewell@umich.edu }; 672686Sksewell@umich.edu 684661Sksewell@umich.edu class HiLoRsSelOp: public HiLoOp 692686Sksewell@umich.edu { 702686Sksewell@umich.edu protected: 712686Sksewell@umich.edu 722686Sksewell@umich.edu /// Constructor 734661Sksewell@umich.edu HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 742686Sksewell@umich.edu HiLoOp(mnem, _machInst, __opClass) 752686Sksewell@umich.edu { 762686Sksewell@umich.edu } 772686Sksewell@umich.edu 782686Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 792686Sksewell@umich.edu }; 802686Sksewell@umich.edu 814661Sksewell@umich.edu class HiLoRdSelOp: public HiLoOp 824661Sksewell@umich.edu { 834661Sksewell@umich.edu protected: 844661Sksewell@umich.edu 854661Sksewell@umich.edu /// Constructor 864661Sksewell@umich.edu HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 874661Sksewell@umich.edu HiLoOp(mnem, _machInst, __opClass) 884661Sksewell@umich.edu { 894661Sksewell@umich.edu } 904661Sksewell@umich.edu 914661Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 924661Sksewell@umich.edu }; 934661Sksewell@umich.edu 944661Sksewell@umich.edu class HiLoRdSelValOp: public HiLoOp 954661Sksewell@umich.edu { 964661Sksewell@umich.edu protected: 974661Sksewell@umich.edu 984661Sksewell@umich.edu /// Constructor 994661Sksewell@umich.edu HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 1004661Sksewell@umich.edu HiLoOp(mnem, _machInst, __opClass) 1014661Sksewell@umich.edu { 1024661Sksewell@umich.edu } 1034661Sksewell@umich.edu 1044661Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1054661Sksewell@umich.edu }; 1062686Sksewell@umich.edu 1072044SN/A class IntImmOp : public MipsStaticInst 1082044SN/A { 1092044SN/A protected: 1102239SN/A 1112495SN/A int16_t imm; 1122495SN/A int32_t sextImm; 1132495SN/A uint32_t zextImm; 1142044SN/A 1152044SN/A /// Constructor 1162089SN/A IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 1172495SN/A MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM), 1182495SN/A sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM) 1192022SN/A { 1202239SN/A //If Bit 15 is 1 then Sign Extend 1212495SN/A int32_t temp = sextImm & 0x00008000; 1225269Sksewell@umich.edu if (temp > 0 && strcmp(mnemonic,"lui") != 0) { 1232495SN/A sextImm |= 0xFFFF0000; 1242239SN/A } 1252022SN/A } 1262022SN/A 1272022SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1282239SN/A 1292239SN/A 1302022SN/A }; 1312041SN/A 1322022SN/A}}; 1332022SN/A 1344661Sksewell@umich.edu// HiLo instruction class execute method template. 1352686Sksewell@umich.edudef template HiLoExecute {{ 13610196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 1372686Sksewell@umich.edu { 1382686Sksewell@umich.edu Fault fault = NoFault; 1392686Sksewell@umich.edu 1402686Sksewell@umich.edu %(fp_enable_check)s; 1412686Sksewell@umich.edu %(op_decl)s; 1422686Sksewell@umich.edu %(op_rd)s; 1432686Sksewell@umich.edu %(code)s; 1442686Sksewell@umich.edu 1452686Sksewell@umich.edu if(fault == NoFault) 1462686Sksewell@umich.edu { 1472686Sksewell@umich.edu %(op_wb)s; 1484661Sksewell@umich.edu } 1494661Sksewell@umich.edu return fault; 1504661Sksewell@umich.edu } 1514661Sksewell@umich.edu}}; 1524661Sksewell@umich.edu 1534661Sksewell@umich.edu// HiLoRsSel instruction class execute method template. 1544661Sksewell@umich.edudef template HiLoRsSelExecute {{ 15510196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 1564661Sksewell@umich.edu { 1574661Sksewell@umich.edu Fault fault = NoFault; 1584661Sksewell@umich.edu 1594661Sksewell@umich.edu %(op_decl)s; 1604661Sksewell@umich.edu 1614661Sksewell@umich.edu if( ACSRC > 0 && !isDspEnabled(xc) ) 1624661Sksewell@umich.edu { 16310474Sandreas.hansson@arm.com fault = std::make_shared<DspStateDisabledFault>(); 1644661Sksewell@umich.edu } 1654661Sksewell@umich.edu else 1664661Sksewell@umich.edu { 1674661Sksewell@umich.edu %(op_rd)s; 1684661Sksewell@umich.edu %(code)s; 1694661Sksewell@umich.edu } 1704661Sksewell@umich.edu 1714661Sksewell@umich.edu if(fault == NoFault) 1724661Sksewell@umich.edu { 1734661Sksewell@umich.edu %(op_wb)s; 1744661Sksewell@umich.edu } 1754661Sksewell@umich.edu return fault; 1764661Sksewell@umich.edu } 1774661Sksewell@umich.edu}}; 1784661Sksewell@umich.edu 1794661Sksewell@umich.edu// HiLoRdSel instruction class execute method template. 1804661Sksewell@umich.edudef template HiLoRdSelExecute {{ 18110196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 1824661Sksewell@umich.edu { 1834661Sksewell@umich.edu Fault fault = NoFault; 1844661Sksewell@umich.edu 1854661Sksewell@umich.edu %(op_decl)s; 1864661Sksewell@umich.edu 1874661Sksewell@umich.edu if( ACDST > 0 && !isDspEnabled(xc) ) 1884661Sksewell@umich.edu { 18910474Sandreas.hansson@arm.com fault = std::make_shared<DspStateDisabledFault>(); 1904661Sksewell@umich.edu } 1914661Sksewell@umich.edu else 1924661Sksewell@umich.edu { 1934661Sksewell@umich.edu %(op_rd)s; 1944661Sksewell@umich.edu %(code)s; 1954661Sksewell@umich.edu } 1964661Sksewell@umich.edu 1974661Sksewell@umich.edu if(fault == NoFault) 1984661Sksewell@umich.edu { 1994661Sksewell@umich.edu %(op_wb)s; 2002686Sksewell@umich.edu } 2012686Sksewell@umich.edu return fault; 2022686Sksewell@umich.edu } 2032686Sksewell@umich.edu}}; 2042686Sksewell@umich.edu 2052089SN/A//Outputs to decoder.cc 2062022SN/Aoutput decoder {{ 2072041SN/A std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2082022SN/A { 2092239SN/A std::stringstream ss; 2102239SN/A 2112239SN/A ccprintf(ss, "%-10s ", mnemonic); 2122239SN/A 2132239SN/A // just print the first dest... if there's a second one, 2142239SN/A // it's generally implicit 2152239SN/A if (_numDestRegs > 0) { 2162239SN/A printReg(ss, _destRegIdx[0]); 2172686Sksewell@umich.edu ss << ", "; 2182239SN/A } 2192239SN/A 2202239SN/A // just print the first two source regs... if there's 2212239SN/A // a third one, it's a read-modify-write dest (Rc), 2222239SN/A // e.g. for CMOVxx 2232239SN/A if (_numSrcRegs > 0) { 2242239SN/A printReg(ss, _srcRegIdx[0]); 2252239SN/A } 2262239SN/A 2272239SN/A if (_numSrcRegs > 1) { 2282686Sksewell@umich.edu ss << ", "; 2292239SN/A printReg(ss, _srcRegIdx[1]); 2302239SN/A } 2312239SN/A 2322239SN/A return ss.str(); 2332022SN/A } 2342041SN/A 2352686Sksewell@umich.edu std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2362686Sksewell@umich.edu { 2372686Sksewell@umich.edu std::stringstream ss; 2382686Sksewell@umich.edu 2392686Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 2402686Sksewell@umich.edu 2412686Sksewell@umich.edu //Destination Registers are implicit for HI/LO ops 2422686Sksewell@umich.edu if (_numSrcRegs > 0) { 2432686Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 2442686Sksewell@umich.edu } 2452686Sksewell@umich.edu 2462686Sksewell@umich.edu if (_numSrcRegs > 1) { 2472686Sksewell@umich.edu ss << ", "; 2482686Sksewell@umich.edu printReg(ss, _srcRegIdx[1]); 2492686Sksewell@umich.edu } 2502686Sksewell@umich.edu 2512686Sksewell@umich.edu return ss.str(); 2522686Sksewell@umich.edu } 2532686Sksewell@umich.edu 2544661Sksewell@umich.edu std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2554661Sksewell@umich.edu { 2564661Sksewell@umich.edu std::stringstream ss; 2574661Sksewell@umich.edu 2584661Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 2594661Sksewell@umich.edu 2604661Sksewell@umich.edu if (_numDestRegs > 0 && _destRegIdx[0] < 32) { 2614661Sksewell@umich.edu printReg(ss, _destRegIdx[0]); 2624661Sksewell@umich.edu } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) { 2634661Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 2644661Sksewell@umich.edu } 2654661Sksewell@umich.edu 2664661Sksewell@umich.edu return ss.str(); 2674661Sksewell@umich.edu } 2684661Sksewell@umich.edu 2694661Sksewell@umich.edu std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2704661Sksewell@umich.edu { 2714661Sksewell@umich.edu std::stringstream ss; 2724661Sksewell@umich.edu 2734661Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 2744661Sksewell@umich.edu 2754661Sksewell@umich.edu if (_numDestRegs > 0 && _destRegIdx[0] < 32) { 2764661Sksewell@umich.edu printReg(ss, _destRegIdx[0]); 2774661Sksewell@umich.edu } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) { 2784661Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 2794661Sksewell@umich.edu } 2804661Sksewell@umich.edu 2814661Sksewell@umich.edu return ss.str(); 2824661Sksewell@umich.edu } 2834661Sksewell@umich.edu 2844661Sksewell@umich.edu std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2852686Sksewell@umich.edu { 2862686Sksewell@umich.edu std::stringstream ss; 2872686Sksewell@umich.edu 2882686Sksewell@umich.edu ccprintf(ss, "%-10s ", mnemonic); 2892686Sksewell@umich.edu 2902686Sksewell@umich.edu if (_numDestRegs > 0 && _destRegIdx[0] < 32) { 2912686Sksewell@umich.edu printReg(ss, _destRegIdx[0]); 2922686Sksewell@umich.edu } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) { 2932686Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 2942686Sksewell@umich.edu } 2952686Sksewell@umich.edu 2962686Sksewell@umich.edu return ss.str(); 2972686Sksewell@umich.edu } 2982686Sksewell@umich.edu 2992043SN/A std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 3002041SN/A { 3012239SN/A std::stringstream ss; 3022239SN/A 3032239SN/A ccprintf(ss, "%-10s ", mnemonic); 3042239SN/A 3052239SN/A if (_numDestRegs > 0) { 3062239SN/A printReg(ss, _destRegIdx[0]); 3072239SN/A } 3082239SN/A 3092686Sksewell@umich.edu ss << ", "; 3102239SN/A 3112239SN/A if (_numSrcRegs > 0) { 3122239SN/A printReg(ss, _srcRegIdx[0]); 3132686Sksewell@umich.edu ss << ", "; 3142239SN/A } 3152239SN/A 3165269Sksewell@umich.edu if(strcmp(mnemonic,"lui") == 0) 3172686Sksewell@umich.edu ccprintf(ss, "0x%x ", sextImm); 3182239SN/A else 3192495SN/A ss << (int) sextImm; 3202239SN/A 3212239SN/A return ss.str(); 3222041SN/A } 3232239SN/A 3242022SN/A}}; 3252022SN/A 3262043SN/Adef format IntOp(code, *opt_flags) {{ 3273951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'IntOp', code, opt_flags) 3282686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3292686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3302750Sksewell@umich.edu decode_block = RegNopCheckDecode.subst(iop) 3312686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3322022SN/A}}; 3332022SN/A 3342686Sksewell@umich.edudef format IntImmOp(code, *opt_flags) {{ 3353951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags) 3362686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3372686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3382750Sksewell@umich.edu decode_block = ImmNopCheckDecode.subst(iop) 3392686Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3402686Sksewell@umich.edu}}; 3412044SN/A 3424661Sksewell@umich.edudef format HiLoRsSelOp(code, *opt_flags) {{ 3434661Sksewell@umich.edu iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags) 3444661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3454661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3464661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3474661Sksewell@umich.edu exec_output = HiLoRsSelExecute.subst(iop) 3484661Sksewell@umich.edu}}; 3494661Sksewell@umich.edu 3504661Sksewell@umich.edudef format HiLoRdSelOp(code, *opt_flags) {{ 3514661Sksewell@umich.edu iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags) 3524661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3534661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3544661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3554661Sksewell@umich.edu exec_output = HiLoRdSelExecute.subst(iop) 3564661Sksewell@umich.edu}}; 3574661Sksewell@umich.edu 3584661Sksewell@umich.edudef format HiLoRdSelValOp(code, *opt_flags) {{ 3594661Sksewell@umich.edu 3608588Sgblack@eecs.umich.edu if '_sd' in code: 3614661Sksewell@umich.edu code = 'int64_t ' + code 3628588Sgblack@eecs.umich.edu elif '_ud' in code: 3634661Sksewell@umich.edu code = 'uint64_t ' + code 3644661Sksewell@umich.edu 3654661Sksewell@umich.edu code += 'HI_RD_SEL = val<63:32>;\n' 3664661Sksewell@umich.edu code += 'LO_RD_SEL = val<31:0>;\n' 3674661Sksewell@umich.edu 3684661Sksewell@umich.edu iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags) 3694661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3704661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3714661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3724661Sksewell@umich.edu exec_output = HiLoRdSelExecute.subst(iop) 3734661Sksewell@umich.edu}}; 3744661Sksewell@umich.edu 3752686Sksewell@umich.edudef format HiLoOp(code, *opt_flags) {{ 3763951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags) 3772686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3782686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3792750Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3802686Sksewell@umich.edu exec_output = HiLoExecute.subst(iop) 3812686Sksewell@umich.edu}}; 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