fp.isa revision 8564
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30 31//////////////////////////////////////////////////////////////////// 32// 33// Floating Point operate instructions 34// 35 36output header {{ 37 /** 38 * Base class for FP operations. 39 */ 40 class FPOp : public MipsStaticInst 41 { 42 protected: 43 44 /// Constructor 45 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) 46 { 47 } 48 49 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 50 51 //needs function to check for fpEnable or not 52 }; 53 54 class FPCompareOp : public FPOp 55 { 56 protected: 57 FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass) 58 { 59 } 60 61 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 62 63 }; 64}}; 65 66output decoder {{ 67 std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 68 { 69 std::stringstream ss; 70 71 ccprintf(ss, "%-10s ", mnemonic); 72 73 ccprintf(ss,"%d",CC); 74 75 if(_numSrcRegs > 0) { 76 ss << ", "; 77 printReg(ss, _srcRegIdx[0]); 78 } 79 80 if(_numSrcRegs > 1) { 81 ss << ", "; 82 printReg(ss, _srcRegIdx[1]); 83 } 84 85 return ss.str(); 86 } 87}}; 88 89output exec {{ 90 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) 91 { 92 //@TODO: Implement correct CP0 checks to see if the CP1 93 // unit is enable or not 94 if (!isCoprocessorEnabled(xc, 1)) 95 return new CoprocessorUnusableFault(1); 96 97 return NoFault; 98 } 99 100 //If any operand is Nan return the appropriate QNaN 101 template <class T> 102 bool 103 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type, 104 Trace::InstRecord *traceData) 105 { 106 uint64_t mips_nan = 0; 107 assert(sizeof(T) == 4); 108 109 for (int i = 0; i < inst->numSrcRegs(); i++) { 110 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0); 111 112 if (isNan(&src_bits, 32) ) { 113 mips_nan = MIPS32_QNAN; 114 xc->setFloatRegOperandBits(inst, 0, mips_nan); 115 if (traceData) { traceData->setData(mips_nan); } 116 return true; 117 } 118 } 119 return false; 120 } 121 122 template <class T> 123 bool 124 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val, 125 Trace::InstRecord *traceData) 126 { 127 uint64_t mips_nan = 0; 128 T src_op = dest_val; 129 assert(sizeof(T) == 4); 130 131 if (isNan(&src_op, 32)) { 132 mips_nan = MIPS32_QNAN; 133 134 //Set value to QNAN 135 cpu->setFloatRegOperandBits(inst, 0, mips_nan); 136 137 //Read FCSR from FloatRegFile 138 uint32_t fcsr_bits = 139 cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); 140 141 uint32_t new_fcsr = genInvalidVector(fcsr_bits); 142 143 //Write FCSR from FloatRegFile 144 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr); 145 146 if (traceData) { traceData->setData(mips_nan); } 147 return true; 148 } 149 150 return false; 151 } 152 153 void 154 fpResetCauseBits(%(CPU_exec_context)s *cpu) 155 { 156 //Read FCSR from FloatRegFile 157 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); 158 159 // TODO: Use utility function here 160 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); 161 162 //Write FCSR from FloatRegFile 163 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr); 164 } 165}}; 166 167def template FloatingPointExecute {{ 168 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 169 { 170 Fault fault = NoFault; 171 172 %(fp_enable_check)s; 173 174 175 //When is the right time to reset cause bits? 176 //start of every instruction or every cycle? 177 if (FULL_SYSTEM) 178 fpResetCauseBits(xc); 179 %(op_decl)s; 180 %(op_rd)s; 181 182 //Check if any FP operand is a NaN value 183 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) { 184 %(code)s; 185 186 //Change this code for Full-System/Sycall Emulation 187 //separation 188 //---- 189 //Should Full System-Mode throw a fault here? 190 //---- 191 //Check for IEEE 754 FP Exceptions 192 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); 193 bool invalid_op = false; 194 if (FULL_SYSTEM) { 195 invalid_op = 196 fpInvalidOp((FPOp*)this, xc, Fd, traceData); 197 } 198 if (!invalid_op && fault == NoFault) { 199 %(op_wb)s; 200 } 201 } 202 203 return fault; 204 } 205}}; 206 207// Primary format for float point operate instructions: 208def format FloatOp(code, *flags) {{ 209 iop = InstObjParams(name, Name, 'FPOp', code, flags) 210 header_output = BasicDeclare.subst(iop) 211 decoder_output = BasicConstructor.subst(iop) 212 decode_block = BasicDecode.subst(iop) 213 exec_output = FloatingPointExecute.subst(iop) 214}}; 215 216def format FloatCompareOp(cond_code, *flags) {{ 217 import sys 218 219 code = 'bool cond;\n' 220 if '.sf' in cond_code or 'SinglePrecision' in flags: 221 if 'QnanException' in flags: 222 code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n' 223 code += '\tFCSR = genInvalidVector(FCSR);\n' 224 code += '\treturn NoFault;' 225 code += '}\n else ' 226 code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n' 227 elif '.df' in cond_code or 'DoublePrecision' in flags: 228 if 'QnanException' in flags: 229 code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n' 230 code += '\tFCSR = genInvalidVector(FCSR);\n' 231 code += '\treturn NoFault;' 232 code += '}\n else ' 233 code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n' 234 else: 235 sys.exit('Decoder Failed: Can\'t Determine Operand Type\n') 236 237 if 'UnorderedTrue' in flags: 238 code += 'cond = 1;\n' 239 elif 'UnorderedFalse' in flags: 240 code += 'cond = 0;\n' 241 else: 242 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 243 244 code += '} else {\n' 245 code += cond_code + '}' 246 code += 'FCSR = genCCVector(FCSR, CC, cond);\n' 247 248 iop = InstObjParams(name, Name, 'FPCompareOp', code) 249 header_output = BasicDeclare.subst(iop) 250 decoder_output = BasicConstructor.subst(iop) 251 decode_block = BasicDecode.subst(iop) 252 exec_output = BasicExecute.subst(iop) 253}}; 254 255def format FloatConvertOp(code, *flags) {{ 256 import sys 257 258 #Determine Source Type 259 convert = 'fpConvert(' 260 if '.sf' in code: 261 code = 'float ' + code + '\n' 262 convert += 'SINGLE_TO_' 263 elif '.df' in code: 264 code = 'double ' + code + '\n' 265 convert += 'DOUBLE_TO_' 266 elif '.uw' in code: 267 code = 'uint32_t ' + code + '\n' 268 convert += 'WORD_TO_' 269 elif '.ud' in code: 270 code = 'uint64_t ' + code + '\n' 271 convert += 'LONG_TO_' 272 else: 273 sys.exit("Error Determining Source Type for Conversion") 274 275 #Determine Destination Type 276 if 'ToSingle' in flags: 277 code += 'Fd.uw = ' + convert + 'SINGLE, ' 278 elif 'ToDouble' in flags: 279 code += 'Fd.ud = ' + convert + 'DOUBLE, ' 280 elif 'ToWord' in flags: 281 code += 'Fd.uw = ' + convert + 'WORD, ' 282 elif 'ToLong' in flags: 283 code += 'Fd.ud = ' + convert + 'LONG, ' 284 else: 285 sys.exit("Error Determining Destination Type for Conversion") 286 287 #Figure out how to round value 288 if 'Ceil' in flags: 289 code += 'ceil(val)); ' 290 elif 'Floor' in flags: 291 code += 'floor(val)); ' 292 elif 'Round' in flags: 293 code += 'roundFP(val, 0)); ' 294 elif 'Trunc' in flags: 295 code += 'truncFP(val));' 296 else: 297 code += 'val); ' 298 299 iop = InstObjParams(name, Name, 'FPOp', code) 300 header_output = BasicDeclare.subst(iop) 301 decoder_output = BasicConstructor.subst(iop) 302 decode_block = BasicDecode.subst(iop) 303 exec_output = BasicExecute.subst(iop) 304}}; 305 306def format FloatAccOp(code, *flags) {{ 307 iop = InstObjParams(name, Name, 'FPOp', code, flags) 308 header_output = BasicDeclare.subst(iop) 309 decoder_output = BasicConstructor.subst(iop) 310 decode_block = BasicDecode.subst(iop) 311 exec_output = BasicExecute.subst(iop) 312}}; 313 314// Primary format for float64 operate instructions: 315def format Float64Op(code, *flags) {{ 316 iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags) 317 header_output = BasicDeclare.subst(iop) 318 decoder_output = BasicConstructor.subst(iop) 319 decode_block = BasicDecode.subst(iop) 320 exec_output = BasicExecute.subst(iop) 321}}; 322 323def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ 324 import sys 325 326 code = 'bool cond1, cond2;\n' 327 code += 'bool code_block1, code_block2;\n' 328 code += 'code_block1 = code_block2 = true;\n' 329 330 if 'QnanException' in flags: 331 code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n' 332 code += '\tFCSR = genInvalidVector(FCSR);\n' 333 code += 'code_block1 = false;' 334 code += '}\n' 335 code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n' 336 code += '\tFCSR = genInvalidVector(FCSR);\n' 337 code += 'code_block2 = false;' 338 code += '}\n' 339 340 code += 'if (code_block1) {' 341 code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n' 342 if 'UnorderedTrue' in flags: 343 code += 'cond1 = 1;\n' 344 elif 'UnorderedFalse' in flags: 345 code += 'cond1 = 0;\n' 346 else: 347 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 348 code += '} else {\n' 349 code += cond_code1 350 code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n' 351 352 code += 'if (code_block2) {' 353 code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n' 354 if 'UnorderedTrue' in flags: 355 code += 'cond2 = 1;\n' 356 elif 'UnorderedFalse' in flags: 357 code += 'cond2 = 0;\n' 358 else: 359 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n') 360 code += '} else {\n' 361 code += cond_code2 362 code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}' 363 364 iop = InstObjParams(name, Name, 'FPCompareOp', code) 365 header_output = BasicDeclare.subst(iop) 366 decoder_output = BasicConstructor.subst(iop) 367 decode_block = BasicDecode.subst(iop) 368 exec_output = BasicExecute.subst(iop) 369}}; 370 371