dsp.isa revision 10196
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30// Brett Miller 31 32//////////////////////////////////////////////////////////////////// 33// 34// DSP integer operate instructions 35// 36output header {{ 37#include <iostream> 38 using namespace std; 39 /** 40 * Base class for integer operations. 41 */ 42 class DspIntOp : public MipsStaticInst 43 { 44 protected: 45 46 /// Constructor 47 DspIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 48 MipsStaticInst(mnem, _machInst, __opClass) 49 { 50 } 51 }; 52 53 class DspHiLoOp : public MipsStaticInst 54 { 55 protected: 56 57 /// Constructor 58 DspHiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 59 MipsStaticInst(mnem, _machInst, __opClass) 60 { 61 } 62 }; 63}}; 64 65// Dsp instruction class execute method template. 66def template DspExecute {{ 67 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 68 { 69 Fault fault = NoFault; 70 71 %(op_decl)s; 72 73 if (isDspPresent(xc)) 74 { 75 if (isDspEnabled(xc)) 76 { 77 %(op_rd)s; 78 %(code)s; 79 } 80 else 81 { 82 fault = new DspStateDisabledFault(); 83 } 84 } 85 else 86 { 87 fault = new ReservedInstructionFault(); 88 } 89 90 if(fault == NoFault) 91 { 92 %(op_wb)s; 93 } 94 return fault; 95 } 96}}; 97 98// DspHiLo instruction class execute method template. 99def template DspHiLoExecute {{ 100 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 101 { 102 Fault fault = NoFault; 103 104 %(op_decl)s; 105 106 if (isDspPresent(xc)) 107 { 108 if (isDspEnabled(xc)) 109 { 110 %(op_rd)s; 111 %(code)s; 112 } 113 else 114 { 115 fault = new DspStateDisabledFault(); 116 } 117 } 118 else 119 { 120 fault = new ReservedInstructionFault(); 121 } 122 123 if(fault == NoFault) 124 { 125 %(op_wb)s; 126 //If there are 2 Destination Registers then 127 //concatenate the values for the traceData 128 if(traceData && _numDestRegs == 2) { 129 // FIXME - set the trace value correctly here 130 //uint64_t hilo_final_val = (uint64_t)HI_RD_SEL << 32 | LO_RD_SEL; 131 //traceData->setData(hilo_final_val); 132 } 133 } 134 return fault; 135 } 136}}; 137 138output header {{ 139 bool isDspEnabled(%(CPU_exec_context)s *xc); 140 141 bool isDspPresent(%(CPU_exec_context)s *xc); 142}}; 143 144//Outputs to decoder.cc 145output decoder {{ 146}}; 147 148output exec {{ 149 bool 150 isDspEnabled(CPU_EXEC_CONTEXT *xc) 151 { 152 return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24); 153 } 154}}; 155 156output exec {{ 157 bool 158 isDspPresent(CPU_EXEC_CONTEXT *xc) 159 { 160 return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10); 161 } 162}}; 163 164// add code to fetch the DSPControl register 165// and write it back after execution, giving 166// the instruction the opportunity to modify 167// it if necessary 168def format DspIntOp(code, *opt_flags) {{ 169 170 decl_code = 'uint32_t dspctl;\n' 171 decl_code += 'dspctl = DSPControl;\n' 172 173 write_code = 'DSPControl = dspctl;\n' 174 175 code = decl_code + code + write_code 176 177 opt_flags += ('IsDspOp',) 178 179 iop = InstObjParams(name, Name, 'DspIntOp', code, opt_flags) 180 header_output = BasicDeclare.subst(iop) 181 decoder_output = BasicConstructor.subst(iop) 182 decode_block = BasicDecode.subst(iop) 183 exec_output = DspExecute.subst(iop) 184}}; 185 186// add code to fetch the DSPControl register 187// and write it back after execution, giving 188// the instruction the opportunity to modify 189// it if necessary; also, fetch the appropriate 190// HI/LO register pair, based on the AC 191// instruction field. 192 193def format DspHiLoOp(code, *opt_flags) {{ 194 195 decl_code = 'int64_t dspac;\n' 196 decl_code += 'uint32_t dspctl;\n' 197 198 fetch_code = 'dspctl = DSPControl;\n' 199 fetch_code += 'dspac = HI_RD_SEL;\n' 200 fetch_code += 'dspac = dspac << 32 | LO_RD_SEL;\n' 201 202 write_code = 'DSPControl = dspctl;\n' 203 write_code += 'HI_RD_SEL = dspac<63:32>;\n' 204 write_code += 'LO_RD_SEL = dspac<31:0>;\n' 205 206 code = decl_code + fetch_code + code + write_code 207 208 opt_flags += ('IsDspOp',) 209 210 iop = InstObjParams(name, Name, 'DspHiLoOp', code, opt_flags) 211 header_output = BasicDeclare.subst(iop) 212 decoder_output = BasicConstructor.subst(iop) 213 decode_block = BasicDecode.subst(iop) 214 exec_output = DspHiLoExecute.subst(iop) 215 216}}; 217 218 219 220