dsp.isa revision 10196
14661Sksewell@umich.edu// -*- mode:c++ -*- 24661Sksewell@umich.edu 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Korey Sewell 305268Sksewell@umich.edu// Brett Miller 314661Sksewell@umich.edu 324661Sksewell@umich.edu//////////////////////////////////////////////////////////////////// 334661Sksewell@umich.edu// 344661Sksewell@umich.edu// DSP integer operate instructions 354661Sksewell@umich.edu// 364661Sksewell@umich.eduoutput header {{ 374661Sksewell@umich.edu#include <iostream> 384661Sksewell@umich.edu using namespace std; 394661Sksewell@umich.edu /** 404661Sksewell@umich.edu * Base class for integer operations. 414661Sksewell@umich.edu */ 424661Sksewell@umich.edu class DspIntOp : public MipsStaticInst 434661Sksewell@umich.edu { 444661Sksewell@umich.edu protected: 454661Sksewell@umich.edu 464661Sksewell@umich.edu /// Constructor 474661Sksewell@umich.edu DspIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 484661Sksewell@umich.edu MipsStaticInst(mnem, _machInst, __opClass) 494661Sksewell@umich.edu { 504661Sksewell@umich.edu } 514661Sksewell@umich.edu }; 524661Sksewell@umich.edu 534661Sksewell@umich.edu class DspHiLoOp : public MipsStaticInst 544661Sksewell@umich.edu { 554661Sksewell@umich.edu protected: 564661Sksewell@umich.edu 574661Sksewell@umich.edu /// Constructor 584661Sksewell@umich.edu DspHiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 594661Sksewell@umich.edu MipsStaticInst(mnem, _machInst, __opClass) 604661Sksewell@umich.edu { 614661Sksewell@umich.edu } 624661Sksewell@umich.edu }; 634661Sksewell@umich.edu}}; 644661Sksewell@umich.edu 654661Sksewell@umich.edu// Dsp instruction class execute method template. 664661Sksewell@umich.edudef template DspExecute {{ 6710196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 684661Sksewell@umich.edu { 694661Sksewell@umich.edu Fault fault = NoFault; 704661Sksewell@umich.edu 714661Sksewell@umich.edu %(op_decl)s; 724661Sksewell@umich.edu 734661Sksewell@umich.edu if (isDspPresent(xc)) 744661Sksewell@umich.edu { 754661Sksewell@umich.edu if (isDspEnabled(xc)) 764661Sksewell@umich.edu { 774661Sksewell@umich.edu %(op_rd)s; 784661Sksewell@umich.edu %(code)s; 794661Sksewell@umich.edu } 804661Sksewell@umich.edu else 814661Sksewell@umich.edu { 824661Sksewell@umich.edu fault = new DspStateDisabledFault(); 834661Sksewell@umich.edu } 844661Sksewell@umich.edu } 854661Sksewell@umich.edu else 864661Sksewell@umich.edu { 874661Sksewell@umich.edu fault = new ReservedInstructionFault(); 884661Sksewell@umich.edu } 894661Sksewell@umich.edu 904661Sksewell@umich.edu if(fault == NoFault) 914661Sksewell@umich.edu { 924661Sksewell@umich.edu %(op_wb)s; 934661Sksewell@umich.edu } 944661Sksewell@umich.edu return fault; 954661Sksewell@umich.edu } 964661Sksewell@umich.edu}}; 974661Sksewell@umich.edu 984661Sksewell@umich.edu// DspHiLo instruction class execute method template. 994661Sksewell@umich.edudef template DspHiLoExecute {{ 10010196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 1014661Sksewell@umich.edu { 1024661Sksewell@umich.edu Fault fault = NoFault; 1034661Sksewell@umich.edu 1044661Sksewell@umich.edu %(op_decl)s; 1054661Sksewell@umich.edu 1064661Sksewell@umich.edu if (isDspPresent(xc)) 1074661Sksewell@umich.edu { 1084661Sksewell@umich.edu if (isDspEnabled(xc)) 1094661Sksewell@umich.edu { 1104661Sksewell@umich.edu %(op_rd)s; 1114661Sksewell@umich.edu %(code)s; 1124661Sksewell@umich.edu } 1134661Sksewell@umich.edu else 1144661Sksewell@umich.edu { 1154661Sksewell@umich.edu fault = new DspStateDisabledFault(); 1164661Sksewell@umich.edu } 1174661Sksewell@umich.edu } 1184661Sksewell@umich.edu else 1194661Sksewell@umich.edu { 1204661Sksewell@umich.edu fault = new ReservedInstructionFault(); 1214661Sksewell@umich.edu } 1224661Sksewell@umich.edu 1234661Sksewell@umich.edu if(fault == NoFault) 1244661Sksewell@umich.edu { 1254661Sksewell@umich.edu %(op_wb)s; 1264661Sksewell@umich.edu //If there are 2 Destination Registers then 1274661Sksewell@umich.edu //concatenate the values for the traceData 1284661Sksewell@umich.edu if(traceData && _numDestRegs == 2) { 1294661Sksewell@umich.edu // FIXME - set the trace value correctly here 1304661Sksewell@umich.edu //uint64_t hilo_final_val = (uint64_t)HI_RD_SEL << 32 | LO_RD_SEL; 1314661Sksewell@umich.edu //traceData->setData(hilo_final_val); 1324661Sksewell@umich.edu } 1334661Sksewell@umich.edu } 1344661Sksewell@umich.edu return fault; 1354661Sksewell@umich.edu } 1364661Sksewell@umich.edu}}; 1374661Sksewell@umich.edu 1389554Sandreas.hansson@arm.comoutput header {{ 1399554Sandreas.hansson@arm.com bool isDspEnabled(%(CPU_exec_context)s *xc); 1409554Sandreas.hansson@arm.com 1419554Sandreas.hansson@arm.com bool isDspPresent(%(CPU_exec_context)s *xc); 1429554Sandreas.hansson@arm.com}}; 1439554Sandreas.hansson@arm.com 1444661Sksewell@umich.edu//Outputs to decoder.cc 1454661Sksewell@umich.eduoutput decoder {{ 1464661Sksewell@umich.edu}}; 1474661Sksewell@umich.edu 1484661Sksewell@umich.eduoutput exec {{ 1498564Sgblack@eecs.umich.edu bool 15010196SCurtis.Dunham@arm.com isDspEnabled(CPU_EXEC_CONTEXT *xc) 1514661Sksewell@umich.edu { 1528738Sgblack@eecs.umich.edu return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24); 1534661Sksewell@umich.edu } 1544661Sksewell@umich.edu}}; 1554661Sksewell@umich.edu 1564661Sksewell@umich.eduoutput exec {{ 1578564Sgblack@eecs.umich.edu bool 15810196SCurtis.Dunham@arm.com isDspPresent(CPU_EXEC_CONTEXT *xc) 1594661Sksewell@umich.edu { 1608738Sgblack@eecs.umich.edu return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10); 1614661Sksewell@umich.edu } 1624661Sksewell@umich.edu}}; 1634661Sksewell@umich.edu 1644661Sksewell@umich.edu// add code to fetch the DSPControl register 1654661Sksewell@umich.edu// and write it back after execution, giving 1664661Sksewell@umich.edu// the instruction the opportunity to modify 1674661Sksewell@umich.edu// it if necessary 1684661Sksewell@umich.edudef format DspIntOp(code, *opt_flags) {{ 1694661Sksewell@umich.edu 1704661Sksewell@umich.edu decl_code = 'uint32_t dspctl;\n' 1714661Sksewell@umich.edu decl_code += 'dspctl = DSPControl;\n' 1724661Sksewell@umich.edu 1734661Sksewell@umich.edu write_code = 'DSPControl = dspctl;\n' 1744661Sksewell@umich.edu 1754661Sksewell@umich.edu code = decl_code + code + write_code 1764661Sksewell@umich.edu 1775222Sksewell@umich.edu opt_flags += ('IsDspOp',) 1785222Sksewell@umich.edu 1794661Sksewell@umich.edu iop = InstObjParams(name, Name, 'DspIntOp', code, opt_flags) 1804661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 1814661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 1824661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 1834661Sksewell@umich.edu exec_output = DspExecute.subst(iop) 1844661Sksewell@umich.edu}}; 1854661Sksewell@umich.edu 1864661Sksewell@umich.edu// add code to fetch the DSPControl register 1874661Sksewell@umich.edu// and write it back after execution, giving 1884661Sksewell@umich.edu// the instruction the opportunity to modify 1894661Sksewell@umich.edu// it if necessary; also, fetch the appropriate 1904661Sksewell@umich.edu// HI/LO register pair, based on the AC 1914661Sksewell@umich.edu// instruction field. 1924661Sksewell@umich.edu 1934661Sksewell@umich.edudef format DspHiLoOp(code, *opt_flags) {{ 1944661Sksewell@umich.edu 1954661Sksewell@umich.edu decl_code = 'int64_t dspac;\n' 1964661Sksewell@umich.edu decl_code += 'uint32_t dspctl;\n' 1974661Sksewell@umich.edu 1984661Sksewell@umich.edu fetch_code = 'dspctl = DSPControl;\n' 1994661Sksewell@umich.edu fetch_code += 'dspac = HI_RD_SEL;\n' 2004661Sksewell@umich.edu fetch_code += 'dspac = dspac << 32 | LO_RD_SEL;\n' 2014661Sksewell@umich.edu 2024661Sksewell@umich.edu write_code = 'DSPControl = dspctl;\n' 2034661Sksewell@umich.edu write_code += 'HI_RD_SEL = dspac<63:32>;\n' 2044661Sksewell@umich.edu write_code += 'LO_RD_SEL = dspac<31:0>;\n' 2054661Sksewell@umich.edu 2064661Sksewell@umich.edu code = decl_code + fetch_code + code + write_code 2074661Sksewell@umich.edu 2085222Sksewell@umich.edu opt_flags += ('IsDspOp',) 2095222Sksewell@umich.edu 2104661Sksewell@umich.edu iop = InstObjParams(name, Name, 'DspHiLoOp', code, opt_flags) 2114661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2124661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2134661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2144661Sksewell@umich.edu exec_output = DspHiLoExecute.subst(iop) 2154661Sksewell@umich.edu 2164661Sksewell@umich.edu}}; 2174661Sksewell@umich.edu 2184661Sksewell@umich.edu 2194661Sksewell@umich.edu 220