control.isa revision 8800:1882c44e510a 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30//          Jaidev Patwardhan
31
32////////////////////////////////////////////////////////////////////
33//
34// Coprocessor instructions
35//
36
37//Outputs to decoder.hh
38output header {{
39
40        class CP0Control : public MipsStaticInst
41        {
42                protected:
43
44                /// Constructor
45                CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
46                           MipsStaticInst(mnem, _machInst, __opClass)
47                {
48                }
49
50                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
51        };
52        class CP0TLB : public MipsStaticInst
53        {
54                protected:
55
56                /// Constructor
57                CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) :
58                           MipsStaticInst(mnem, _machInst, __opClass)
59                {
60                }
61
62                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
63        };
64
65
66        class CP1Control : public MipsStaticInst
67        {
68                protected:
69
70                /// Constructor
71                CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
72                           MipsStaticInst(mnem, _machInst, __opClass)
73                {
74                }
75
76                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
77        };
78
79}};
80
81// Basic instruction class execute method template.
82def template CP0Execute {{
83        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
84        {
85                Fault fault = NoFault;
86                %(op_decl)s;
87                %(op_rd)s;
88
89                if (isCoprocessorEnabled(xc, 0)) {
90                    %(code)s;
91
92                    if(fault == NoFault)
93                    {
94                        %(op_wb)s;
95                    }
96                } else {
97                    fault = new CoprocessorUnusableFault(0);
98                }
99                return fault;
100        }
101}};
102
103def template CP1Execute {{
104        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
105        {
106                Fault fault = NoFault;
107                %(op_decl)s;
108                %(op_rd)s;
109
110                if (isCoprocessorEnabled(xc, 1)) {
111                    %(code)s;
112                } else {
113                    fault = new CoprocessorUnusableFault(1);
114                }
115
116                if(fault == NoFault)
117                {
118                    %(op_wb)s;
119                }
120                return fault;
121        }
122}};
123// Basic instruction class execute method template.
124def template ControlTLBExecute {{
125        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
126        {
127            Fault fault = NoFault;
128            %(op_decl)s;
129            %(op_rd)s;
130
131            if (FullSystem) {
132                if (isCoprocessor0Enabled(xc)) {
133                    if(isMMUTLB(xc)){
134                        %(code)s;
135                    } else {
136                        fault = new ReservedInstructionFault();
137                    }
138                } else {
139                    fault = new CoprocessorUnusableFault(0);
140                }
141            } else { // Syscall Emulation Mode - No TLB Instructions
142                fault = new ReservedInstructionFault();
143            }
144
145            if (fault == NoFault) {
146                %(op_wb)s;
147            }
148            return fault;
149        }
150}};
151
152//Outputs to decoder.cc
153output decoder {{
154        std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
155        {
156            std::stringstream ss;
157            ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
158            return ss.str();
159        }
160        std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const
161        {
162            std::stringstream ss;
163            ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
164            return ss.str();
165        }
166        std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
167        {
168            std::stringstream ss;
169            ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
170            return ss.str();
171        }
172
173}};
174
175output exec {{
176        bool
177        isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
178        {
179            if (!FullSystem)
180                return true;
181
182            MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
183            if (cop_num == 0) {
184                MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
185                // In Stat, EXL, ERL or CU0 set, CP0 accessible
186                // In Dbg, DM bit set, CP0 accessible
187                // In Stat, KSU = 0, kernel mode is base mode
188                return (Stat & 0x10000006) ||
189                       (Dbg & 0x40000000) ||
190                       !(Stat & 0x00000018);
191            } else if (cop_num < 4) {
192                return Stat & (0x10000000 << cop_num); // CU is reset
193            } else {
194                panic("Invalid Coprocessor Number Specified");
195            }
196        }
197
198        bool inline
199        isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
200        {
201            if (FullSystem) {
202                MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
203                MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
204                // In Stat, EXL, ERL or CU0 set, CP0 accessible
205                // In Dbg, DM bit set, CP0 accessible
206                // In Stat KSU = 0, kernel mode is base mode
207                return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
208                    !(Stat & 0x00000018);
209            } else {
210                return true;
211            }
212        }
213
214        bool
215        isMMUTLB(%(CPU_exec_context)s *xc)
216        {
217            MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
218            return FullSystem && (Config & 0x380) == 0x80;
219        }
220}};
221
222def format CP0Control(code, *flags) {{
223    flags += ('IsNonSpeculative', )
224    iop = InstObjParams(name, Name, 'CP0Control', code, flags)
225    header_output = BasicDeclare.subst(iop)
226    decoder_output = BasicConstructor.subst(iop)
227    decode_block = BasicDecode.subst(iop)
228    exec_output = CP0Execute.subst(iop)
229}};
230def format CP0TLB(code, *flags) {{
231    flags += ('IsNonSpeculative', )
232    iop = InstObjParams(name, Name, 'CP0Control', code, flags)
233    header_output = BasicDeclare.subst(iop)
234    decoder_output = BasicConstructor.subst(iop)
235    decode_block = BasicDecode.subst(iop)
236    exec_output = ControlTLBExecute.subst(iop)
237}};
238def format CP1Control(code, *flags) {{
239    flags += ('IsNonSpeculative', )
240    iop = InstObjParams(name, Name, 'CP1Control', code, flags)
241    header_output = BasicDeclare.subst(iop)
242    decoder_output = BasicConstructor.subst(iop)
243    decode_block = BasicDecode.subst(iop)
244    exec_output = CP1Execute.subst(iop)
245}};
246
247
248