control.isa revision 5268:5bfc53fe60e7 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30//          Jaidev Patwardhan
31
32////////////////////////////////////////////////////////////////////
33//
34// Coprocessor instructions
35//
36
37//Outputs to decoder.hh
38output header {{
39
40        class CP0Control : public MipsStaticInst
41        {
42                protected:
43
44                /// Constructor
45                CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
46                           MipsStaticInst(mnem, _machInst, __opClass)
47                {
48                }
49
50                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
51        };
52        class CP0TLB : public MipsStaticInst
53        {
54                protected:
55
56                /// Constructor
57                CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) :
58                           MipsStaticInst(mnem, _machInst, __opClass)
59                {
60                }
61
62                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
63        };
64
65
66        class CP1Control : public MipsStaticInst
67        {
68                protected:
69
70                /// Constructor
71                CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
72                           MipsStaticInst(mnem, _machInst, __opClass)
73                {
74                }
75
76                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
77        };
78
79}};
80
81// Basic instruction class execute method template.
82def template CP0Execute {{
83        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
84        {
85                Fault fault = NoFault;
86                %(op_decl)s;
87                %(op_rd)s;
88
89                if (isCoprocessorEnabled(xc, 0)) {
90                    %(code)s;
91                } else {
92                    fault = new CoprocessorUnusableFault(0);
93                }
94
95                if(fault == NoFault)
96                {
97                    %(op_wb)s;
98                }
99                return fault;
100        }
101}};
102
103def template CP1Execute {{
104        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
105        {
106                Fault fault = NoFault;
107                %(op_decl)s;
108                %(op_rd)s;
109
110                if (isCoprocessorEnabled(xc, 1)) {
111                    %(code)s;
112                } else {
113                    fault = new CoprocessorUnusableFault(1);
114                }
115
116                if(fault == NoFault)
117                {
118                    %(op_wb)s;
119                }
120                return fault;
121        }
122}};
123// Basic instruction class execute method template.
124def template ControlTLBExecute {{
125        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
126        {
127                Fault fault = NoFault;
128                %(op_decl)s;
129                %(op_rd)s;
130
131#if FULL_SYSTEM
132                if (isCoprocessor0Enabled(xc)) {
133                  if(isMMUTLB(xc)){
134                      %(code)s;
135                  } else {
136                    fault = new ReservedInstructionFault();
137                  }
138                } else {
139                  fault = new CoprocessorUnusableFault(0);
140                }
141#else // Syscall Emulation Mode - No TLB Instructions
142                fault = new ReservedInstructionFault();
143#endif
144
145                if(fault == NoFault)
146                {
147                    %(op_wb)s;
148                }
149                return fault;
150
151        }
152}};
153
154//Outputs to decoder.cc
155output decoder {{
156        std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
157        {
158            std::stringstream ss;
159            ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
160            return ss.str();
161        }
162        std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const
163        {
164            std::stringstream ss;
165            ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
166            return ss.str();
167        }
168        std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
169        {
170            std::stringstream ss;
171            ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
172            return ss.str();
173        }
174
175}};
176
177output exec {{
178        bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
179        {
180#if !FULL_SYSTEM
181            return true;
182#else
183          MiscReg Stat = xc->readMiscReg(MipsISA::Status);
184          switch(cop_num)
185            {
186            case 0:
187              {
188                  MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
189                  if((Stat & 0x10000006) == 0  // EXL, ERL or CU0 set, CP0 accessible
190                     && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
191                     && (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
192                      // Unable to use Status_CU0, etc directly, using bitfields & masks
193                      return false;
194                  }
195
196              }
197              break;
198            case 1:
199              if((Stat & 0x20000000) == 0) // CU1 is reset
200                return false;
201              break;
202            case 2:
203              if((Stat & 0x40000000) == 0) // CU2 is reset
204                return false;
205              break;
206            case 3:
207              if((Stat & 0x80000000) == 0) // CU3 is reset
208                return false;
209              break;
210            default: panic("Invalid Coprocessor Number Specified");
211              break;
212            }
213            return true;
214#endif
215        }
216        bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
217        {
218#if FULL_SYSTEM
219          MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status);
220          MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug);
221          if((Stat & 0x10000006) == 0  // EXL, ERL or CU0 set, CP0 accessible
222                 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
223                 && (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
224                // Unable to use Status_CU0, etc directly, using bitfields & masks
225                  return false;
226              }
227#else
228              //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
229#endif
230            return true;
231        }
232        bool isMMUTLB(%(CPU_exec_context)s *xc)
233        {
234#if FULL_SYSTEM
235          if((xc->readMiscRegNoEffect(MipsISA::Config) & 0x00000380)==0x80)
236            return true;
237#endif
238          return false;
239        }
240}};
241
242def format CP0Control(code, *flags) {{
243    flags += ('IsNonSpeculative', )
244    iop = InstObjParams(name, Name, 'CP0Control', code, flags)
245    header_output = BasicDeclare.subst(iop)
246    decoder_output = BasicConstructor.subst(iop)
247    decode_block = BasicDecode.subst(iop)
248    exec_output = CP0Execute.subst(iop)
249}};
250def format CP0TLB(code, *flags) {{
251    flags += ('IsNonSpeculative', )
252    iop = InstObjParams(name, Name, 'CP0Control', code, flags)
253    header_output = BasicDeclare.subst(iop)
254    decoder_output = BasicConstructor.subst(iop)
255    decode_block = BasicDecode.subst(iop)
256    exec_output = ControlTLBExecute.subst(iop)
257}};
258def format CP1Control(code, *flags) {{
259    flags += ('IsNonSpeculative', )
260    iop = InstObjParams(name, Name, 'CP1Control', code, flags)
261    header_output = BasicDeclare.subst(iop)
262    decoder_output = BasicConstructor.subst(iop)
263    decode_block = BasicDecode.subst(iop)
264    exec_output = CP1Execute.subst(iop)
265}};
266
267
268