control.isa revision 4661:44458219add1 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Coprocessor instructions
34//
35
36//Outputs to decoder.hh
37output header {{
38
39        class CP0Control : public MipsStaticInst
40        {
41                protected:
42
43                /// Constructor
44                CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
45                           MipsStaticInst(mnem, _machInst, __opClass)
46                {
47                }
48
49                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
50        };
51
52        class CP1Control : public MipsStaticInst
53        {
54                protected:
55
56                /// Constructor
57                CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
58                           MipsStaticInst(mnem, _machInst, __opClass)
59                {
60                }
61
62                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
63        };
64
65}};
66
67// Basic instruction class execute method template.
68def template ControlExecute {{
69        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
70        {
71                Fault fault = NoFault;
72                %(op_decl)s;
73                %(op_rd)s;
74
75                if (isCoprocessorEnabled(xc, 0)) {
76                    %(code)s;
77                } else {
78                    fault = new CoprocessorUnusableFault();
79                }
80
81                if(fault == NoFault)
82                {
83                    %(op_wb)s;
84                }
85                return fault;
86        }
87}};
88
89//Outputs to decoder.cc
90output decoder {{
91        std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
92        {
93            std::stringstream ss;
94            ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
95            return ss.str();
96        }
97
98        std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
99        {
100            std::stringstream ss;
101            ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
102            return ss.str();
103        }
104
105}};
106
107output exec {{
108        bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
109        {
110          switch(cop_num)
111            {
112            case 0:
113#if FULL_SYSTEM
114              if((xc->readMiscReg(MipsISA::Status) & 0x10000006) == 0 && (xc->readMiscReg(MipsISA::Debug) & 0x40000000 ) == 0) {
115                  // Unable to use Status_CU0, etc directly, using bitfields & masks
116                  return false;
117              }
118#else
119              //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
120#endif
121              break;
122            case 1:
123              break;
124            case 2:
125              break;
126            case 3:
127              break;
128            default: panic("Invalid Coprocessor Number Specified");
129              break;
130            }
131            return true;
132        }
133}};
134
135def format CP0Control(code, *flags) {{
136    flags += ('IsNonSpeculative', )
137    iop = InstObjParams(name, Name, 'CP0Control', code, flags)
138    header_output = BasicDeclare.subst(iop)
139    decoder_output = BasicConstructor.subst(iop)
140    decode_block = BasicDecode.subst(iop)
141    exec_output = ControlExecute.subst(iop)
142}};
143
144def format CP1Control(code, *flags) {{
145    flags += ('IsNonSpeculative', )
146    iop = InstObjParams(name, Name, 'CP1Control', code, flags)
147    header_output = BasicDeclare.subst(iop)
148    decoder_output = BasicConstructor.subst(iop)
149    decode_block = BasicDecode.subst(iop)
150    exec_output = ControlExecute.subst(iop)
151}};
152
153
154