xref: /gem5/src/arch/mips/isa/formats/control.isa

// -*- mode:c++ -*-

// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Korey Sewell

////////////////////////////////////////////////////////////////////
//
// Coprocessor instructions
//

//Outputs to decoder.hh
output header {{

        class CP0Control : public MipsStaticInst
        {
                protected:

                /// Constructor
                CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
                           MipsStaticInst(mnem, _machInst, __opClass)
                {
                }

                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
        };

        class CP1Control : public MipsStaticInst
        {
                protected:

                /// Constructor
                CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
                           MipsStaticInst(mnem, _machInst, __opClass)
                {
                }

                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
        };

}};

// Basic instruction class execute method template.
def template ControlExecute {{
        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
        {
                Fault fault = NoFault;
                %(op_decl)s;
                %(op_rd)s;

                if (isCoprocessorEnabled(xc, 0)) {
                    %(code)s;
                } else {
                    fault = new CoprocessorUnusableFault();
                }

                if(fault == NoFault)
                {
                    %(op_wb)s;
                }
                return fault;
        }
}};

//Outputs to decoder.cc
output decoder {{
        std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
        {
            std::stringstream ss;
            ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
            return ss.str();
        }

        std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
        {
            std::stringstream ss;
            ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
            return ss.str();
        }

}};

output exec {{
        bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
        {
          switch(cop_num)
            {
            case 0:
#if FULL_SYSTEM
              if((xc->readMiscReg(MipsISA::Status) & 0x10000006) == 0 && (xc->readMiscReg(MipsISA::Debug) & 0x40000000 ) == 0) {
                  // Unable to use Status_CU0, etc directly, using bitfields & masks
                  return false;
              }
#else
              //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
#endif
              break;
            case 1:
              break;
            case 2:
              break;
            case 3:
              break;
            default: panic("Invalid Coprocessor Number Specified");
              break;
            }
            return true;
        }
}};

def format CP0Control(code, *flags) {{
    flags += ('IsNonSpeculative', )
    iop = InstObjParams(name, Name, 'CP0Control', code, flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = ControlExecute.subst(iop)
}};

def format CP1Control(code, *flags) {{
    flags += ('IsNonSpeculative', )
    iop = InstObjParams(name, Name, 'CP1Control', code, flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = ControlExecute.subst(iop)
}};