xref: /gem5/src/arch/mips/isa/formats/control.isa

// -*- mode:c++ -*-

// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Korey Sewell

////////////////////////////////////////////////////////////////////
//
// Integer operate instructions
//

//Outputs to decoder.hh
output header {{

        class Control : public MipsStaticInst
        {
                protected:

                /// Constructor
                Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
                           MipsStaticInst(mnem, _machInst, __opClass)
                {
                }

                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
        };

        class CP0Control : public Control
        {
                protected:

                /// Constructor
                CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
                           Control(mnem, _machInst, __opClass)
                {
                }

                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
        };

        class CP1Control : public Control
        {
                protected:

                /// Constructor
                CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
                           Control(mnem, _machInst, __opClass)
                {
                }

                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
        };

}};

//Outputs to decoder.cc
output decoder {{
        std::string Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
        {
            std::stringstream ss;

            ccprintf(ss, "%-10s ", mnemonic);

            if (mnemonic == "mfc0" || mnemonic == "mtc0") {
                ccprintf(ss, "%-10s %d,%d,%d", mnemonic,RT,RD,SEL);
            } else {

                // just print the first dest... if there's a second one,
                // it's generally implicit
                if (_numDestRegs > 0) {
                    printReg(ss, _destRegIdx[0]);
                }

                ss << ", ";

                // just print the first two source regs... if there's
                // a third one, it's a read-modify-write dest (Rc),
                // e.g. for CMOVxx
                if (_numSrcRegs > 0) {
                    printReg(ss, _srcRegIdx[0]);
                }

                if (_numSrcRegs > 1) {
                    ss << ", ";
                    printReg(ss, _srcRegIdx[1]);
                }
            }

            return ss.str();
        }

        std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
        {
            std::stringstream ss;
            ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
            return ss.str();
        }

        std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
        {
            std::stringstream ss;
            ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
            return ss.str();
        }

}};

def format System(code, *flags) {{
        iop = InstObjParams(name, Name, 'Control', CodeBlock(code), flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        decode_block = BasicDecode.subst(iop)
        exec_output = BasicExecute.subst(iop)
}};

def format CP0Control(code, *flags) {{
        iop = InstObjParams(name, Name, 'CP0Control', CodeBlock(code), flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        decode_block = BasicDecode.subst(iop)
        exec_output = BasicExecute.subst(iop)
}};

def format CP1Control(code, *flags) {{
        iop = InstObjParams(name, Name, 'CP1Control', CodeBlock(code), flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        decode_block = BasicDecode.subst(iop)
        exec_output = BasicExecute.subst(iop)
}};