branch.isa revision 5268:5bfc53fe60e7 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Control transfer instructions
34//
35
36output header {{
37
38#include <iostream>
39    using namespace std;
40
41    /**
42     * Base class for instructions whose disassembly is not purely a
43     * function of the machine instruction (i.e., it depends on the
44     * PC).  This class overrides the disassemble() method to check
45     * the PC and symbol table values before re-using a cached
46     * disassembly string.  This is necessary for branches and jumps,
47     * where the disassembly string includes the target address (which
48     * may depend on the PC and/or symbol table).
49     */
50    class PCDependentDisassembly : public MipsStaticInst
51    {
52      protected:
53        /// Cached program counter from last disassembly
54        mutable Addr cachedPC;
55
56        /// Cached symbol table pointer from last disassembly
57        mutable const SymbolTable *cachedSymtab;
58
59        /// Constructor
60        PCDependentDisassembly(const char *mnem, MachInst _machInst,
61                               OpClass __opClass)
62            : MipsStaticInst(mnem, _machInst, __opClass),
63              cachedPC(0), cachedSymtab(0)
64        {
65        }
66
67        const std::string &
68        disassemble(Addr pc, const SymbolTable *symtab) const;
69    };
70
71    /**
72     * Base class for branches (PC-relative control transfers),
73     * conditional or unconditional.
74     */
75    class Branch : public PCDependentDisassembly
76    {
77      protected:
78        /// target address (signed) Displacement .
79        int32_t disp;
80
81        /// Constructor.
82        Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
83            : PCDependentDisassembly(mnem, _machInst, __opClass),
84              disp(OFFSET << 2)
85        {
86            //If Bit 17 is 1 then Sign Extend
87            if ( (disp & 0x00020000) > 0  ) {
88                disp |= 0xFFFE0000;
89            }
90        }
91
92        Addr branchTarget(Addr branchPC) const;
93
94        std::string
95        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
96    };
97
98    /**
99     * Base class for jumps (register-indirect control transfers).  In
100     * the Mips ISA, these are always unconditional.
101     */
102    class Jump : public PCDependentDisassembly
103    {
104      protected:
105
106        /// Displacement to target address (signed).
107        int32_t disp;
108
109        uint32_t target;
110
111      public:
112        /// Constructor
113        Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
114            : PCDependentDisassembly(mnem, _machInst, __opClass),
115              disp(JMPTARG << 2)
116        {
117        }
118
119        Addr branchTarget(ThreadContext *tc) const;
120
121        std::string
122        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
123    };
124}};
125
126output decoder {{
127    Addr
128    Branch::branchTarget(Addr branchPC) const
129    {
130        return branchPC + 4 + disp;
131    }
132
133    Addr
134    Jump::branchTarget(ThreadContext *tc) const
135    {
136      Addr NPC = tc->readNextPC();
137      return (NPC & 0xF0000000) | (disp);
138    }
139
140    const std::string &
141    PCDependentDisassembly::disassemble(Addr pc,
142                                        const SymbolTable *symtab) const
143    {
144        if (!cachedDisassembly ||
145            pc != cachedPC || symtab != cachedSymtab)
146        {
147            if (cachedDisassembly)
148                delete cachedDisassembly;
149
150            cachedDisassembly =
151                new std::string(generateDisassembly(pc, symtab));
152            cachedPC = pc;
153            cachedSymtab = symtab;
154        }
155
156        return *cachedDisassembly;
157    }
158
159    std::string
160    Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
161    {
162        std::stringstream ss;
163
164        ccprintf(ss, "%-10s ", mnemonic);
165
166        // There's only one register arg (RA), but it could be
167        // either a source (the condition for conditional
168        // branches) or a destination (the link reg for
169        // unconditional branches)
170        if (_numSrcRegs == 1) {
171            printReg(ss, _srcRegIdx[0]);
172            ss << ", ";
173        } else if(_numSrcRegs == 2) {
174            printReg(ss, _srcRegIdx[0]);
175            ss << ", ";
176            printReg(ss, _srcRegIdx[1]);
177            ss << ", ";
178        }
179
180        Addr target = pc + 4 + disp;
181
182        std::string str;
183        if (symtab && symtab->findSymbol(target, str))
184            ss << str;
185        else
186            ccprintf(ss, "0x%x", target);
187
188        return ss.str();
189    }
190
191    std::string
192    Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
193    {
194        std::stringstream ss;
195
196        ccprintf(ss, "%-10s ", mnemonic);
197
198        if ( mnemonic == "jal" ) {
199            Addr npc = pc + 4;
200            ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
201        } else if (_numSrcRegs == 0) {
202            std::string str;
203            if (symtab && symtab->findSymbol(disp, str))
204                ss << str;
205            else
206                ccprintf(ss, "0x%x", disp);
207        } else if (_numSrcRegs == 1) {
208             printReg(ss, _srcRegIdx[0]);
209        } else if(_numSrcRegs == 2) {
210            printReg(ss, _srcRegIdx[0]);
211            ss << ", ";
212            printReg(ss, _srcRegIdx[1]);
213        }
214
215        return ss.str();
216    }
217}};
218
219def format Branch(code, *opt_flags) {{
220    not_taken_code = '  NNPC = NNPC;\n'
221    not_taken_code += '} \n'
222
223    #Build Instruction Flags
224    #Use Link & Likely Flags to Add Link/Condition Code
225    inst_flags = ('IsDirectControl', )
226    for x in opt_flags:
227        if x == 'Link':
228            code += 'R31 = NNPC;\n'
229        elif x == 'Likely':
230            not_taken_code = '  NPC = NNPC;\n'
231            not_taken_code += '  NNPC = NNPC + 4;\n'
232            not_taken_code += '} \n'
233            inst_flags += ('IsCondDelaySlot', )
234        else:
235            inst_flags += (x, )
236
237    #Take into account uncond. branch instruction
238    if 'cond = 1' in code:
239         inst_flags += ('IsUncondControl', )
240    else:
241         inst_flags += ('IsCondControl', )
242
243    #Condition code
244    code = 'bool cond;\n' + code
245    code += 'if (cond) {\n'
246    code += '  NNPC = NPC + disp;\n'
247    code += '} else {\n'
248    code += not_taken_code
249
250    iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
251    header_output = BasicDeclare.subst(iop)
252    decoder_output = BasicConstructor.subst(iop)
253    decode_block = BasicDecode.subst(iop)
254    exec_output = BasicExecute.subst(iop)
255}};
256
257def format DspBranch(code, *opt_flags) {{
258    not_taken_code = '  NNPC = NNPC;\n'
259    not_taken_code += '} \n'
260
261    #Build Instruction Flags
262    #Use Link & Likely Flags to Add Link/Condition Code
263    inst_flags = ('IsDirectControl', )
264    for x in opt_flags:
265        if x == 'Link':
266            code += 'R31 = NNPC;\n'
267        elif x == 'Likely':
268            not_taken_code = '  NPC = NNPC;\n'
269            not_taken_code += '  NNPC = NNPC + 4;\n'
270            not_taken_code += '} \n'
271            inst_flags += ('IsCondDelaySlot', )
272        else:
273            inst_flags += (x, )
274
275    #Take into account uncond. branch instruction
276    if 'cond = 1' in code:
277         inst_flags += ('IsUncondControl', )
278    else:
279         inst_flags += ('IsCondControl', )
280
281    #Declaration code
282    decl_code = 'bool cond;\n'
283    decl_code += 'uint32_t dspctl;\n'
284
285    #Fetch code
286    fetch_code = 'dspctl = DSPControl;\n'
287
288    #Condition code
289    code = decl_code + fetch_code + code
290    code += 'if (cond) {\n'
291    code += '  NNPC = NPC + disp;\n'
292    code += '} else {\n'
293    code += not_taken_code
294
295    iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
296    header_output = BasicDeclare.subst(iop)
297    decoder_output = BasicConstructor.subst(iop)
298    decode_block = BasicDecode.subst(iop)
299    exec_output = BasicExecute.subst(iop)
300}};
301
302def format Jump(code, *opt_flags) {{
303    #Build Instruction Flags
304    #Use Link Flag to Add Link Code
305    inst_flags = ('IsIndirectControl', 'IsUncondControl')
306    for x in opt_flags:
307        if x == 'Link':
308            code = 'R31 = NNPC;\n' + code
309        elif x == 'ClearHazards':
310            code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
311        else:
312            inst_flags += (x, )
313
314    iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
315    header_output = BasicDeclare.subst(iop)
316    decoder_output = BasicConstructor.subst(iop)
317    decode_block = BasicDecode.subst(iop)
318    exec_output = BasicExecute.subst(iop)
319}};
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