branch.isa revision 2980:eab855f06b79 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Control transfer instructions
34//
35
36output header {{
37
38#include <iostream>
39
40    /**
41     * Base class for instructions whose disassembly is not purely a
42     * function of the machine instruction (i.e., it depends on the
43     * PC).  This class overrides the disassemble() method to check
44     * the PC and symbol table values before re-using a cached
45     * disassembly string.  This is necessary for branches and jumps,
46     * where the disassembly string includes the target address (which
47     * may depend on the PC and/or symbol table).
48     */
49    class PCDependentDisassembly : public MipsStaticInst
50    {
51      protected:
52        /// Cached program counter from last disassembly
53        mutable Addr cachedPC;
54
55        /// Cached symbol table pointer from last disassembly
56        mutable const SymbolTable *cachedSymtab;
57
58        /// Constructor
59        PCDependentDisassembly(const char *mnem, MachInst _machInst,
60                               OpClass __opClass)
61            : MipsStaticInst(mnem, _machInst, __opClass),
62              cachedPC(0), cachedSymtab(0)
63        {
64        }
65
66        const std::string &
67        disassemble(Addr pc, const SymbolTable *symtab) const;
68    };
69
70    /**
71     * Base class for branches (PC-relative control transfers),
72     * conditional or unconditional.
73     */
74    class Branch : public PCDependentDisassembly
75    {
76      protected:
77        /// target address (signed) Displacement .
78        int32_t disp;
79
80        /// Constructor.
81        Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
82            : PCDependentDisassembly(mnem, _machInst, __opClass),
83              disp(OFFSET << 2)
84        {
85            //If Bit 17 is 1 then Sign Extend
86            if ( (disp & 0x00020000) > 0  ) {
87                disp |= 0xFFFE0000;
88            }
89        }
90
91        Addr branchTarget(Addr branchPC) const;
92
93        std::string
94        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
95    };
96
97    /**
98     * Base class for jumps (register-indirect control transfers).  In
99     * the Mips ISA, these are always unconditional.
100     */
101    class Jump : public PCDependentDisassembly
102    {
103      protected:
104
105        /// Displacement to target address (signed).
106        int32_t disp;
107
108        uint32_t target;
109
110      public:
111        /// Constructor
112        Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
113            : PCDependentDisassembly(mnem, _machInst, __opClass),
114              disp(JMPTARG << 2)
115        {
116        }
117
118        Addr branchTarget(ThreadContext *tc) const;
119
120        std::string
121        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
122    };
123}};
124
125output decoder {{
126    Addr
127    Branch::branchTarget(Addr branchPC) const
128    {
129        return branchPC + 4 + disp;
130    }
131
132    Addr
133    Jump::branchTarget(ThreadContext *tc) const
134    {
135        Addr NPC = tc->readPC() + 4;
136        uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
137        return (Rb & ~3) | (NPC & 1);
138    }
139
140    const std::string &
141    PCDependentDisassembly::disassemble(Addr pc,
142                                        const SymbolTable *symtab) const
143    {
144        if (!cachedDisassembly ||
145            pc != cachedPC || symtab != cachedSymtab)
146        {
147            if (cachedDisassembly)
148                delete cachedDisassembly;
149
150            cachedDisassembly =
151                new std::string(generateDisassembly(pc, symtab));
152            cachedPC = pc;
153            cachedSymtab = symtab;
154        }
155
156        return *cachedDisassembly;
157    }
158
159    std::string
160    Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
161    {
162        std::stringstream ss;
163
164        ccprintf(ss, "%-10s ", mnemonic);
165
166        // There's only one register arg (RA), but it could be
167        // either a source (the condition for conditional
168        // branches) or a destination (the link reg for
169        // unconditional branches)
170        if (_numSrcRegs == 1) {
171            printReg(ss, _srcRegIdx[0]);
172            ss << ", ";
173        } else if(_numSrcRegs == 2) {
174            printReg(ss, _srcRegIdx[0]);
175            ss << ", ";
176            printReg(ss, _srcRegIdx[1]);
177            ss << ", ";
178        }
179
180        Addr target = pc + 4 + disp;
181
182        std::string str;
183        if (symtab && symtab->findSymbol(target, str))
184            ss << str;
185        else
186            ccprintf(ss, "0x%x", target);
187
188        return ss.str();
189    }
190
191    std::string
192    Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
193    {
194        std::stringstream ss;
195
196        ccprintf(ss, "%-10s ", mnemonic);
197
198        if ( mnemonic == "jal" ) {
199            Addr npc = pc + 4;
200            ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
201        } else if (_numSrcRegs == 0) {
202            std::string str;
203            if (symtab && symtab->findSymbol(disp, str))
204                ss << str;
205            else
206                ccprintf(ss, "0x%x", disp);
207        } else if (_numSrcRegs == 1) {
208             printReg(ss, _srcRegIdx[0]);
209        } else if(_numSrcRegs == 2) {
210            printReg(ss, _srcRegIdx[0]);
211            ss << ", ";
212            printReg(ss, _srcRegIdx[1]);
213        }
214
215        return ss.str();
216    }
217}};
218
219def format Branch(code,*opt_flags) {{
220    not_taken_code = '  NNPC = NNPC;\n'
221    not_taken_code += '} \n'
222
223    #Build Instruction Flags
224    #Use Link & Likely Flags to Add Link/Condition Code
225    inst_flags = ('IsDirectControl', )
226    for x in opt_flags:
227        if x == 'Link':
228            code += 'R31 = NNPC;\n'
229        elif x == 'Likely':
230            not_taken_code = '  NPC = NNPC;\n'
231            not_taken_code += '  NNPC = NNPC + 4;\n'
232            not_taken_code += '} \n'
233            inst_flags = ('IsCondDelaySlot', )
234        else:
235            inst_flags += (x, )
236
237    #Take into account uncond. branch instruction
238    if 'cond == 1' in code:
239         inst_flags += ('IsUnCondControl', )
240    else:
241         inst_flags += ('IsCondControl', )
242
243    #Condition code
244    code = 'bool cond;\n' + code
245    code += 'if (cond) {\n'
246    code += '  NNPC = NPC + disp;\n'
247    code += '} else {\n'
248    code += not_taken_code
249
250    iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), inst_flags)
251    header_output = BasicDeclare.subst(iop)
252    decoder_output = BasicConstructor.subst(iop)
253    decode_block = BasicDecode.subst(iop)
254    exec_output = BasicExecute.subst(iop)
255}};
256
257def format Jump(code, *opt_flags) {{
258    #Build Instruction Flags
259    #Use Link Flag to Add Link Code
260    inst_flags = ('IsIndirectControl', 'IsUncondControl')
261    for x in opt_flags:
262        if x == 'Link':
263            code = 'R31 = NNPC;\n' + code
264        elif x == 'ClearHazards':
265            code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
266        else:
267            inst_flags += (x, )
268
269    iop = InstObjParams(name, Name, 'Jump', CodeBlock(code), inst_flags)
270    header_output = BasicDeclare.subst(iop)
271    decoder_output = BasicConstructor.subst(iop)
272    decode_block = BasicDecode.subst(iop)
273    exec_output = BasicExecute.subst(iop)
274}};
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