branch.isa revision 9552
12100SN/A// -*- mode:c++ -*- 22083SN/A 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Korey Sewell 302706Sksewell@umich.edu 312089SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332089SN/A// Control transfer instructions 342022SN/A// 352022SN/A 362022SN/Aoutput header {{ 372083SN/A 382239SN/A#include <iostream> 394661Sksewell@umich.edu using namespace std; 402239SN/A 412083SN/A /** 422083SN/A * Base class for instructions whose disassembly is not purely a 432083SN/A * function of the machine instruction (i.e., it depends on the 442083SN/A * PC). This class overrides the disassemble() method to check 452083SN/A * the PC and symbol table values before re-using a cached 462083SN/A * disassembly string. This is necessary for branches and jumps, 472083SN/A * where the disassembly string includes the target address (which 482083SN/A * may depend on the PC and/or symbol table). 492083SN/A */ 502089SN/A class PCDependentDisassembly : public MipsStaticInst 512083SN/A { 522083SN/A protected: 532083SN/A /// Cached program counter from last disassembly 542083SN/A mutable Addr cachedPC; 552089SN/A 562083SN/A /// Cached symbol table pointer from last disassembly 572083SN/A mutable const SymbolTable *cachedSymtab; 582083SN/A 592083SN/A /// Constructor 602083SN/A PCDependentDisassembly(const char *mnem, MachInst _machInst, 612083SN/A OpClass __opClass) 622089SN/A : MipsStaticInst(mnem, _machInst, __opClass), 632083SN/A cachedPC(0), cachedSymtab(0) 642022SN/A { 652083SN/A } 662022SN/A 672083SN/A const std::string & 682083SN/A disassemble(Addr pc, const SymbolTable *symtab) const; 692083SN/A }; 702022SN/A 712083SN/A /** 722083SN/A * Base class for branches (PC-relative control transfers), 732083SN/A * conditional or unconditional. 742083SN/A */ 752083SN/A class Branch : public PCDependentDisassembly 762083SN/A { 772083SN/A protected: 782089SN/A /// target address (signed) Displacement . 792104SN/A int32_t disp; 802083SN/A 812083SN/A /// Constructor. 822083SN/A Branch(const char *mnem, MachInst _machInst, OpClass __opClass) 832083SN/A : PCDependentDisassembly(mnem, _machInst, __opClass), 842104SN/A disp(OFFSET << 2) 852089SN/A { 862239SN/A //If Bit 17 is 1 then Sign Extend 872239SN/A if ( (disp & 0x00020000) > 0 ) { 882239SN/A disp |= 0xFFFE0000; 892239SN/A } 902089SN/A } 912089SN/A 927720Sgblack@eecs.umich.edu MipsISA::PCState branchTarget(const MipsISA::PCState &branchPC) const; 932089SN/A 949552Sandreas.hansson@arm.com /// Explicitly import the otherwise hidden branchTarget 959552Sandreas.hansson@arm.com using StaticInst::branchTarget; 969552Sandreas.hansson@arm.com 972089SN/A std::string 982089SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 992089SN/A }; 1002089SN/A 1012089SN/A /** 1022083SN/A * Base class for jumps (register-indirect control transfers). In 1032089SN/A * the Mips ISA, these are always unconditional. 1042083SN/A */ 1052083SN/A class Jump : public PCDependentDisassembly 1062083SN/A { 1072083SN/A protected: 1082083SN/A 1092083SN/A /// Displacement to target address (signed). 1102083SN/A int32_t disp; 1112083SN/A 1122239SN/A uint32_t target; 1132239SN/A 1142083SN/A public: 1152083SN/A /// Constructor 1162083SN/A Jump(const char *mnem, MachInst _machInst, OpClass __opClass) 1172083SN/A : PCDependentDisassembly(mnem, _machInst, __opClass), 1182239SN/A disp(JMPTARG << 2) 1192083SN/A { 1202083SN/A } 1212083SN/A 1227720Sgblack@eecs.umich.edu MipsISA::PCState branchTarget(ThreadContext *tc) const; 1232083SN/A 1249552Sandreas.hansson@arm.com /// Explicitly import the otherwise hidden branchTarget 1259552Sandreas.hansson@arm.com using StaticInst::branchTarget; 1269552Sandreas.hansson@arm.com 1272083SN/A std::string 1282083SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1292083SN/A }; 1302022SN/A}}; 1312022SN/A 1322022SN/Aoutput decoder {{ 1337720Sgblack@eecs.umich.edu MipsISA::PCState 1347720Sgblack@eecs.umich.edu Branch::branchTarget(const MipsISA::PCState &branchPC) const 1352083SN/A { 1367720Sgblack@eecs.umich.edu MipsISA::PCState target = branchPC; 1377720Sgblack@eecs.umich.edu target.advance(); 1387720Sgblack@eecs.umich.edu target.npc(branchPC.pc() + sizeof(MachInst) + disp); 1397720Sgblack@eecs.umich.edu target.nnpc(target.npc() + sizeof(MachInst)); 1407720Sgblack@eecs.umich.edu return target; 1412083SN/A } 1422083SN/A 1437720Sgblack@eecs.umich.edu MipsISA::PCState 1442687Sksewell@umich.edu Jump::branchTarget(ThreadContext *tc) const 1452083SN/A { 1467720Sgblack@eecs.umich.edu MipsISA::PCState target = tc->pcState(); 1477720Sgblack@eecs.umich.edu Addr pc = target.pc(); 1487720Sgblack@eecs.umich.edu target.advance(); 1497720Sgblack@eecs.umich.edu target.npc((pc & 0xF0000000) | disp); 1507720Sgblack@eecs.umich.edu target.nnpc(target.npc() + sizeof(MachInst)); 1517720Sgblack@eecs.umich.edu return target; 1522083SN/A } 1532083SN/A 1542083SN/A const std::string & 1552083SN/A PCDependentDisassembly::disassemble(Addr pc, 1562083SN/A const SymbolTable *symtab) const 1572083SN/A { 1582083SN/A if (!cachedDisassembly || 1592083SN/A pc != cachedPC || symtab != cachedSymtab) 1602022SN/A { 1612083SN/A if (cachedDisassembly) 1622083SN/A delete cachedDisassembly; 1632083SN/A 1642083SN/A cachedDisassembly = 1652083SN/A new std::string(generateDisassembly(pc, symtab)); 1662083SN/A cachedPC = pc; 1672083SN/A cachedSymtab = symtab; 1682022SN/A } 1692083SN/A 1702083SN/A return *cachedDisassembly; 1712083SN/A } 1722083SN/A 1732083SN/A std::string 1742083SN/A Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1752083SN/A { 1762083SN/A std::stringstream ss; 1772083SN/A 1782083SN/A ccprintf(ss, "%-10s ", mnemonic); 1792083SN/A 1802083SN/A // There's only one register arg (RA), but it could be 1812083SN/A // either a source (the condition for conditional 1822083SN/A // branches) or a destination (the link reg for 1832083SN/A // unconditional branches) 1842239SN/A if (_numSrcRegs == 1) { 1852083SN/A printReg(ss, _srcRegIdx[0]); 1862686Sksewell@umich.edu ss << ", "; 1872239SN/A } else if(_numSrcRegs == 2) { 1882239SN/A printReg(ss, _srcRegIdx[0]); 1892686Sksewell@umich.edu ss << ", "; 1902239SN/A printReg(ss, _srcRegIdx[1]); 1912686Sksewell@umich.edu ss << ", "; 1922103SN/A } 1932103SN/A 1942103SN/A Addr target = pc + 4 + disp; 1952103SN/A 1962103SN/A std::string str; 1972103SN/A if (symtab && symtab->findSymbol(target, str)) 1982103SN/A ss << str; 1992103SN/A else 2002103SN/A ccprintf(ss, "0x%x", target); 2012103SN/A 2022103SN/A return ss.str(); 2032103SN/A } 2042103SN/A 2052103SN/A std::string 2062083SN/A Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2072083SN/A { 2082083SN/A std::stringstream ss; 2092083SN/A 2102083SN/A ccprintf(ss, "%-10s ", mnemonic); 2112083SN/A 2125269Sksewell@umich.edu if ( strcmp(mnemonic,"jal") == 0 ) { 2132239SN/A Addr npc = pc + 4; 2142239SN/A ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp); 2152239SN/A } else if (_numSrcRegs == 0) { 2162239SN/A std::string str; 2172239SN/A if (symtab && symtab->findSymbol(disp, str)) 2182239SN/A ss << str; 2192239SN/A else 2202239SN/A ccprintf(ss, "0x%x", disp); 2212239SN/A } else if (_numSrcRegs == 1) { 2222239SN/A printReg(ss, _srcRegIdx[0]); 2232239SN/A } else if(_numSrcRegs == 2) { 2242239SN/A printReg(ss, _srcRegIdx[0]); 2252686Sksewell@umich.edu ss << ", "; 2262239SN/A printReg(ss, _srcRegIdx[1]); 2272083SN/A } 2282083SN/A 2292083SN/A return ss.str(); 2302083SN/A } 2312022SN/A}}; 2322022SN/A 2334661Sksewell@umich.edudef format Branch(code, *opt_flags) {{ 2347792Sgblack@eecs.umich.edu not_taken_code = 'NNPC = NNPC; NPC = NPC;' 2352686Sksewell@umich.edu 2362686Sksewell@umich.edu #Build Instruction Flags 2372686Sksewell@umich.edu #Use Link & Likely Flags to Add Link/Condition Code 2382686Sksewell@umich.edu inst_flags = ('IsDirectControl', ) 2392686Sksewell@umich.edu for x in opt_flags: 2402686Sksewell@umich.edu if x == 'Link': 2417792Sgblack@eecs.umich.edu code += 'R31 = NNPC;\n' 2422686Sksewell@umich.edu elif x == 'Likely': 2437792Sgblack@eecs.umich.edu not_taken_code = 'NNPC = NPC; NPC = PC;' 2444661Sksewell@umich.edu inst_flags += ('IsCondDelaySlot', ) 2452686Sksewell@umich.edu else: 2462686Sksewell@umich.edu inst_flags += (x, ) 2472686Sksewell@umich.edu 2482935Sksewell@umich.edu #Take into account uncond. branch instruction 2494661Sksewell@umich.edu if 'cond = 1' in code: 2504661Sksewell@umich.edu inst_flags += ('IsUncondControl', ) 2512935Sksewell@umich.edu else: 2522686Sksewell@umich.edu inst_flags += ('IsCondControl', ) 2532101SN/A 2542123SN/A #Condition code 2557720Sgblack@eecs.umich.edu code = ''' 2567720Sgblack@eecs.umich.edu bool cond; 2577720Sgblack@eecs.umich.edu %(code)s 2587720Sgblack@eecs.umich.edu if (cond) { 2597792Sgblack@eecs.umich.edu NNPC = NPC + disp; 2607720Sgblack@eecs.umich.edu } else { 2617720Sgblack@eecs.umich.edu %(not_taken_code)s 2627720Sgblack@eecs.umich.edu } 2637720Sgblack@eecs.umich.edu ''' % { "code" : code, "not_taken_code" : not_taken_code } 2642101SN/A 2653951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'Branch', code, inst_flags) 2662047SN/A header_output = BasicDeclare.subst(iop) 2672047SN/A decoder_output = BasicConstructor.subst(iop) 2682047SN/A decode_block = BasicDecode.subst(iop) 2692047SN/A exec_output = BasicExecute.subst(iop) 2702022SN/A}}; 2712047SN/A 2724661Sksewell@umich.edudef format DspBranch(code, *opt_flags) {{ 2737792Sgblack@eecs.umich.edu not_taken_code = 'NNPC = NNPC; NPC = NPC;' 2744661Sksewell@umich.edu 2754661Sksewell@umich.edu #Build Instruction Flags 2764661Sksewell@umich.edu #Use Link & Likely Flags to Add Link/Condition Code 2774661Sksewell@umich.edu inst_flags = ('IsDirectControl', ) 2784661Sksewell@umich.edu for x in opt_flags: 2794661Sksewell@umich.edu if x == 'Link': 2807792Sgblack@eecs.umich.edu code += 'R32 = NNPC;' 2814661Sksewell@umich.edu elif x == 'Likely': 2827792Sgblack@eecs.umich.edu not_taken_code = 'NNPC = NPC, NPC = PC;' 2834661Sksewell@umich.edu inst_flags += ('IsCondDelaySlot', ) 2844661Sksewell@umich.edu else: 2854661Sksewell@umich.edu inst_flags += (x, ) 2864661Sksewell@umich.edu 2874661Sksewell@umich.edu #Take into account uncond. branch instruction 2884661Sksewell@umich.edu if 'cond = 1' in code: 2894661Sksewell@umich.edu inst_flags += ('IsUncondControl', ) 2904661Sksewell@umich.edu else: 2914661Sksewell@umich.edu inst_flags += ('IsCondControl', ) 2924661Sksewell@umich.edu 2934661Sksewell@umich.edu #Condition code 2947720Sgblack@eecs.umich.edu code = ''' 2957720Sgblack@eecs.umich.edu bool cond; 2967720Sgblack@eecs.umich.edu uint32_t dspctl = DSPControl; 2977720Sgblack@eecs.umich.edu %(code)s 2987720Sgblack@eecs.umich.edu if (cond) { 2997792Sgblack@eecs.umich.edu NNPC = NPC + disp; 3007720Sgblack@eecs.umich.edu } else { 3017720Sgblack@eecs.umich.edu %(not_taken_code)s 3027720Sgblack@eecs.umich.edu } 3037720Sgblack@eecs.umich.edu ''' % { "code" : code, "not_taken_code" : not_taken_code } 3044661Sksewell@umich.edu 3054661Sksewell@umich.edu iop = InstObjParams(name, Name, 'Branch', code, inst_flags) 3064661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3074661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3084661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3094661Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3104661Sksewell@umich.edu}}; 3114661Sksewell@umich.edu 3122686Sksewell@umich.edudef format Jump(code, *opt_flags) {{ 3132686Sksewell@umich.edu #Build Instruction Flags 3142686Sksewell@umich.edu #Use Link Flag to Add Link Code 3152686Sksewell@umich.edu inst_flags = ('IsIndirectControl', 'IsUncondControl') 3162686Sksewell@umich.edu for x in opt_flags: 3172686Sksewell@umich.edu if x == 'Link': 3187720Sgblack@eecs.umich.edu code = ''' 3197792Sgblack@eecs.umich.edu R31 = NNPC; 3207720Sgblack@eecs.umich.edu ''' + code 3212686Sksewell@umich.edu elif x == 'ClearHazards': 3222686Sksewell@umich.edu code += '/* Code Needed to Clear Execute & Inst Hazards */\n' 3232686Sksewell@umich.edu else: 3242686Sksewell@umich.edu inst_flags += (x, ) 3252104SN/A 3263951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'Jump', code, inst_flags) 3272089SN/A header_output = BasicDeclare.subst(iop) 3282089SN/A decoder_output = BasicConstructor.subst(iop) 3292089SN/A decode_block = BasicDecode.subst(iop) 3302089SN/A exec_output = BasicExecute.subst(iop) 3312089SN/A}}; 3322083SN/A 3332239SN/A 3342123SN/A 3352123SN/A 336