branch.isa revision 7720
12100SN/A// -*- mode:c++ -*- 22083SN/A 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Korey Sewell 302706Sksewell@umich.edu 312089SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332089SN/A// Control transfer instructions 342022SN/A// 352022SN/A 362022SN/Aoutput header {{ 372083SN/A 382239SN/A#include <iostream> 394661Sksewell@umich.edu using namespace std; 402239SN/A 412083SN/A /** 422083SN/A * Base class for instructions whose disassembly is not purely a 432083SN/A * function of the machine instruction (i.e., it depends on the 442083SN/A * PC). This class overrides the disassemble() method to check 452083SN/A * the PC and symbol table values before re-using a cached 462083SN/A * disassembly string. This is necessary for branches and jumps, 472083SN/A * where the disassembly string includes the target address (which 482083SN/A * may depend on the PC and/or symbol table). 492083SN/A */ 502089SN/A class PCDependentDisassembly : public MipsStaticInst 512083SN/A { 522083SN/A protected: 532083SN/A /// Cached program counter from last disassembly 542083SN/A mutable Addr cachedPC; 552089SN/A 562083SN/A /// Cached symbol table pointer from last disassembly 572083SN/A mutable const SymbolTable *cachedSymtab; 582083SN/A 592083SN/A /// Constructor 602083SN/A PCDependentDisassembly(const char *mnem, MachInst _machInst, 612083SN/A OpClass __opClass) 622089SN/A : MipsStaticInst(mnem, _machInst, __opClass), 632083SN/A cachedPC(0), cachedSymtab(0) 642022SN/A { 652083SN/A } 662022SN/A 672083SN/A const std::string & 682083SN/A disassemble(Addr pc, const SymbolTable *symtab) const; 692083SN/A }; 702022SN/A 712083SN/A /** 722083SN/A * Base class for branches (PC-relative control transfers), 732083SN/A * conditional or unconditional. 742083SN/A */ 752083SN/A class Branch : public PCDependentDisassembly 762083SN/A { 772083SN/A protected: 782089SN/A /// target address (signed) Displacement . 792104SN/A int32_t disp; 802083SN/A 812083SN/A /// Constructor. 822083SN/A Branch(const char *mnem, MachInst _machInst, OpClass __opClass) 832083SN/A : PCDependentDisassembly(mnem, _machInst, __opClass), 842104SN/A disp(OFFSET << 2) 852089SN/A { 862239SN/A //If Bit 17 is 1 then Sign Extend 872239SN/A if ( (disp & 0x00020000) > 0 ) { 882239SN/A disp |= 0xFFFE0000; 892239SN/A } 902089SN/A } 912089SN/A 927720Sgblack@eecs.umich.edu MipsISA::PCState branchTarget(const MipsISA::PCState &branchPC) const; 932089SN/A 942089SN/A std::string 952089SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 962089SN/A }; 972089SN/A 982089SN/A /** 992083SN/A * Base class for jumps (register-indirect control transfers). In 1002089SN/A * the Mips ISA, these are always unconditional. 1012083SN/A */ 1022083SN/A class Jump : public PCDependentDisassembly 1032083SN/A { 1042083SN/A protected: 1052083SN/A 1062083SN/A /// Displacement to target address (signed). 1072083SN/A int32_t disp; 1082083SN/A 1092239SN/A uint32_t target; 1102239SN/A 1112083SN/A public: 1122083SN/A /// Constructor 1132083SN/A Jump(const char *mnem, MachInst _machInst, OpClass __opClass) 1142083SN/A : PCDependentDisassembly(mnem, _machInst, __opClass), 1152239SN/A disp(JMPTARG << 2) 1162083SN/A { 1172083SN/A } 1182083SN/A 1197720Sgblack@eecs.umich.edu MipsISA::PCState branchTarget(ThreadContext *tc) const; 1202083SN/A 1212083SN/A std::string 1222083SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1232083SN/A }; 1242022SN/A}}; 1252022SN/A 1262022SN/Aoutput decoder {{ 1277720Sgblack@eecs.umich.edu MipsISA::PCState 1287720Sgblack@eecs.umich.edu Branch::branchTarget(const MipsISA::PCState &branchPC) const 1292083SN/A { 1307720Sgblack@eecs.umich.edu MipsISA::PCState target = branchPC; 1317720Sgblack@eecs.umich.edu target.advance(); 1327720Sgblack@eecs.umich.edu target.npc(branchPC.pc() + sizeof(MachInst) + disp); 1337720Sgblack@eecs.umich.edu target.nnpc(target.npc() + sizeof(MachInst)); 1347720Sgblack@eecs.umich.edu return target; 1352083SN/A } 1362083SN/A 1377720Sgblack@eecs.umich.edu MipsISA::PCState 1382687Sksewell@umich.edu Jump::branchTarget(ThreadContext *tc) const 1392083SN/A { 1407720Sgblack@eecs.umich.edu MipsISA::PCState target = tc->pcState(); 1417720Sgblack@eecs.umich.edu Addr pc = target.pc(); 1427720Sgblack@eecs.umich.edu target.advance(); 1437720Sgblack@eecs.umich.edu target.npc((pc & 0xF0000000) | disp); 1447720Sgblack@eecs.umich.edu target.nnpc(target.npc() + sizeof(MachInst)); 1457720Sgblack@eecs.umich.edu return target; 1462083SN/A } 1472083SN/A 1482083SN/A const std::string & 1492083SN/A PCDependentDisassembly::disassemble(Addr pc, 1502083SN/A const SymbolTable *symtab) const 1512083SN/A { 1522083SN/A if (!cachedDisassembly || 1532083SN/A pc != cachedPC || symtab != cachedSymtab) 1542022SN/A { 1552083SN/A if (cachedDisassembly) 1562083SN/A delete cachedDisassembly; 1572083SN/A 1582083SN/A cachedDisassembly = 1592083SN/A new std::string(generateDisassembly(pc, symtab)); 1602083SN/A cachedPC = pc; 1612083SN/A cachedSymtab = symtab; 1622022SN/A } 1632083SN/A 1642083SN/A return *cachedDisassembly; 1652083SN/A } 1662083SN/A 1672083SN/A std::string 1682083SN/A Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1692083SN/A { 1702083SN/A std::stringstream ss; 1712083SN/A 1722083SN/A ccprintf(ss, "%-10s ", mnemonic); 1732083SN/A 1742083SN/A // There's only one register arg (RA), but it could be 1752083SN/A // either a source (the condition for conditional 1762083SN/A // branches) or a destination (the link reg for 1772083SN/A // unconditional branches) 1782239SN/A if (_numSrcRegs == 1) { 1792083SN/A printReg(ss, _srcRegIdx[0]); 1802686Sksewell@umich.edu ss << ", "; 1812239SN/A } else if(_numSrcRegs == 2) { 1822239SN/A printReg(ss, _srcRegIdx[0]); 1832686Sksewell@umich.edu ss << ", "; 1842239SN/A printReg(ss, _srcRegIdx[1]); 1852686Sksewell@umich.edu ss << ", "; 1862103SN/A } 1872103SN/A 1882103SN/A Addr target = pc + 4 + disp; 1892103SN/A 1902103SN/A std::string str; 1912103SN/A if (symtab && symtab->findSymbol(target, str)) 1922103SN/A ss << str; 1932103SN/A else 1942103SN/A ccprintf(ss, "0x%x", target); 1952103SN/A 1962103SN/A return ss.str(); 1972103SN/A } 1982103SN/A 1992103SN/A std::string 2002083SN/A Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const 2012083SN/A { 2022083SN/A std::stringstream ss; 2032083SN/A 2042083SN/A ccprintf(ss, "%-10s ", mnemonic); 2052083SN/A 2065269Sksewell@umich.edu if ( strcmp(mnemonic,"jal") == 0 ) { 2072239SN/A Addr npc = pc + 4; 2082239SN/A ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp); 2092239SN/A } else if (_numSrcRegs == 0) { 2102239SN/A std::string str; 2112239SN/A if (symtab && symtab->findSymbol(disp, str)) 2122239SN/A ss << str; 2132239SN/A else 2142239SN/A ccprintf(ss, "0x%x", disp); 2152239SN/A } else if (_numSrcRegs == 1) { 2162239SN/A printReg(ss, _srcRegIdx[0]); 2172239SN/A } else if(_numSrcRegs == 2) { 2182239SN/A printReg(ss, _srcRegIdx[0]); 2192686Sksewell@umich.edu ss << ", "; 2202239SN/A printReg(ss, _srcRegIdx[1]); 2212083SN/A } 2222083SN/A 2232083SN/A return ss.str(); 2242083SN/A } 2252022SN/A}}; 2262022SN/A 2274661Sksewell@umich.edudef format Branch(code, *opt_flags) {{ 2287720Sgblack@eecs.umich.edu not_taken_code = '' 2292686Sksewell@umich.edu 2302686Sksewell@umich.edu #Build Instruction Flags 2312686Sksewell@umich.edu #Use Link & Likely Flags to Add Link/Condition Code 2322686Sksewell@umich.edu inst_flags = ('IsDirectControl', ) 2332686Sksewell@umich.edu for x in opt_flags: 2342686Sksewell@umich.edu if x == 'Link': 2357720Sgblack@eecs.umich.edu code += 'R31 = pc.nnpc();\n' 2362686Sksewell@umich.edu elif x == 'Likely': 2377720Sgblack@eecs.umich.edu not_taken_code = 'pc.advance();' 2384661Sksewell@umich.edu inst_flags += ('IsCondDelaySlot', ) 2392686Sksewell@umich.edu else: 2402686Sksewell@umich.edu inst_flags += (x, ) 2412686Sksewell@umich.edu 2422935Sksewell@umich.edu #Take into account uncond. branch instruction 2434661Sksewell@umich.edu if 'cond = 1' in code: 2444661Sksewell@umich.edu inst_flags += ('IsUncondControl', ) 2452935Sksewell@umich.edu else: 2462686Sksewell@umich.edu inst_flags += ('IsCondControl', ) 2472101SN/A 2482123SN/A #Condition code 2497720Sgblack@eecs.umich.edu code = ''' 2507720Sgblack@eecs.umich.edu bool cond; 2517720Sgblack@eecs.umich.edu MipsISA::PCState pc = PCS; 2527720Sgblack@eecs.umich.edu %(code)s 2537720Sgblack@eecs.umich.edu if (cond) { 2547720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + disp); 2557720Sgblack@eecs.umich.edu } else { 2567720Sgblack@eecs.umich.edu %(not_taken_code)s 2577720Sgblack@eecs.umich.edu } 2587720Sgblack@eecs.umich.edu PCS = pc; 2597720Sgblack@eecs.umich.edu ''' % { "code" : code, "not_taken_code" : not_taken_code } 2602101SN/A 2613951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'Branch', code, inst_flags) 2622047SN/A header_output = BasicDeclare.subst(iop) 2632047SN/A decoder_output = BasicConstructor.subst(iop) 2642047SN/A decode_block = BasicDecode.subst(iop) 2652047SN/A exec_output = BasicExecute.subst(iop) 2662022SN/A}}; 2672047SN/A 2684661Sksewell@umich.edudef format DspBranch(code, *opt_flags) {{ 2697720Sgblack@eecs.umich.edu not_taken_code = '' 2704661Sksewell@umich.edu 2714661Sksewell@umich.edu #Build Instruction Flags 2724661Sksewell@umich.edu #Use Link & Likely Flags to Add Link/Condition Code 2734661Sksewell@umich.edu inst_flags = ('IsDirectControl', ) 2744661Sksewell@umich.edu for x in opt_flags: 2754661Sksewell@umich.edu if x == 'Link': 2767720Sgblack@eecs.umich.edu code += 'R32 = pc.nnpc();' 2774661Sksewell@umich.edu elif x == 'Likely': 2787720Sgblack@eecs.umich.edu not_taken_code = 'pc.advance();' 2794661Sksewell@umich.edu inst_flags += ('IsCondDelaySlot', ) 2804661Sksewell@umich.edu else: 2814661Sksewell@umich.edu inst_flags += (x, ) 2824661Sksewell@umich.edu 2834661Sksewell@umich.edu #Take into account uncond. branch instruction 2844661Sksewell@umich.edu if 'cond = 1' in code: 2854661Sksewell@umich.edu inst_flags += ('IsUncondControl', ) 2864661Sksewell@umich.edu else: 2874661Sksewell@umich.edu inst_flags += ('IsCondControl', ) 2884661Sksewell@umich.edu 2894661Sksewell@umich.edu #Condition code 2907720Sgblack@eecs.umich.edu code = ''' 2917720Sgblack@eecs.umich.edu MipsISA::PCState pc = PCS; 2927720Sgblack@eecs.umich.edu bool cond; 2937720Sgblack@eecs.umich.edu uint32_t dspctl = DSPControl; 2947720Sgblack@eecs.umich.edu %(code)s 2957720Sgblack@eecs.umich.edu if (cond) { 2967720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + disp); 2977720Sgblack@eecs.umich.edu } else { 2987720Sgblack@eecs.umich.edu %(not_taken_code)s 2997720Sgblack@eecs.umich.edu } 3007720Sgblack@eecs.umich.edu PCS = pc; 3017720Sgblack@eecs.umich.edu ''' % { "code" : code, "not_taken_code" : not_taken_code } 3024661Sksewell@umich.edu 3034661Sksewell@umich.edu iop = InstObjParams(name, Name, 'Branch', code, inst_flags) 3044661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 3054661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 3064661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 3074661Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3084661Sksewell@umich.edu}}; 3094661Sksewell@umich.edu 3102686Sksewell@umich.edudef format Jump(code, *opt_flags) {{ 3112686Sksewell@umich.edu #Build Instruction Flags 3122686Sksewell@umich.edu #Use Link Flag to Add Link Code 3132686Sksewell@umich.edu inst_flags = ('IsIndirectControl', 'IsUncondControl') 3142686Sksewell@umich.edu for x in opt_flags: 3152686Sksewell@umich.edu if x == 'Link': 3167720Sgblack@eecs.umich.edu code = ''' 3177720Sgblack@eecs.umich.edu R31 = pc.nnpc(); 3187720Sgblack@eecs.umich.edu ''' + code 3192686Sksewell@umich.edu elif x == 'ClearHazards': 3202686Sksewell@umich.edu code += '/* Code Needed to Clear Execute & Inst Hazards */\n' 3212686Sksewell@umich.edu else: 3222686Sksewell@umich.edu inst_flags += (x, ) 3232104SN/A 3247720Sgblack@eecs.umich.edu code = ''' 3257720Sgblack@eecs.umich.edu MipsISA::PCState pc = PCS; 3267720Sgblack@eecs.umich.edu ''' + code 3277720Sgblack@eecs.umich.edu 3283951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'Jump', code, inst_flags) 3292089SN/A header_output = BasicDeclare.subst(iop) 3302089SN/A decoder_output = BasicConstructor.subst(iop) 3312089SN/A decode_block = BasicDecode.subst(iop) 3322089SN/A exec_output = BasicExecute.subst(iop) 3332089SN/A}}; 3342083SN/A 3352239SN/A 3362123SN/A 3372123SN/A 338