branch.isa revision 5269
12100SN/A// -*- mode:c++ -*- 22083SN/A 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Korey Sewell 302706Sksewell@umich.edu 312089SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332089SN/A// Control transfer instructions 342022SN/A// 352022SN/A 362022SN/Aoutput header {{ 372083SN/A 382239SN/A#include <iostream> 394661Sksewell@umich.edu using namespace std; 402239SN/A 412083SN/A /** 422083SN/A * Base class for instructions whose disassembly is not purely a 432083SN/A * function of the machine instruction (i.e., it depends on the 442083SN/A * PC). This class overrides the disassemble() method to check 452083SN/A * the PC and symbol table values before re-using a cached 462083SN/A * disassembly string. This is necessary for branches and jumps, 472083SN/A * where the disassembly string includes the target address (which 482083SN/A * may depend on the PC and/or symbol table). 492083SN/A */ 502089SN/A class PCDependentDisassembly : public MipsStaticInst 512083SN/A { 522083SN/A protected: 532083SN/A /// Cached program counter from last disassembly 542083SN/A mutable Addr cachedPC; 552089SN/A 562083SN/A /// Cached symbol table pointer from last disassembly 572083SN/A mutable const SymbolTable *cachedSymtab; 582083SN/A 592083SN/A /// Constructor 602083SN/A PCDependentDisassembly(const char *mnem, MachInst _machInst, 612083SN/A OpClass __opClass) 622089SN/A : MipsStaticInst(mnem, _machInst, __opClass), 632083SN/A cachedPC(0), cachedSymtab(0) 642022SN/A { 652083SN/A } 662022SN/A 672083SN/A const std::string & 682083SN/A disassemble(Addr pc, const SymbolTable *symtab) const; 692083SN/A }; 702022SN/A 712083SN/A /** 722083SN/A * Base class for branches (PC-relative control transfers), 732083SN/A * conditional or unconditional. 742083SN/A */ 752083SN/A class Branch : public PCDependentDisassembly 762083SN/A { 772083SN/A protected: 782089SN/A /// target address (signed) Displacement . 792104SN/A int32_t disp; 802083SN/A 812083SN/A /// Constructor. 822083SN/A Branch(const char *mnem, MachInst _machInst, OpClass __opClass) 832083SN/A : PCDependentDisassembly(mnem, _machInst, __opClass), 842104SN/A disp(OFFSET << 2) 852089SN/A { 862239SN/A //If Bit 17 is 1 then Sign Extend 872239SN/A if ( (disp & 0x00020000) > 0 ) { 882239SN/A disp |= 0xFFFE0000; 892239SN/A } 902089SN/A } 912089SN/A 922089SN/A Addr branchTarget(Addr branchPC) const; 932089SN/A 942089SN/A std::string 952089SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 962089SN/A }; 972089SN/A 982089SN/A /** 992083SN/A * Base class for jumps (register-indirect control transfers). In 1002089SN/A * the Mips ISA, these are always unconditional. 1012083SN/A */ 1022083SN/A class Jump : public PCDependentDisassembly 1032083SN/A { 1042083SN/A protected: 1052083SN/A 1062083SN/A /// Displacement to target address (signed). 1072083SN/A int32_t disp; 1082083SN/A 1092239SN/A uint32_t target; 1102239SN/A 1112083SN/A public: 1122083SN/A /// Constructor 1132083SN/A Jump(const char *mnem, MachInst _machInst, OpClass __opClass) 1142083SN/A : PCDependentDisassembly(mnem, _machInst, __opClass), 1152239SN/A disp(JMPTARG << 2) 1162083SN/A { 1172083SN/A } 1182083SN/A 1192687Sksewell@umich.edu Addr branchTarget(ThreadContext *tc) const; 1202083SN/A 1212083SN/A std::string 1222083SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1232083SN/A }; 1242022SN/A}}; 1252022SN/A 1262022SN/Aoutput decoder {{ 1272083SN/A Addr 1282083SN/A Branch::branchTarget(Addr branchPC) const 1292083SN/A { 1302083SN/A return branchPC + 4 + disp; 1312083SN/A } 1322083SN/A 1332083SN/A Addr 1342687Sksewell@umich.edu Jump::branchTarget(ThreadContext *tc) const 1352083SN/A { 1365222Sksewell@umich.edu Addr NPC = tc->readNextPC(); 1375222Sksewell@umich.edu return (NPC & 0xF0000000) | (disp); 1382083SN/A } 1392083SN/A 1402083SN/A const std::string & 1412083SN/A PCDependentDisassembly::disassemble(Addr pc, 1422083SN/A const SymbolTable *symtab) const 1432083SN/A { 1442083SN/A if (!cachedDisassembly || 1452083SN/A pc != cachedPC || symtab != cachedSymtab) 1462022SN/A { 1472083SN/A if (cachedDisassembly) 1482083SN/A delete cachedDisassembly; 1492083SN/A 1502083SN/A cachedDisassembly = 1512083SN/A new std::string(generateDisassembly(pc, symtab)); 1522083SN/A cachedPC = pc; 1532083SN/A cachedSymtab = symtab; 1542022SN/A } 1552083SN/A 1562083SN/A return *cachedDisassembly; 1572083SN/A } 1582083SN/A 1592083SN/A std::string 1602083SN/A Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1612083SN/A { 1622083SN/A std::stringstream ss; 1632083SN/A 1642083SN/A ccprintf(ss, "%-10s ", mnemonic); 1652083SN/A 1662083SN/A // There's only one register arg (RA), but it could be 1672083SN/A // either a source (the condition for conditional 1682083SN/A // branches) or a destination (the link reg for 1692083SN/A // unconditional branches) 1702239SN/A if (_numSrcRegs == 1) { 1712083SN/A printReg(ss, _srcRegIdx[0]); 1722686Sksewell@umich.edu ss << ", "; 1732239SN/A } else if(_numSrcRegs == 2) { 1742239SN/A printReg(ss, _srcRegIdx[0]); 1752686Sksewell@umich.edu ss << ", "; 1762239SN/A printReg(ss, _srcRegIdx[1]); 1772686Sksewell@umich.edu ss << ", "; 1782103SN/A } 1792103SN/A 1802103SN/A Addr target = pc + 4 + disp; 1812103SN/A 1822103SN/A std::string str; 1832103SN/A if (symtab && symtab->findSymbol(target, str)) 1842103SN/A ss << str; 1852103SN/A else 1862103SN/A ccprintf(ss, "0x%x", target); 1872103SN/A 1882103SN/A return ss.str(); 1892103SN/A } 1902103SN/A 1912103SN/A std::string 1922083SN/A Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1932083SN/A { 1942083SN/A std::stringstream ss; 1952083SN/A 1962083SN/A ccprintf(ss, "%-10s ", mnemonic); 1972083SN/A 1985269Sksewell@umich.edu if ( strcmp(mnemonic,"jal") == 0 ) { 1992239SN/A Addr npc = pc + 4; 2002239SN/A ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp); 2012239SN/A } else if (_numSrcRegs == 0) { 2022239SN/A std::string str; 2032239SN/A if (symtab && symtab->findSymbol(disp, str)) 2042239SN/A ss << str; 2052239SN/A else 2062239SN/A ccprintf(ss, "0x%x", disp); 2072239SN/A } else if (_numSrcRegs == 1) { 2082239SN/A printReg(ss, _srcRegIdx[0]); 2092239SN/A } else if(_numSrcRegs == 2) { 2102239SN/A printReg(ss, _srcRegIdx[0]); 2112686Sksewell@umich.edu ss << ", "; 2122239SN/A printReg(ss, _srcRegIdx[1]); 2132083SN/A } 2142083SN/A 2152083SN/A return ss.str(); 2162083SN/A } 2172022SN/A}}; 2182022SN/A 2194661Sksewell@umich.edudef format Branch(code, *opt_flags) {{ 2202686Sksewell@umich.edu not_taken_code = ' NNPC = NNPC;\n' 2212686Sksewell@umich.edu not_taken_code += '} \n' 2222686Sksewell@umich.edu 2232686Sksewell@umich.edu #Build Instruction Flags 2242686Sksewell@umich.edu #Use Link & Likely Flags to Add Link/Condition Code 2252686Sksewell@umich.edu inst_flags = ('IsDirectControl', ) 2262686Sksewell@umich.edu for x in opt_flags: 2272686Sksewell@umich.edu if x == 'Link': 2282686Sksewell@umich.edu code += 'R31 = NNPC;\n' 2292686Sksewell@umich.edu elif x == 'Likely': 2302686Sksewell@umich.edu not_taken_code = ' NPC = NNPC;\n' 2312686Sksewell@umich.edu not_taken_code += ' NNPC = NNPC + 4;\n' 2322686Sksewell@umich.edu not_taken_code += '} \n' 2334661Sksewell@umich.edu inst_flags += ('IsCondDelaySlot', ) 2342686Sksewell@umich.edu else: 2352686Sksewell@umich.edu inst_flags += (x, ) 2362686Sksewell@umich.edu 2372935Sksewell@umich.edu #Take into account uncond. branch instruction 2384661Sksewell@umich.edu if 'cond = 1' in code: 2394661Sksewell@umich.edu inst_flags += ('IsUncondControl', ) 2402935Sksewell@umich.edu else: 2412686Sksewell@umich.edu inst_flags += ('IsCondControl', ) 2422101SN/A 2432123SN/A #Condition code 2442123SN/A code = 'bool cond;\n' + code 2452123SN/A code += 'if (cond) {\n' 2462123SN/A code += ' NNPC = NPC + disp;\n' 2472239SN/A code += '} else {\n' 2482686Sksewell@umich.edu code += not_taken_code 2492101SN/A 2503951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'Branch', code, inst_flags) 2512047SN/A header_output = BasicDeclare.subst(iop) 2522047SN/A decoder_output = BasicConstructor.subst(iop) 2532047SN/A decode_block = BasicDecode.subst(iop) 2542047SN/A exec_output = BasicExecute.subst(iop) 2552022SN/A}}; 2562047SN/A 2574661Sksewell@umich.edudef format DspBranch(code, *opt_flags) {{ 2584661Sksewell@umich.edu not_taken_code = ' NNPC = NNPC;\n' 2594661Sksewell@umich.edu not_taken_code += '} \n' 2604661Sksewell@umich.edu 2614661Sksewell@umich.edu #Build Instruction Flags 2624661Sksewell@umich.edu #Use Link & Likely Flags to Add Link/Condition Code 2634661Sksewell@umich.edu inst_flags = ('IsDirectControl', ) 2644661Sksewell@umich.edu for x in opt_flags: 2654661Sksewell@umich.edu if x == 'Link': 2664661Sksewell@umich.edu code += 'R31 = NNPC;\n' 2674661Sksewell@umich.edu elif x == 'Likely': 2684661Sksewell@umich.edu not_taken_code = ' NPC = NNPC;\n' 2694661Sksewell@umich.edu not_taken_code += ' NNPC = NNPC + 4;\n' 2704661Sksewell@umich.edu not_taken_code += '} \n' 2714661Sksewell@umich.edu inst_flags += ('IsCondDelaySlot', ) 2724661Sksewell@umich.edu else: 2734661Sksewell@umich.edu inst_flags += (x, ) 2744661Sksewell@umich.edu 2754661Sksewell@umich.edu #Take into account uncond. branch instruction 2764661Sksewell@umich.edu if 'cond = 1' in code: 2774661Sksewell@umich.edu inst_flags += ('IsUncondControl', ) 2784661Sksewell@umich.edu else: 2794661Sksewell@umich.edu inst_flags += ('IsCondControl', ) 2804661Sksewell@umich.edu 2814661Sksewell@umich.edu #Declaration code 2824661Sksewell@umich.edu decl_code = 'bool cond;\n' 2834661Sksewell@umich.edu decl_code += 'uint32_t dspctl;\n' 2844661Sksewell@umich.edu 2854661Sksewell@umich.edu #Fetch code 2864661Sksewell@umich.edu fetch_code = 'dspctl = DSPControl;\n' 2874661Sksewell@umich.edu 2884661Sksewell@umich.edu #Condition code 2894661Sksewell@umich.edu code = decl_code + fetch_code + code 2904661Sksewell@umich.edu code += 'if (cond) {\n' 2914661Sksewell@umich.edu code += ' NNPC = NPC + disp;\n' 2924661Sksewell@umich.edu code += '} else {\n' 2934661Sksewell@umich.edu code += not_taken_code 2944661Sksewell@umich.edu 2954661Sksewell@umich.edu iop = InstObjParams(name, Name, 'Branch', code, inst_flags) 2964661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2974661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2984661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2994661Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 3004661Sksewell@umich.edu}}; 3014661Sksewell@umich.edu 3022686Sksewell@umich.edudef format Jump(code, *opt_flags) {{ 3032686Sksewell@umich.edu #Build Instruction Flags 3042686Sksewell@umich.edu #Use Link Flag to Add Link Code 3052686Sksewell@umich.edu inst_flags = ('IsIndirectControl', 'IsUncondControl') 3062686Sksewell@umich.edu for x in opt_flags: 3072686Sksewell@umich.edu if x == 'Link': 3082686Sksewell@umich.edu code = 'R31 = NNPC;\n' + code 3092686Sksewell@umich.edu elif x == 'ClearHazards': 3102686Sksewell@umich.edu code += '/* Code Needed to Clear Execute & Inst Hazards */\n' 3112686Sksewell@umich.edu else: 3122686Sksewell@umich.edu inst_flags += (x, ) 3132104SN/A 3143951Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'Jump', code, inst_flags) 3152089SN/A header_output = BasicDeclare.subst(iop) 3162089SN/A decoder_output = BasicConstructor.subst(iop) 3172089SN/A decode_block = BasicDecode.subst(iop) 3182089SN/A exec_output = BasicExecute.subst(iop) 3192089SN/A}}; 3202083SN/A 3212239SN/A 3222123SN/A 3232123SN/A 324