branch.isa revision 2706
111238Sandreas.sandberg@arm.com// -*- mode:c++ -*- 211238Sandreas.sandberg@arm.com 311238Sandreas.sandberg@arm.com// Copyright (c) 2003-2006 The Regents of The University of Michigan 411889Spierre-yves.peneau@lirmm.fr// All rights reserved. 511889Spierre-yves.peneau@lirmm.fr// 611238Sandreas.sandberg@arm.com// Redistribution and use in source and binary forms, with or without 711238Sandreas.sandberg@arm.com// modification, are permitted provided that the following conditions are 811238Sandreas.sandberg@arm.com// met: redistributions of source code must retain the above copyright 911238Sandreas.sandberg@arm.com// notice, this list of conditions and the following disclaimer; 1011238Sandreas.sandberg@arm.com// redistributions in binary form must reproduce the above copyright 1111238Sandreas.sandberg@arm.com// notice, this list of conditions and the following disclaimer in the 1211238Sandreas.sandberg@arm.com// documentation and/or other materials provided with the distribution; 1311238Sandreas.sandberg@arm.com// neither the name of the copyright holders nor the names of its 1411238Sandreas.sandberg@arm.com// contributors may be used to endorse or promote products derived from 1511238Sandreas.sandberg@arm.com// this software without specific prior written permission. 1611238Sandreas.sandberg@arm.com// 1711238Sandreas.sandberg@arm.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1811238Sandreas.sandberg@arm.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1911238Sandreas.sandberg@arm.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2011238Sandreas.sandberg@arm.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2111238Sandreas.sandberg@arm.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2211238Sandreas.sandberg@arm.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2311238Sandreas.sandberg@arm.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2411238Sandreas.sandberg@arm.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2511238Sandreas.sandberg@arm.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2611238Sandreas.sandberg@arm.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2711238Sandreas.sandberg@arm.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2811238Sandreas.sandberg@arm.com// 2911238Sandreas.sandberg@arm.com// Authors: Korey Sewell 3011238Sandreas.sandberg@arm.com 3111238Sandreas.sandberg@arm.com//////////////////////////////////////////////////////////////////// 3211238Sandreas.sandberg@arm.com// 3311238Sandreas.sandberg@arm.com// Control transfer instructions 3411238Sandreas.sandberg@arm.com// 3511238Sandreas.sandberg@arm.com 3611238Sandreas.sandberg@arm.comoutput header {{ 3711238Sandreas.sandberg@arm.com 3811238Sandreas.sandberg@arm.com#include <iostream> 3911889Spierre-yves.peneau@lirmm.fr using namespace std; 4011238Sandreas.sandberg@arm.com 4112564Sgabeblack@google.com /** 4212564Sgabeblack@google.com * Base class for instructions whose disassembly is not purely a 4311238Sandreas.sandberg@arm.com * function of the machine instruction (i.e., it depends on the 4411238Sandreas.sandberg@arm.com * PC). This class overrides the disassemble() method to check 4511238Sandreas.sandberg@arm.com * the PC and symbol table values before re-using a cached 4611889Spierre-yves.peneau@lirmm.fr * disassembly string. This is necessary for branches and jumps, 4711238Sandreas.sandberg@arm.com * where the disassembly string includes the target address (which 4811238Sandreas.sandberg@arm.com * may depend on the PC and/or symbol table). 4911238Sandreas.sandberg@arm.com */ 5011238Sandreas.sandberg@arm.com class PCDependentDisassembly : public MipsStaticInst 5111238Sandreas.sandberg@arm.com { 5211238Sandreas.sandberg@arm.com protected: 5311238Sandreas.sandberg@arm.com /// Cached program counter from last disassembly 5411238Sandreas.sandberg@arm.com mutable Addr cachedPC; 5511238Sandreas.sandberg@arm.com 5611297Sandreas.sandberg@arm.com /// Cached symbol table pointer from last disassembly 5711238Sandreas.sandberg@arm.com mutable const SymbolTable *cachedSymtab; 5811238Sandreas.sandberg@arm.com 5911238Sandreas.sandberg@arm.com /// Constructor 6011238Sandreas.sandberg@arm.com PCDependentDisassembly(const char *mnem, MachInst _machInst, 6111238Sandreas.sandberg@arm.com OpClass __opClass) 6211238Sandreas.sandberg@arm.com : MipsStaticInst(mnem, _machInst, __opClass), 6311238Sandreas.sandberg@arm.com cachedPC(0), cachedSymtab(0) 6411238Sandreas.sandberg@arm.com { 6511238Sandreas.sandberg@arm.com } 6611238Sandreas.sandberg@arm.com 6711238Sandreas.sandberg@arm.com const std::string & 6811238Sandreas.sandberg@arm.com disassemble(Addr pc, const SymbolTable *symtab) const; 6911238Sandreas.sandberg@arm.com }; 7011238Sandreas.sandberg@arm.com 7111688Sandreas.hansson@arm.com /** 7211238Sandreas.sandberg@arm.com * Base class for branches (PC-relative control transfers), 7311238Sandreas.sandberg@arm.com * conditional or unconditional. 7411238Sandreas.sandberg@arm.com */ 7511238Sandreas.sandberg@arm.com class Branch : public PCDependentDisassembly 7611238Sandreas.sandberg@arm.com { 7711238Sandreas.sandberg@arm.com protected: 7811238Sandreas.sandberg@arm.com /// target address (signed) Displacement . 7911238Sandreas.sandberg@arm.com int32_t disp; 8011238Sandreas.sandberg@arm.com 8111238Sandreas.sandberg@arm.com /// Constructor. 8211889Spierre-yves.peneau@lirmm.fr Branch(const char *mnem, MachInst _machInst, OpClass __opClass) 8311238Sandreas.sandberg@arm.com : PCDependentDisassembly(mnem, _machInst, __opClass), 8411238Sandreas.sandberg@arm.com disp(OFFSET << 2) 8511238Sandreas.sandberg@arm.com { 8611238Sandreas.sandberg@arm.com //If Bit 17 is 1 then Sign Extend 8712564Sgabeblack@google.com if ( (disp & 0x00020000) > 0 ) { 8811238Sandreas.sandberg@arm.com disp |= 0xFFFE0000; 8911238Sandreas.sandberg@arm.com } 9012564Sgabeblack@google.com } 9111238Sandreas.sandberg@arm.com 9211238Sandreas.sandberg@arm.com Addr branchTarget(Addr branchPC) const; 9311238Sandreas.sandberg@arm.com 9411238Sandreas.sandberg@arm.com std::string 9511238Sandreas.sandberg@arm.com generateDisassembly(Addr pc, const SymbolTable *symtab) const; 9611238Sandreas.sandberg@arm.com }; 9712564Sgabeblack@google.com 9811238Sandreas.sandberg@arm.com /** 9911238Sandreas.sandberg@arm.com * Base class for jumps (register-indirect control transfers). In 10012564Sgabeblack@google.com * the Mips ISA, these are always unconditional. 10111238Sandreas.sandberg@arm.com */ 10212564Sgabeblack@google.com class Jump : public PCDependentDisassembly 10311238Sandreas.sandberg@arm.com { 10411238Sandreas.sandberg@arm.com protected: 10511238Sandreas.sandberg@arm.com 10613731Sandreas.sandberg@arm.com /// Displacement to target address (signed). 10711238Sandreas.sandberg@arm.com int32_t disp; 10811238Sandreas.sandberg@arm.com 10911238Sandreas.sandberg@arm.com uint32_t target; 11011238Sandreas.sandberg@arm.com 11111238Sandreas.sandberg@arm.com public: 11211238Sandreas.sandberg@arm.com /// Constructor 11311238Sandreas.sandberg@arm.com Jump(const char *mnem, MachInst _machInst, OpClass __opClass) 11411238Sandreas.sandberg@arm.com : PCDependentDisassembly(mnem, _machInst, __opClass), 115 disp(JMPTARG << 2) 116 { 117 } 118 119 Addr branchTarget(ThreadContext *tc) const; 120 121 std::string 122 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 123 }; 124}}; 125 126output decoder {{ 127 Addr 128 Branch::branchTarget(Addr branchPC) const 129 { 130 return branchPC + 4 + disp; 131 } 132 133 Addr 134 Jump::branchTarget(ThreadContext *tc) const 135 { 136 Addr NPC = tc->readPC() + 4; 137 uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); 138 return (Rb & ~3) | (NPC & 1); 139 } 140 141 const std::string & 142 PCDependentDisassembly::disassemble(Addr pc, 143 const SymbolTable *symtab) const 144 { 145 if (!cachedDisassembly || 146 pc != cachedPC || symtab != cachedSymtab) 147 { 148 if (cachedDisassembly) 149 delete cachedDisassembly; 150 151 cachedDisassembly = 152 new std::string(generateDisassembly(pc, symtab)); 153 cachedPC = pc; 154 cachedSymtab = symtab; 155 } 156 157 return *cachedDisassembly; 158 } 159 160 std::string 161 Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const 162 { 163 std::stringstream ss; 164 165 ccprintf(ss, "%-10s ", mnemonic); 166 167 // There's only one register arg (RA), but it could be 168 // either a source (the condition for conditional 169 // branches) or a destination (the link reg for 170 // unconditional branches) 171 if (_numSrcRegs == 1) { 172 printReg(ss, _srcRegIdx[0]); 173 ss << ", "; 174 } else if(_numSrcRegs == 2) { 175 printReg(ss, _srcRegIdx[0]); 176 ss << ", "; 177 printReg(ss, _srcRegIdx[1]); 178 ss << ", "; 179 } 180 181 Addr target = pc + 4 + disp; 182 183 std::string str; 184 if (symtab && symtab->findSymbol(target, str)) 185 ss << str; 186 else 187 ccprintf(ss, "0x%x", target); 188 189 return ss.str(); 190 } 191 192 std::string 193 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const 194 { 195 std::stringstream ss; 196 197 ccprintf(ss, "%-10s ", mnemonic); 198 199 if ( mnemonic == "jal" ) { 200 Addr npc = pc + 4; 201 ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp); 202 } else if (_numSrcRegs == 0) { 203 std::string str; 204 if (symtab && symtab->findSymbol(disp, str)) 205 ss << str; 206 else 207 ccprintf(ss, "0x%x", disp); 208 } else if (_numSrcRegs == 1) { 209 printReg(ss, _srcRegIdx[0]); 210 } else if(_numSrcRegs == 2) { 211 printReg(ss, _srcRegIdx[0]); 212 ss << ", "; 213 printReg(ss, _srcRegIdx[1]); 214 } 215 216 return ss.str(); 217 } 218}}; 219 220def format Branch(code,*opt_flags) {{ 221 not_taken_code = ' NNPC = NNPC;\n' 222 not_taken_code += '} \n' 223 224 #Build Instruction Flags 225 #Use Link & Likely Flags to Add Link/Condition Code 226 inst_flags = ('IsDirectControl', ) 227 for x in opt_flags: 228 if x == 'Link': 229 code += 'R31 = NNPC;\n' 230 elif x == 'Likely': 231 not_taken_code = ' NPC = NNPC;\n' 232 not_taken_code += ' NNPC = NNPC + 4;\n' 233 not_taken_code += '} \n' 234 inst_flags = ('IsCondDelaySlot', ) 235 else: 236 inst_flags += (x, ) 237 238 if 'cond == 1' in code: 239 inst_flags += ('IsCondControl', ) 240 else: 241 inst_flags += ('IsUncondControl', ) 242 243 #Condition code 244 code = 'bool cond;\n' + code 245 code += 'if (cond) {\n' 246 code += ' NNPC = NPC + disp;\n' 247 code += '} else {\n' 248 code += not_taken_code 249 250 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), inst_flags) 251 header_output = BasicDeclare.subst(iop) 252 decoder_output = BasicConstructor.subst(iop) 253 decode_block = BasicDecode.subst(iop) 254 exec_output = BasicExecute.subst(iop) 255}}; 256 257def format Jump(code, *opt_flags) {{ 258 #Build Instruction Flags 259 #Use Link Flag to Add Link Code 260 inst_flags = ('IsIndirectControl', 'IsUncondControl') 261 for x in opt_flags: 262 if x == 'Link': 263 code = 'R31 = NNPC;\n' + code 264 elif x == 'ClearHazards': 265 code += '/* Code Needed to Clear Execute & Inst Hazards */\n' 266 else: 267 inst_flags += (x, ) 268 269 iop = InstObjParams(name, Name, 'Jump', CodeBlock(code), inst_flags) 270 header_output = BasicDeclare.subst(iop) 271 decoder_output = BasicConstructor.subst(iop) 272 decode_block = BasicDecode.subst(iop) 273 exec_output = BasicExecute.subst(iop) 274}}; 275 276 277 278 279