decoder.isa revision 7792:8ac74e34c6f4
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30// Brett Miller 31// Jaidev Patwardhan 32 33//////////////////////////////////////////////////////////////////// 34// 35// The actual MIPS32 ISA decoder 36// ----------------------------- 37// The following instructions are specified in the MIPS32 ISA 38// Specification. Decoding closely follows the style specified 39// in the MIPS32 ISA specification document starting with Table 40// A-2 (document available @ http://www.mips.com) 41// 42decode OPCODE_HI default Unknown::unknown() { 43 //Table A-2 44 0x0: decode OPCODE_LO { 45 0x0: decode FUNCTION_HI { 46 0x0: decode FUNCTION_LO { 47 0x1: decode MOVCI { 48 format BasicOp { 49 0: movf({{ 50 Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; 51 }}); 52 1: movt({{ 53 Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; 54 }}); 55 } 56 } 57 58 format BasicOp { 59 //Table A-3 Note: "Specific encodings of the rd, rs, and 60 //rt fields are used to distinguish SLL, SSNOP, and EHB 61 //functions 62 0x0: decode RS { 63 0x0: decode RT_RD { 64 0x0: decode SA default Nop::nop() { 65 0x1: ssnop({{;}}); 66 0x3: ehb({{;}}); 67 } 68 default: sll({{ Rd = Rt.uw << SA; }}); 69 } 70 } 71 72 0x2: decode RS_SRL { 73 0x0:decode SRL { 74 0: srl({{ Rd = Rt.uw >> SA; }}); 75 76 //Hardcoded assuming 32-bit ISA, 77 //probably need parameter here 78 1: rotr({{ 79 Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA); 80 }}); 81 } 82 } 83 84 0x3: decode RS { 85 0x0: sra({{ 86 uint32_t temp = Rt >> SA; 87 if ( (Rt & 0x80000000) > 0 ) { 88 uint32_t mask = 0x80000000; 89 for(int i=0; i < SA; i++) { 90 temp |= mask; 91 mask = mask >> 1; 92 } 93 } 94 Rd = temp; 95 }}); 96 } 97 98 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 99 100 0x6: decode SRLV { 101 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 102 103 //Hardcoded assuming 32-bit ISA, 104 //probably need parameter here 105 1: rotrv({{ 106 Rd = (Rt.uw << (32 - Rs<4:0>)) | 107 (Rt.uw >> Rs<4:0>); 108 }}); 109 } 110 111 0x7: srav({{ 112 int shift_amt = Rs<4:0>; 113 114 uint32_t temp = Rt >> shift_amt; 115 116 if ((Rt & 0x80000000) > 0) { 117 uint32_t mask = 0x80000000; 118 for (int i = 0; i < shift_amt; i++) { 119 temp |= mask; 120 mask = mask >> 1; 121 } 122 } 123 Rd = temp; 124 }}); 125 } 126 } 127 128 0x1: decode FUNCTION_LO { 129 //Table A-3 Note: "Specific encodings of the hint field are 130 //used to distinguish JR from JR.HB and JALR from JALR.HB" 131 format Jump { 132 0x0: decode HINT { 133 0x1: jr_hb({{ 134 Config1Reg config1 = Config1; 135 if (config1.ca == 0) { 136 NNPC = Rs; 137 } else { 138 panic("MIPS16e not supported\n"); 139 } 140 }}, IsReturn, ClearHazards); 141 default: jr({{ 142 Config1Reg config1 = Config1; 143 if (config1.ca == 0) { 144 NNPC = Rs; 145 } else { 146 panic("MIPS16e not supported\n"); 147 } 148 }}, IsReturn); 149 } 150 151 0x1: decode HINT { 152 0x1: jalr_hb({{ 153 Rd = NNPC; 154 NNPC = Rs; 155 }}, IsCall, ClearHazards); 156 default: jalr({{ 157 Rd = NNPC; 158 NNPC = Rs; 159 }}, IsCall); 160 } 161 } 162 163 format BasicOp { 164 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 165 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 166#if FULL_SYSTEM 167 0x4: syscall({{ fault = new SystemCallFault(); }}); 168#else 169 0x4: syscall({{ xc->syscall(R2); }}, 170 IsSerializeAfter, IsNonSpeculative); 171#endif 172 0x7: sync({{ ; }}, IsMemBarrier); 173 0x5: break({{fault = new BreakpointFault();}}); 174 } 175 176 } 177 178 0x2: decode FUNCTION_LO { 179 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, 180 IntMultOp, IsIprAccess); 181 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); 182 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, 183 IntMultOp, IsIprAccess); 184 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 185 } 186 187 0x3: decode FUNCTION_LO { 188 format HiLoRdSelValOp { 189 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp); 190 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp); 191 } 192 193 format HiLoOp { 194 0x2: div({{ 195 if (Rt.sd != 0) { 196 HI0 = Rs.sd % Rt.sd; 197 LO0 = Rs.sd / Rt.sd; 198 } 199 }}, IntDivOp); 200 201 0x3: divu({{ 202 if (Rt.ud != 0) { 203 HI0 = Rs.ud % Rt.ud; 204 LO0 = Rs.ud / Rt.ud; 205 } 206 }}, IntDivOp); 207 } 208 } 209 210 0x4: decode HINT { 211 0x0: decode FUNCTION_LO { 212 format IntOp { 213 0x0: add({{ 214 /* More complicated since an ADD can cause 215 an arithmetic overflow exception */ 216 int64_t Src1 = Rs.sw; 217 int64_t Src2 = Rt.sw; 218 int64_t temp_result; 219#if FULL_SYSTEM 220 if (((Src1 >> 31) & 1) == 1) 221 Src1 |= 0x100000000LL; 222#endif 223 temp_result = Src1 + Src2; 224#if FULL_SYSTEM 225 if (bits(temp_result, 31) == 226 bits(temp_result, 32)) { 227#endif 228 Rd.sw = temp_result; 229#if FULL_SYSTEM 230 } else { 231 fault = new ArithmeticFault(); 232 } 233#endif 234 }}); 235 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 236 0x2: sub({{ 237 /* More complicated since an SUB can cause 238 an arithmetic overflow exception */ 239 int64_t Src1 = Rs.sw; 240 int64_t Src2 = Rt.sw; 241 int64_t temp_result = Src1 - Src2; 242#if FULL_SYSTEM 243 if (bits(temp_result, 31) == 244 bits(temp_result, 32)) { 245#endif 246 Rd.sw = temp_result; 247#if FULL_SYSTEM 248 } else { 249 fault = new ArithmeticFault(); 250 } 251#endif 252 }}); 253 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw; }}); 254 0x4: and({{ Rd = Rs & Rt; }}); 255 0x5: or({{ Rd = Rs | Rt; }}); 256 0x6: xor({{ Rd = Rs ^ Rt; }}); 257 0x7: nor({{ Rd = ~(Rs | Rt); }}); 258 } 259 } 260 } 261 262 0x5: decode HINT { 263 0x0: decode FUNCTION_LO { 264 format IntOp{ 265 0x2: slt({{ Rd.sw = (Rs.sw < Rt.sw) ? 1 : 0 }}); 266 0x3: sltu({{ Rd.uw = (Rs.uw < Rt.uw) ? 1 : 0 }}); 267 } 268 } 269 } 270 271 0x6: decode FUNCTION_LO { 272 format Trap { 273 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 274 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 275 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 276 0x3: tltu({{ cond = (Rs.uw < Rt.uw); }}); 277 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 278 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 279 } 280 } 281 } 282 283 0x1: decode REGIMM_HI { 284 0x0: decode REGIMM_LO { 285 format Branch { 286 0x0: bltz({{ cond = (Rs.sw < 0); }}); 287 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 288 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely); 289 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely); 290 } 291 } 292 293 0x1: decode REGIMM_LO { 294 format TrapImm { 295 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }}); 296 0x1: tgeiu({{ 297 cond = (Rs.uw >= (uint32_t)(int32_t)(int16_t)INTIMM); 298 }}); 299 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }}); 300 0x3: tltiu({{ 301 cond = (Rs.uw < (uint32_t)(int32_t)(int16_t)INTIMM); 302 }}); 303 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM); }}); 304 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM); }}); 305 } 306 } 307 308 0x2: decode REGIMM_LO { 309 format Branch { 310 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link); 311 0x1: decode RS { 312 0x0: bal ({{ cond = 1; }}, IsCall, Link); 313 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link); 314 } 315 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely); 316 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely); 317 } 318 } 319 320 0x3: decode REGIMM_LO { 321 // from Table 5-4 MIPS32 REGIMM Encoding of rt Field 322 // (DSP ASE MANUAL) 323 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 324 format WarnUnimpl { 325 0x7: synci(); 326 } 327 } 328 } 329 330 format Jump { 331 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}); 332 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, 333 IsCall, Link); 334 } 335 336 format Branch { 337 0x4: decode RS_RT { 338 0x0: b({{ cond = 1; }}); 339 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 340 } 341 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 342 0x6: blez({{ cond = (Rs.sw <= 0); }}); 343 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 344 } 345 } 346 347 0x1: decode OPCODE_LO { 348 format IntImmOp { 349 0x0: addi({{ 350 int64_t Src1 = Rs.sw; 351 int64_t Src2 = imm; 352 int64_t temp_result; 353#if FULL_SYSTEM 354 if (((Src1 >> 31) & 1) == 1) 355 Src1 |= 0x100000000LL; 356#endif 357 temp_result = Src1 + Src2; 358#if FULL_SYSTEM 359 if (bits(temp_result, 31) == bits(temp_result, 32)) { 360#endif 361 Rt.sw = temp_result; 362#if FULL_SYSTEM 363 } else { 364 fault = new ArithmeticFault(); 365 } 366#endif 367 }}); 368 0x1: addiu({{ Rt.sw = Rs.sw + imm; }}); 369 0x2: slti({{ Rt.sw = (Rs.sw < imm) ? 1 : 0 }}); 370 371 //Edited to include MIPS AVP Pass/Fail instructions and 372 //default to the sltiu instruction 373 0x3: decode RS_RT_INTIMM { 374 0xabc1: BasicOp::fail({{ 375 exitSimLoop("AVP/SRVP Test Failed"); 376 }}); 377 0xabc2: BasicOp::pass({{ 378 exitSimLoop("AVP/SRVP Test Passed"); 379 }}); 380 default: sltiu({{ 381 Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0; 382 }}); 383 } 384 385 0x4: andi({{ Rt.sw = Rs.sw & zextImm; }}); 386 0x5: ori({{ Rt.sw = Rs.sw | zextImm; }}); 387 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm; }}); 388 389 0x7: decode RS { 390 0x0: lui({{ Rt = imm << 16; }}); 391 } 392 } 393 } 394 395 0x2: decode OPCODE_LO { 396 //Table A-11 MIPS32 COP0 Encoding of rs Field 397 0x0: decode RS_MSB { 398 0x0: decode RS { 399 format CP0Control { 400 0x0: mfc0({{ 401 Config3Reg config3 = Config3; 402 PageGrainReg pageGrain = PageGrain; 403 Rt = CP0_RD_SEL; 404 /* Hack for PageMask */ 405 if (RD == 5) { 406 // PageMask 407 if (config3.sp == 0 || pageGrain.esp == 0) 408 Rt &= 0xFFFFE7FF; 409 } 410 }}); 411 0x4: mtc0({{ 412 CP0_RD_SEL = Rt; 413 CauseReg cause = Cause; 414 IntCtlReg intCtl = IntCtl; 415 if (RD == 11) { 416 // Compare 417 if (cause.ti == 1) { 418 cause.ti = 0; 419 int offset = 10; // corresponding to cause.ip0 420 offset += intCtl.ipti - 2; 421 replaceBits(cause, offset, offset, 0); 422 } 423 } 424 Cause = cause; 425 }}); 426 } 427 format CP0Unimpl { 428 0x1: dmfc0(); 429 0x5: dmtc0(); 430 default: unknown(); 431 } 432 format MT_MFTR { 433 // Decode MIPS MT MFTR instruction into sub-instructions 434 0x8: decode MT_U { 435 0x0: mftc0({{ 436 data = xc->readRegOtherThread((RT << 3 | SEL) + 437 Ctrl_Base_DepTag); 438 }}); 439 0x1: decode SEL { 440 0x0: mftgpr({{ 441 data = xc->readRegOtherThread(RT); 442 }}); 443 0x1: decode RT { 444 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }}); 445 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }}); 446 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }}); 447 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }}); 448 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }}); 449 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }}); 450 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }}); 451 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }}); 452 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }}); 453 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }}); 454 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }}); 455 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }}); 456 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }}); 457 default: CP0Unimpl::unknown(); 458 } 459 0x2: decode MT_H { 460 0x0: mftc1({{ data = xc->readRegOtherThread(RT + 461 FP_Base_DepTag); 462 }}); 463 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + 464 FP_Base_DepTag); 465 }}); 466 } 467 0x3: cftc1({{ 468 uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR + 469 FP_Base_DepTag); 470 switch (RT) { 471 case 0: 472 data = xc->readRegOtherThread(FLOATREG_FIR + 473 Ctrl_Base_DepTag); 474 break; 475 case 25: 476 data = (fcsr_val & 0xFE000000 >> 24) | 477 (fcsr_val & 0x00800000 >> 23); 478 break; 479 case 26: 480 data = fcsr_val & 0x0003F07C; 481 break; 482 case 28: 483 data = (fcsr_val & 0x00000F80) | 484 (fcsr_val & 0x01000000 >> 21) | 485 (fcsr_val & 0x00000003); 486 break; 487 case 31: 488 data = fcsr_val; 489 break; 490 default: 491 fatal("FP Control Value (%d) Not Valid"); 492 } 493 }}); 494 default: CP0Unimpl::unknown(); 495 } 496 } 497 } 498 499 format MT_MTTR { 500 // Decode MIPS MT MTTR instruction into sub-instructions 501 0xC: decode MT_U { 502 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, 503 Rt); 504 }}); 505 0x1: decode SEL { 506 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 507 0x1: decode RT { 508 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt); 509 }}); 510 0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0, 511 Rt); 512 }}); 513 0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0, 514 Rt); 515 }}); 516 0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1, 517 Rt); 518 }}); 519 0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1, 520 Rt); 521 }}); 522 0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1, 523 Rt); 524 }}); 525 0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2, 526 Rt); 527 }}); 528 0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2, 529 Rt); 530 }}); 531 0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2, 532 Rt); 533 }}); 534 0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3, 535 Rt); 536 }}); 537 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3, 538 Rt); 539 }}); 540 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt); 541 }}); 542 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }}); 543 default: CP0Unimpl::unknown(); 544 545 } 546 0x2: mttc1({{ 547 uint64_t data = xc->readRegOtherThread(RD + 548 FP_Base_DepTag); 549 data = insertBits(data, top_bit, 550 bottom_bit, Rt); 551 xc->setRegOtherThread(RD + FP_Base_DepTag, 552 data); 553 }}); 554 0x3: cttc1({{ 555 uint32_t data; 556 switch (RD) { 557 case 25: 558 data = (Rt.uw<7:1> << 25) | // move 31-25 559 (FCSR & 0x01000000) | // bit 24 560 (FCSR & 0x004FFFFF); // bit 22-0 561 break; 562 case 26: 563 data = (FCSR & 0xFFFC0000) | // move 31-18 564 Rt.uw<17:12> << 12 | // bit 17-12 565 (FCSR & 0x00000F80) << 7 | // bit 11-7 566 Rt.uw<6:2> << 2 | // bit 6-2 567 (FCSR & 0x00000002); // bit 1...0 568 break; 569 case 28: 570 data = (FCSR & 0xFE000000) | // move 31-25 571 Rt.uw<2:2> << 24 | // bit 24 572 (FCSR & 0x00FFF000) << 23 | // bit 23-12 573 Rt.uw<11:7> << 7 | // bit 24 574 (FCSR & 0x000007E) | 575 Rt.uw<1:0>; // bit 22-0 576 break; 577 case 31: 578 data = Rt.uw; 579 break; 580 default: 581 panic("FP Control Value (%d) " 582 "Not Available. Ignoring " 583 "Access to Floating Control " 584 "Status Register", FS); 585 } 586 xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); 587 }}); 588 default: CP0Unimpl::unknown(); 589 } 590 } 591 } 592 0xB: decode RD { 593 format MT_Control { 594 0x0: decode POS { 595 0x0: decode SEL { 596 0x1: decode SC { 597 0x0: dvpe({{ 598 MVPControlReg mvpControl = MVPControl; 599 VPEConf0Reg vpeConf0 = VPEConf0; 600 Rt = MVPControl; 601 if (vpeConf0.mvp == 1) 602 mvpControl.evp = 0; 603 MVPControl = mvpControl; 604 }}); 605 0x1: evpe({{ 606 MVPControlReg mvpControl = MVPControl; 607 VPEConf0Reg vpeConf0 = VPEConf0; 608 Rt = MVPControl; 609 if (vpeConf0.mvp == 1) 610 mvpControl.evp = 1; 611 MVPControl = mvpControl; 612 }}); 613 default:CP0Unimpl::unknown(); 614 } 615 default:CP0Unimpl::unknown(); 616 } 617 default:CP0Unimpl::unknown(); 618 } 619 0x1: decode POS { 620 0xF: decode SEL { 621 0x1: decode SC { 622 0x0: dmt({{ 623 VPEControlReg vpeControl = VPEControl; 624 Rt = vpeControl; 625 vpeControl.te = 0; 626 VPEControl = vpeControl; 627 }}); 628 0x1: emt({{ 629 VPEControlReg vpeControl = VPEControl; 630 Rt = vpeControl; 631 vpeControl.te = 1; 632 VPEControl = vpeControl; 633 }}); 634 default:CP0Unimpl::unknown(); 635 } 636 default:CP0Unimpl::unknown(); 637 } 638 default:CP0Unimpl::unknown(); 639 } 640 } 641 0xC: decode POS { 642 0x0: decode SC { 643 0x0: CP0Control::di({{ 644 StatusReg status = Status; 645 ConfigReg config = Config; 646 // Rev 2.0 or beyond? 647 if (config.ar >= 1) { 648 Rt = status; 649 status.ie = 0; 650 } else { 651 // Enable this else branch once we 652 // actually set values for Config on init 653 fault = new ReservedInstructionFault(); 654 } 655 Status = status; 656 }}); 657 0x1: CP0Control::ei({{ 658 StatusReg status = Status; 659 ConfigReg config = Config; 660 if (config.ar >= 1) { 661 Rt = status; 662 status.ie = 1; 663 } else { 664 fault = new ReservedInstructionFault(); 665 } 666 }}); 667 default:CP0Unimpl::unknown(); 668 } 669 } 670 default: CP0Unimpl::unknown(); 671 } 672 format CP0Control { 673 0xA: rdpgpr({{ 674 ConfigReg config = Config; 675 if (config.ar >= 1) { 676 // Rev 2 of the architecture 677 panic("Shadow Sets Not Fully Implemented.\n"); 678 } else { 679 fault = new ReservedInstructionFault(); 680 } 681 }}); 682 0xE: wrpgpr({{ 683 ConfigReg config = Config; 684 if (config.ar >= 1) { 685 // Rev 2 of the architecture 686 panic("Shadow Sets Not Fully Implemented.\n"); 687 } else { 688 fault = new ReservedInstructionFault(); 689 } 690 }}); 691 } 692 } 693 694 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 695 0x1: decode FUNCTION { 696 format CP0Control { 697 0x18: eret({{ 698 StatusReg status = Status; 699 ConfigReg config = Config; 700 SRSCtlReg srsCtl = SRSCtl; 701 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 702 if (status.erl == 1) { 703 status.erl = 0; 704 NPC = ErrorEPC; 705 // Need to adjust NNPC, otherwise things break 706 NNPC = ErrorEPC + sizeof(MachInst); 707 } else { 708 NPC = EPC; 709 // Need to adjust NNPC, otherwise things break 710 NNPC = EPC + sizeof(MachInst); 711 status.exl = 0; 712 if (config.ar >=1 && 713 srsCtl.hss > 0 && 714 status.bev == 0) { 715 srsCtl.css = srsCtl.pss; 716 //xc->setShadowSet(srsCtl.pss); 717 } 718 } 719 LLFlag = 0; 720 Status = status; 721 SRSCtl = srsCtl; 722 }}, IsReturn, IsSerializing, IsERET); 723 724 0x1F: deret({{ 725 DebugReg debug = Debug; 726 if (debug.dm == 1) { 727 debug.dm = 1; 728 debug.iexi = 0; 729 NPC = DEPC; 730 } else { 731 NPC = NPC; 732 // Undefined; 733 } 734 Debug = debug; 735 }}, IsReturn, IsSerializing, IsERET); 736 } 737 format CP0TLB { 738 0x01: tlbr({{ 739 MipsISA::PTE *PTEntry = 740 xc->tcBase()->getITBPtr()-> 741 getEntry(Index & 0x7FFFFFFF); 742 if (PTEntry == NULL) { 743 fatal("Invalid PTE Entry received on " 744 "a TLBR instruction\n"); 745 } 746 /* Setup PageMask */ 747 // If 1KB pages are not enabled, a read of PageMask 748 // must return 0b00 in bits 12, 11 749 PageMask = (PTEntry->Mask << 11); 750 /* Setup EntryHi */ 751 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 752 /* Setup Entry Lo0 */ 753 EntryLo0 = ((PTEntry->PFN0 << 6) | 754 (PTEntry->C0 << 3) | 755 (PTEntry->D0 << 2) | 756 (PTEntry->V0 << 1) | 757 PTEntry->G); 758 /* Setup Entry Lo1 */ 759 EntryLo1 = ((PTEntry->PFN1 << 6) | 760 (PTEntry->C1 << 3) | 761 (PTEntry->D1 << 2) | 762 (PTEntry->V1 << 1) | 763 PTEntry->G); 764 }}); // Need to hook up to TLB 765 766 0x02: tlbwi({{ 767 //Create PTE 768 MipsISA::PTE newEntry; 769 //Write PTE 770 newEntry.Mask = (Addr)(PageMask >> 11); 771 newEntry.VPN = (Addr)(EntryHi >> 11); 772 /* PageGrain _ ESP Config3 _ SP */ 773 if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { 774 // If 1KB pages are *NOT* enabled, lowest bits of 775 // the mask are 0b11 for TLB writes 776 newEntry.Mask |= 0x3; 777 // Reset bits 0 and 1 if 1KB pages are not enabled 778 newEntry.VPN &= 0xFFFFFFFC; 779 } 780 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 781 782 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 783 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 784 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 785 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 786 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 787 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 788 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 789 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 790 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 791 /* Now, compute the AddrShiftAmount and OffsetMask - 792 TLB optimizations */ 793 /* Addr Shift Amount for 1KB or larger pages */ 794 if ((newEntry.Mask & 0xFFFF) == 3) { 795 newEntry.AddrShiftAmount = 12; 796 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 797 newEntry.AddrShiftAmount = 10; 798 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 799 newEntry.AddrShiftAmount = 14; 800 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 801 newEntry.AddrShiftAmount = 16; 802 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 803 newEntry.AddrShiftAmount = 18; 804 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 805 newEntry.AddrShiftAmount = 20; 806 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 807 newEntry.AddrShiftAmount = 22; 808 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 809 newEntry.AddrShiftAmount = 24; 810 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 811 newEntry.AddrShiftAmount = 26; 812 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 813 newEntry.AddrShiftAmount = 28; 814 } else { 815 fatal("Invalid Mask Pattern Detected!\n"); 816 } 817 newEntry.OffsetMask = 818 (1 << newEntry.AddrShiftAmount) - 1; 819 820 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 821 Config3Reg config3 = Config3; 822 PageGrainReg pageGrain = PageGrain; 823 int SP = 0; 824 if (bits(config3, config3.sp) == 1 && 825 bits(pageGrain, pageGrain.esp) == 1) { 826 SP = 1; 827 } 828 IndexReg index = Index; 829 Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 830 }}); 831 0x06: tlbwr({{ 832 //Create PTE 833 MipsISA::PTE newEntry; 834 //Write PTE 835 newEntry.Mask = (Addr)(PageMask >> 11); 836 newEntry.VPN = (Addr)(EntryHi >> 11); 837 /* PageGrain _ ESP Config3 _ SP */ 838 if (bits(PageGrain, 28) == 0 || 839 bits(Config3, 4) == 0) { 840 // If 1KB pages are *NOT* enabled, lowest bits of 841 // the mask are 0b11 for TLB writes 842 newEntry.Mask |= 0x3; 843 // Reset bits 0 and 1 if 1KB pages are not enabled 844 newEntry.VPN &= 0xFFFFFFFC; 845 } 846 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 847 848 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 849 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 850 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 851 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 852 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 853 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 854 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 855 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 856 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 857 /* Now, compute the AddrShiftAmount and OffsetMask - 858 TLB optimizations */ 859 /* Addr Shift Amount for 1KB or larger pages */ 860 if ((newEntry.Mask & 0xFFFF) == 3){ 861 newEntry.AddrShiftAmount = 12; 862 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 863 newEntry.AddrShiftAmount = 10; 864 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 865 newEntry.AddrShiftAmount = 14; 866 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 867 newEntry.AddrShiftAmount = 16; 868 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 869 newEntry.AddrShiftAmount = 18; 870 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 871 newEntry.AddrShiftAmount = 20; 872 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 873 newEntry.AddrShiftAmount = 22; 874 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 875 newEntry.AddrShiftAmount = 24; 876 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 877 newEntry.AddrShiftAmount = 26; 878 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 879 newEntry.AddrShiftAmount = 28; 880 } else { 881 fatal("Invalid Mask Pattern Detected!\n"); 882 } 883 newEntry.OffsetMask = 884 (1 << newEntry.AddrShiftAmount) - 1; 885 886 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 887 Config3Reg config3 = Config3; 888 PageGrainReg pageGrain = PageGrain; 889 int SP = 0; 890 if (bits(config3, config3.sp) == 1 && 891 bits(pageGrain, pageGrain.esp) == 1) { 892 SP = 1; 893 } 894 IndexReg index = Index; 895 Ptr->insertAt(newEntry, Random, SP); 896 }}); 897 898 0x08: tlbp({{ 899 Config3Reg config3 = Config3; 900 PageGrainReg pageGrain = PageGrain; 901 EntryHiReg entryHi = EntryHi; 902 int tlbIndex; 903 Addr vpn; 904 if (pageGrain.esp == 1 && config3.sp ==1) { 905 vpn = EntryHi >> 11; 906 } else { 907 // Mask off lower 2 bits 908 vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 909 } 910 tlbIndex = xc->tcBase()->getITBPtr()-> 911 probeEntry(vpn, entryHi.asid); 912 // Check TLB for entry matching EntryHi 913 if (tlbIndex != -1) { 914 Index = tlbIndex; 915 } else { 916 // else, set Index = 1 << 31 917 Index = (1 << 31); 918 } 919 }}); 920 } 921 format CP0Unimpl { 922 0x20: wait(); 923 } 924 default: CP0Unimpl::unknown(); 925 } 926 } 927 928 //Table A-13 MIPS32 COP1 Encoding of rs Field 929 0x1: decode RS_MSB { 930 0x0: decode RS_HI { 931 0x0: decode RS_LO { 932 format CP1Control { 933 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 934 935 0x2: cfc1({{ 936 switch (FS) { 937 case 0: 938 Rt = FIR; 939 break; 940 case 25: 941 Rt = (FCSR & 0xFE000000) >> 24 | 942 (FCSR & 0x00800000) >> 23; 943 break; 944 case 26: 945 Rt = (FCSR & 0x0003F07C); 946 break; 947 case 28: 948 Rt = (FCSR & 0x00000F80) | 949 (FCSR & 0x01000000) >> 21 | 950 (FCSR & 0x00000003); 951 break; 952 case 31: 953 Rt = FCSR; 954 break; 955 default: 956 warn("FP Control Value (%d) Not Valid"); 957 } 958 }}); 959 960 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>; }}); 961 962 0x4: mtc1({{ Fs.uw = Rt.uw; }}); 963 964 0x6: ctc1({{ 965 switch (FS) { 966 case 25: 967 FCSR = (Rt.uw<7:1> << 25) | // move 31-25 968 (FCSR & 0x01000000) | // bit 24 969 (FCSR & 0x004FFFFF); // bit 22-0 970 break; 971 case 26: 972 FCSR = (FCSR & 0xFFFC0000) | // move 31-18 973 Rt.uw<17:12> << 12 | // bit 17-12 974 (FCSR & 0x00000F80) << 7 | // bit 11-7 975 Rt.uw<6:2> << 2 | // bit 6-2 976 (FCSR & 0x00000002); // bit 1-0 977 break; 978 case 28: 979 FCSR = (FCSR & 0xFE000000) | // move 31-25 980 Rt.uw<2:2> << 24 | // bit 24 981 (FCSR & 0x00FFF000) << 23 | // bit 23-12 982 Rt.uw<11:7> << 7 | // bit 24 983 (FCSR & 0x000007E) | 984 Rt.uw<1:0>; // bit 22-0 985 break; 986 case 31: 987 FCSR = Rt.uw; 988 break; 989 990 default: 991 panic("FP Control Value (%d) " 992 "Not Available. Ignoring Access " 993 "to Floating Control Status " 994 "Register", FS); 995 } 996 }}); 997 998 0x7: mthc1({{ 999 uint64_t fs_hi = Rt.uw; 1000 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 1001 Fs.ud = (fs_hi << 32) | fs_lo; 1002 }}); 1003 1004 } 1005 format CP1Unimpl { 1006 0x1: dmfc1(); 1007 0x5: dmtc1(); 1008 } 1009 } 1010 1011 0x1: decode RS_LO { 1012 0x0: decode ND { 1013 format Branch { 1014 0x0: decode TF { 1015 0x0: bc1f({{ 1016 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1017 }}); 1018 0x1: bc1t({{ 1019 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1020 }}); 1021 } 1022 0x1: decode TF { 1023 0x0: bc1fl({{ 1024 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1025 }}, Likely); 1026 0x1: bc1tl({{ 1027 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1028 }}, Likely); 1029 } 1030 } 1031 } 1032 format CP1Unimpl { 1033 0x1: bc1any2(); 1034 0x2: bc1any4(); 1035 default: unknown(); 1036 } 1037 } 1038 } 1039 1040 0x1: decode RS_HI { 1041 0x2: decode RS_LO { 1042 //Table A-14 MIPS32 COP1 Encoding of Function Field When 1043 //rs=S (( single-precision floating point)) 1044 0x0: decode FUNCTION_HI { 1045 0x0: decode FUNCTION_LO { 1046 format FloatOp { 1047 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf; }}); 1048 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf; }}); 1049 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf; }}); 1050 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf; }}); 1051 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf); }}); 1052 0x5: abs_s({{ Fd.sf = fabs(Fs.sf); }}); 1053 0x7: neg_s({{ Fd.sf = -Fs.sf; }}); 1054 } 1055 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf; }}); 1056 } 1057 0x1: decode FUNCTION_LO { 1058 format FloatConvertOp { 1059 0x0: round_l_s({{ val = Fs.sf; }}, 1060 ToLong, Round); 1061 0x1: trunc_l_s({{ val = Fs.sf; }}, 1062 ToLong, Trunc); 1063 0x2: ceil_l_s({{ val = Fs.sf;}}, 1064 ToLong, Ceil); 1065 0x3: floor_l_s({{ val = Fs.sf; }}, 1066 ToLong, Floor); 1067 0x4: round_w_s({{ val = Fs.sf; }}, 1068 ToWord, Round); 1069 0x5: trunc_w_s({{ val = Fs.sf; }}, 1070 ToWord, Trunc); 1071 0x6: ceil_w_s({{ val = Fs.sf; }}, 1072 ToWord, Ceil); 1073 0x7: floor_w_s({{ val = Fs.sf; }}, 1074 ToWord, Floor); 1075 } 1076 } 1077 1078 0x2: decode FUNCTION_LO { 1079 0x1: decode MOVCF { 1080 format BasicOp { 1081 0x0: movf_s({{ 1082 Fd = (getCondCode(FCSR,CC) == 0) ? 1083 Fs : Fd; 1084 }}); 1085 0x1: movt_s({{ 1086 Fd = (getCondCode(FCSR,CC) == 1) ? 1087 Fs : Fd; 1088 }}); 1089 } 1090 } 1091 1092 format BasicOp { 1093 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1094 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1095 } 1096 1097 format FloatOp { 1098 0x5: recip_s({{ Fd = 1 / Fs; }}); 1099 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 1100 } 1101 format CP1Unimpl { 1102 default: unknown(); 1103 } 1104 } 1105 0x3: CP1Unimpl::unknown(); 1106 1107 0x4: decode FUNCTION_LO { 1108 format FloatConvertOp { 1109 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 1110 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 1111 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 1112 } 1113 1114 0x6: FloatOp::cvt_ps_s({{ 1115 Fd.ud = (uint64_t) Fs.uw << 32 | 1116 (uint64_t) Ft.uw; 1117 }}); 1118 format CP1Unimpl { 1119 default: unknown(); 1120 } 1121 } 1122 0x5: CP1Unimpl::unknown(); 1123 1124 0x6: decode FUNCTION_LO { 1125 format FloatCompareOp { 1126 0x0: c_f_s({{ cond = 0; }}, 1127 SinglePrecision, UnorderedFalse); 1128 0x1: c_un_s({{ cond = 0; }}, 1129 SinglePrecision, UnorderedTrue); 1130 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 1131 UnorderedFalse); 1132 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 1133 UnorderedTrue); 1134 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 1135 UnorderedFalse); 1136 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 1137 UnorderedTrue); 1138 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }}, 1139 UnorderedFalse); 1140 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }}, 1141 UnorderedTrue); 1142 } 1143 } 1144 1145 0x7: decode FUNCTION_LO { 1146 format FloatCompareOp { 1147 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1148 UnorderedFalse, QnanException); 1149 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1150 UnorderedTrue, QnanException); 1151 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf); }}, 1152 UnorderedFalse, QnanException); 1153 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 1154 UnorderedTrue, QnanException); 1155 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 1156 UnorderedFalse, QnanException); 1157 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 1158 UnorderedTrue, QnanException); 1159 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 1160 UnorderedFalse, QnanException); 1161 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 1162 UnorderedTrue, QnanException); 1163 } 1164 } 1165 } 1166 1167 //Table A-15 MIPS32 COP1 Encoding of Function Field When 1168 //rs=D 1169 0x1: decode FUNCTION_HI { 1170 0x0: decode FUNCTION_LO { 1171 format FloatOp { 1172 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 1173 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 1174 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 1175 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); 1176 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 1177 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 1178 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); 1179 } 1180 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); 1181 } 1182 1183 0x1: decode FUNCTION_LO { 1184 format FloatConvertOp { 1185 0x0: round_l_d({{ val = Fs.df; }}, 1186 ToLong, Round); 1187 0x1: trunc_l_d({{ val = Fs.df; }}, 1188 ToLong, Trunc); 1189 0x2: ceil_l_d({{ val = Fs.df; }}, 1190 ToLong, Ceil); 1191 0x3: floor_l_d({{ val = Fs.df; }}, 1192 ToLong, Floor); 1193 0x4: round_w_d({{ val = Fs.df; }}, 1194 ToWord, Round); 1195 0x5: trunc_w_d({{ val = Fs.df; }}, 1196 ToWord, Trunc); 1197 0x6: ceil_w_d({{ val = Fs.df; }}, 1198 ToWord, Ceil); 1199 0x7: floor_w_d({{ val = Fs.df; }}, 1200 ToWord, Floor); 1201 } 1202 } 1203 1204 0x2: decode FUNCTION_LO { 1205 0x1: decode MOVCF { 1206 format BasicOp { 1207 0x0: movf_d({{ 1208 Fd.df = (getCondCode(FCSR,CC) == 0) ? 1209 Fs.df : Fd.df; 1210 }}); 1211 0x1: movt_d({{ 1212 Fd.df = (getCondCode(FCSR,CC) == 1) ? 1213 Fs.df : Fd.df; 1214 }}); 1215 } 1216 } 1217 1218 format BasicOp { 1219 0x2: movz_d({{ 1220 Fd.df = (Rt == 0) ? Fs.df : Fd.df; 1221 }}); 1222 0x3: movn_d({{ 1223 Fd.df = (Rt != 0) ? Fs.df : Fd.df; 1224 }}); 1225 } 1226 1227 format FloatOp { 1228 0x5: recip_d({{ Fd.df = 1 / Fs.df; }}); 1229 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df); }}); 1230 } 1231 format CP1Unimpl { 1232 default: unknown(); 1233 } 1234 1235 } 1236 0x4: decode FUNCTION_LO { 1237 format FloatConvertOp { 1238 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 1239 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 1240 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 1241 } 1242 default: CP1Unimpl::unknown(); 1243 } 1244 1245 0x6: decode FUNCTION_LO { 1246 format FloatCompareOp { 1247 0x0: c_f_d({{ cond = 0; }}, 1248 DoublePrecision, UnorderedFalse); 1249 0x1: c_un_d({{ cond = 0; }}, 1250 DoublePrecision, UnorderedTrue); 1251 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 1252 UnorderedFalse); 1253 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 1254 UnorderedTrue); 1255 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 1256 UnorderedFalse); 1257 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 1258 UnorderedTrue); 1259 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }}, 1260 UnorderedFalse); 1261 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }}, 1262 UnorderedTrue); 1263 } 1264 } 1265 1266 0x7: decode FUNCTION_LO { 1267 format FloatCompareOp { 1268 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1269 UnorderedFalse, QnanException); 1270 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1271 UnorderedTrue, QnanException); 1272 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }}, 1273 UnorderedFalse, QnanException); 1274 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }}, 1275 UnorderedTrue, QnanException); 1276 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }}, 1277 UnorderedFalse, QnanException); 1278 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 1279 UnorderedTrue, QnanException); 1280 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 1281 UnorderedFalse, QnanException); 1282 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 1283 UnorderedTrue, QnanException); 1284 } 1285 } 1286 default: CP1Unimpl::unknown(); 1287 } 1288 0x2: CP1Unimpl::unknown(); 1289 0x3: CP1Unimpl::unknown(); 1290 0x7: CP1Unimpl::unknown(); 1291 1292 //Table A-16 MIPS32 COP1 Encoding of Function 1293 //Field When rs=W 1294 0x4: decode FUNCTION { 1295 format FloatConvertOp { 1296 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 1297 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 1298 0x26: CP1Unimpl::cvt_ps_w(); 1299 } 1300 default: CP1Unimpl::unknown(); 1301 } 1302 1303 //Table A-16 MIPS32 COP1 Encoding of Function Field 1304 //When rs=L1 1305 //Note: "1. Format type L is legal only if 64-bit 1306 //floating point operations are enabled." 1307 0x5: decode FUNCTION_HI { 1308 format FloatConvertOp { 1309 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 1310 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 1311 0x26: CP1Unimpl::cvt_ps_l(); 1312 } 1313 default: CP1Unimpl::unknown(); 1314 } 1315 1316 //Table A-17 MIPS64 COP1 Encoding of Function Field 1317 //When rs=PS1 1318 //Note: "1. Format type PS is legal only if 64-bit 1319 //floating point operations are enabled. " 1320 0x6: decode FUNCTION_HI { 1321 0x0: decode FUNCTION_LO { 1322 format Float64Op { 1323 0x0: add_ps({{ 1324 Fd1.sf = Fs1.sf + Ft2.sf; 1325 Fd2.sf = Fs2.sf + Ft2.sf; 1326 }}); 1327 0x1: sub_ps({{ 1328 Fd1.sf = Fs1.sf - Ft2.sf; 1329 Fd2.sf = Fs2.sf - Ft2.sf; 1330 }}); 1331 0x2: mul_ps({{ 1332 Fd1.sf = Fs1.sf * Ft2.sf; 1333 Fd2.sf = Fs2.sf * Ft2.sf; 1334 }}); 1335 0x5: abs_ps({{ 1336 Fd1.sf = fabs(Fs1.sf); 1337 Fd2.sf = fabs(Fs2.sf); 1338 }}); 1339 0x6: mov_ps({{ 1340 Fd1.sf = Fs1.sf; 1341 Fd2.sf = Fs2.sf; 1342 }}); 1343 0x7: neg_ps({{ 1344 Fd1.sf = -(Fs1.sf); 1345 Fd2.sf = -(Fs2.sf); 1346 }}); 1347 default: CP1Unimpl::unknown(); 1348 } 1349 } 1350 0x1: CP1Unimpl::unknown(); 1351 0x2: decode FUNCTION_LO { 1352 0x1: decode MOVCF { 1353 format Float64Op { 1354 0x0: movf_ps({{ 1355 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1356 Fs1 : Fd1; 1357 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1358 Fs2 : Fd2; 1359 }}); 1360 0x1: movt_ps({{ 1361 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1362 Fs1 : Fd1; 1363 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1364 Fs2 : Fd2; 1365 }}); 1366 } 1367 } 1368 1369 format Float64Op { 1370 0x2: movz_ps({{ 1371 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1372 Fs1 : Fd1; 1373 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1374 Fs2 : Fd2; 1375 }}); 1376 0x3: movn_ps({{ 1377 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1378 Fs1 : Fd1; 1379 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1380 Fs2 : Fd2; 1381 }}); 1382 } 1383 default: CP1Unimpl::unknown(); 1384 } 1385 0x3: CP1Unimpl::unknown(); 1386 0x4: decode FUNCTION_LO { 1387 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 1388 default: CP1Unimpl::unknown(); 1389 } 1390 1391 0x5: decode FUNCTION_LO { 1392 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); 1393 format Float64Op { 1394 0x4: pll({{ 1395 Fd.ud = (uint64_t)Fs1.uw << 32 | Ft1.uw; 1396 }}); 1397 0x5: plu({{ 1398 Fd.ud = (uint64_t)Fs1.uw << 32 | Ft2.uw; 1399 }}); 1400 0x6: pul({{ 1401 Fd.ud = (uint64_t)Fs2.uw << 32 | Ft1.uw; 1402 }}); 1403 0x7: puu({{ 1404 Fd.ud = (uint64_t)Fs2.uw << 32 | Ft2.uw; 1405 }}); 1406 } 1407 default: CP1Unimpl::unknown(); 1408 } 1409 1410 0x6: decode FUNCTION_LO { 1411 format FloatPSCompareOp { 1412 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1413 UnorderedFalse); 1414 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1415 UnorderedTrue); 1416 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1417 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1418 UnorderedFalse); 1419 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1420 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1421 UnorderedTrue); 1422 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1423 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1424 UnorderedFalse); 1425 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }}, 1426 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1427 UnorderedTrue); 1428 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }}, 1429 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1430 UnorderedFalse); 1431 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1432 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1433 UnorderedTrue); 1434 } 1435 } 1436 1437 0x7: decode FUNCTION_LO { 1438 format FloatPSCompareOp { 1439 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1440 UnorderedFalse, QnanException); 1441 0x1: c_ngle_ps({{ cond1 = 0; }}, 1442 {{ cond2 = 0; }}, 1443 UnorderedTrue, QnanException); 1444 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1445 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1446 UnorderedFalse, QnanException); 1447 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1448 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1449 UnorderedTrue, QnanException); 1450 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1451 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1452 UnorderedFalse, QnanException); 1453 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1454 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1455 UnorderedTrue, QnanException); 1456 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1457 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1458 UnorderedFalse, QnanException); 1459 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1460 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1461 UnorderedTrue, QnanException); 1462 } 1463 } 1464 } 1465 } 1466 default: CP1Unimpl::unknown(); 1467 } 1468 } 1469 1470 //Table A-19 MIPS32 COP2 Encoding of rs Field 1471 0x2: decode RS_MSB { 1472 format CP2Unimpl { 1473 0x0: decode RS_HI { 1474 0x0: decode RS_LO { 1475 0x0: mfc2(); 1476 0x2: cfc2(); 1477 0x3: mfhc2(); 1478 0x4: mtc2(); 1479 0x6: ctc2(); 1480 0x7: mftc2(); 1481 default: unknown(); 1482 } 1483 1484 0x1: decode ND { 1485 0x0: decode TF { 1486 0x0: bc2f(); 1487 0x1: bc2t(); 1488 default: unknown(); 1489 } 1490 1491 0x1: decode TF { 1492 0x0: bc2fl(); 1493 0x1: bc2tl(); 1494 default: unknown(); 1495 } 1496 default: unknown(); 1497 1498 } 1499 default: unknown(); 1500 } 1501 default: unknown(); 1502 } 1503 } 1504 1505 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1506 //Note: "COP1X instructions are legal only if 64-bit floating point 1507 //operations are enabled." 1508 0x3: decode FUNCTION_HI { 1509 0x0: decode FUNCTION_LO { 1510 format LoadIndexedMemory { 1511 0x0: lwxc1({{ Fd.uw = Mem.uw; }}); 1512 0x1: ldxc1({{ Fd.ud = Mem.ud; }}); 1513 0x5: luxc1({{ Fd.ud = Mem.ud; }}, 1514 {{ EA = (Rs + Rt) & ~7; }}); 1515 } 1516 } 1517 1518 0x1: decode FUNCTION_LO { 1519 format StoreIndexedMemory { 1520 0x0: swxc1({{ Mem.uw = Fs.uw; }}); 1521 0x1: sdxc1({{ Mem.ud = Fs.ud; }}); 1522 0x5: suxc1({{ Mem.ud = Fs.ud; }}, 1523 {{ EA = (Rs + Rt) & ~7; }}); 1524 } 1525 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1526 } 1527 1528 0x3: decode FUNCTION_LO { 1529 0x6: Float64Op::alnv_ps({{ 1530 if (Rs<2:0> == 0) { 1531 Fd.ud = Fs.ud; 1532 } else if (Rs<2:0> == 4) { 1533#if BYTE_ORDER == BIG_ENDIAN 1534 Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>; 1535#elif BYTE_ORDER == LITTLE_ENDIAN 1536 Fd.ud = Ft.ud<31:0> << 32 | Fs.ud<63:32>; 1537#endif 1538 } else { 1539 Fd.ud = Fd.ud; 1540 } 1541 }}); 1542 } 1543 1544 format FloatAccOp { 1545 0x4: decode FUNCTION_LO { 1546 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 1547 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 1548 0x6: madd_ps({{ 1549 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; 1550 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; 1551 }}); 1552 } 1553 1554 0x5: decode FUNCTION_LO { 1555 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); 1556 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 1557 0x6: msub_ps({{ 1558 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; 1559 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; 1560 }}); 1561 } 1562 1563 0x6: decode FUNCTION_LO { 1564 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1565 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 1566 0x6: nmadd_ps({{ 1567 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df); 1568 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df); 1569 }}); 1570 } 1571 1572 0x7: decode FUNCTION_LO { 1573 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1574 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 1575 0x6: nmsub_ps({{ 1576 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 1577 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 1578 }}); 1579 } 1580 } 1581 } 1582 1583 format Branch { 1584 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 1585 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 1586 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 1587 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 1588 } 1589 } 1590 1591 0x3: decode OPCODE_LO { 1592 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1593 0x4: decode FUNCTION_HI { 1594 0x0: decode FUNCTION_LO { 1595 0x2: IntOp::mul({{ 1596 int64_t temp1 = Rs.sd * Rt.sd; 1597 Rd.sw = temp1<31:0>; 1598 }}, IntMultOp); 1599 1600 format HiLoRdSelValOp { 1601 0x0: madd({{ 1602 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1603 (Rs.sd * Rt.sd); 1604 }}, IntMultOp); 1605 0x1: maddu({{ 1606 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1607 (Rs.ud * Rt.ud); 1608 }}, IntMultOp); 1609 0x4: msub({{ 1610 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1611 (Rs.sd * Rt.sd); 1612 }}, IntMultOp); 1613 0x5: msubu({{ 1614 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1615 (Rs.ud * Rt.ud); 1616 }}, IntMultOp); 1617 } 1618 } 1619 1620 0x4: decode FUNCTION_LO { 1621 format BasicOp { 1622 0x0: clz({{ 1623 int cnt = 32; 1624 for (int idx = 31; idx >= 0; idx--) { 1625 if (Rs<idx:idx> == 1) { 1626 cnt = 31 - idx; 1627 break; 1628 } 1629 } 1630 Rd.uw = cnt; 1631 }}); 1632 0x1: clo({{ 1633 int cnt = 32; 1634 for (int idx = 31; idx >= 0; idx--) { 1635 if (Rs<idx:idx> == 0) { 1636 cnt = 31 - idx; 1637 break; 1638 } 1639 } 1640 Rd.uw = cnt; 1641 }}); 1642 } 1643 } 1644 1645 0x7: decode FUNCTION_LO { 1646 0x7: FailUnimpl::sdbbp(); 1647 } 1648 } 1649 1650 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1651 //of the Architecture 1652 0x7: decode FUNCTION_HI { 1653 0x0: decode FUNCTION_LO { 1654 format BasicOp { 1655 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); 1656 0x4: ins({{ 1657 Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 1658 bits(Rs.uw, MSB-LSB, 0) << LSB | 1659 bits(Rt.uw, LSB-1, 0); 1660 }}); 1661 } 1662 } 1663 1664 0x1: decode FUNCTION_LO { 1665 format MT_Control { 1666 0x0: fork({{ 1667 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1668 }}, UserMode); 1669 0x1: yield({{ 1670 Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, 1671 YQMask); 1672 }}, UserMode); 1673 } 1674 1675 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1676 0x2: decode OP_HI { 1677 0x0: decode OP_LO { 1678 format LoadIndexedMemory { 1679 0x0: lwx({{ Rd.sw = Mem.sw; }}); 1680 0x4: lhx({{ Rd.sw = Mem.sh; }}); 1681 0x6: lbux({{ Rd.uw = Mem.ub; }}); 1682 } 1683 } 1684 } 1685 0x4: DspIntOp::insv({{ 1686 int pos = dspctl<5:0>; 1687 int size = dspctl<12:7> - 1; 1688 Rt.uw = insertBits(Rt.uw, pos+size, 1689 pos, Rs.uw<size:0>); 1690 }}); 1691 } 1692 1693 0x2: decode FUNCTION_LO { 1694 1695 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1696 //(DSP ASE MANUAL) 1697 0x0: decode OP_HI { 1698 0x0: decode OP_LO { 1699 format DspIntOp { 1700 0x0: addu_qb({{ 1701 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1702 NOSATURATE, UNSIGNED, &dspctl); 1703 }}); 1704 0x1: subu_qb({{ 1705 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, 1706 NOSATURATE, UNSIGNED, &dspctl); 1707 }}); 1708 0x4: addu_s_qb({{ 1709 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1710 SATURATE, UNSIGNED, &dspctl); 1711 }}); 1712 0x5: subu_s_qb({{ 1713 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, 1714 SATURATE, UNSIGNED, &dspctl); 1715 }}); 1716 0x6: muleu_s_ph_qbl({{ 1717 Rd.uw = dspMuleu(Rs.uw, Rt.uw, 1718 MODE_L, &dspctl); 1719 }}, IntMultOp); 1720 0x7: muleu_s_ph_qbr({{ 1721 Rd.uw = dspMuleu(Rs.uw, Rt.uw, 1722 MODE_R, &dspctl); 1723 }}, IntMultOp); 1724 } 1725 } 1726 0x1: decode OP_LO { 1727 format DspIntOp { 1728 0x0: addu_ph({{ 1729 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1730 NOSATURATE, UNSIGNED, &dspctl); 1731 }}); 1732 0x1: subu_ph({{ 1733 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1734 NOSATURATE, UNSIGNED, &dspctl); 1735 }}); 1736 0x2: addq_ph({{ 1737 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1738 NOSATURATE, SIGNED, &dspctl); 1739 }}); 1740 0x3: subq_ph({{ 1741 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1742 NOSATURATE, SIGNED, &dspctl); 1743 }}); 1744 0x4: addu_s_ph({{ 1745 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1746 SATURATE, UNSIGNED, &dspctl); 1747 }}); 1748 0x5: subu_s_ph({{ 1749 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1750 SATURATE, UNSIGNED, &dspctl); 1751 }}); 1752 0x6: addq_s_ph({{ 1753 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1754 SATURATE, SIGNED, &dspctl); 1755 }}); 1756 0x7: subq_s_ph({{ 1757 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1758 SATURATE, SIGNED, &dspctl); 1759 }}); 1760 } 1761 } 1762 0x2: decode OP_LO { 1763 format DspIntOp { 1764 0x0: addsc({{ 1765 int64_t dresult; 1766 dresult = Rs.ud + Rt.ud; 1767 Rd.sw = dresult<31:0>; 1768 dspctl = insertBits(dspctl, 13, 13, 1769 dresult<32:32>); 1770 }}); 1771 0x1: addwc({{ 1772 int64_t dresult; 1773 dresult = Rs.sd + Rt.sd + dspctl<13:13>; 1774 Rd.sw = dresult<31:0>; 1775 if (dresult<32:32> != dresult<31:31>) 1776 dspctl = insertBits(dspctl, 20, 20, 1); 1777 }}); 1778 0x2: modsub({{ 1779 Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : 1780 Rs.sw - Rt.sw<7:0>; 1781 }}); 1782 0x4: raddu_w_qb({{ 1783 Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + 1784 Rs.uw<15:8> + Rs.uw<7:0>; 1785 }}); 1786 0x6: addq_s_w({{ 1787 Rd.sw = dspAdd(Rs.sw, Rt.sw, SIMD_FMT_W, 1788 SATURATE, SIGNED, &dspctl); 1789 }}); 1790 0x7: subq_s_w({{ 1791 Rd.sw = dspSub(Rs.sw, Rt.sw, SIMD_FMT_W, 1792 SATURATE, SIGNED, &dspctl); 1793 }}); 1794 } 1795 } 1796 0x3: decode OP_LO { 1797 format DspIntOp { 1798 0x4: muleq_s_w_phl({{ 1799 Rd.sw = dspMuleq(Rs.sw, Rt.sw, 1800 MODE_L, &dspctl); 1801 }}, IntMultOp); 1802 0x5: muleq_s_w_phr({{ 1803 Rd.sw = dspMuleq(Rs.sw, Rt.sw, 1804 MODE_R, &dspctl); 1805 }}, IntMultOp); 1806 0x6: mulq_s_ph({{ 1807 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, 1808 SATURATE, NOROUND, &dspctl); 1809 }}, IntMultOp); 1810 0x7: mulq_rs_ph({{ 1811 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, 1812 SATURATE, ROUND, &dspctl); 1813 }}, IntMultOp); 1814 } 1815 } 1816 } 1817 1818 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1819 //(DSP ASE MANUAL) 1820 0x1: decode OP_HI { 1821 0x0: decode OP_LO { 1822 format DspIntOp { 1823 0x0: cmpu_eq_qb({{ 1824 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1825 UNSIGNED, CMP_EQ, &dspctl); 1826 }}); 1827 0x1: cmpu_lt_qb({{ 1828 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1829 UNSIGNED, CMP_LT, &dspctl); 1830 }}); 1831 0x2: cmpu_le_qb({{ 1832 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1833 UNSIGNED, CMP_LE, &dspctl); 1834 }}); 1835 0x3: pick_qb({{ 1836 Rd.uw = dspPick(Rs.uw, Rt.uw, 1837 SIMD_FMT_QB, &dspctl); 1838 }}); 1839 0x4: cmpgu_eq_qb({{ 1840 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1841 UNSIGNED, CMP_EQ ); 1842 }}); 1843 0x5: cmpgu_lt_qb({{ 1844 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1845 UNSIGNED, CMP_LT); 1846 }}); 1847 0x6: cmpgu_le_qb({{ 1848 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1849 UNSIGNED, CMP_LE); 1850 }}); 1851 } 1852 } 1853 0x1: decode OP_LO { 1854 format DspIntOp { 1855 0x0: cmp_eq_ph({{ 1856 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1857 SIGNED, CMP_EQ, &dspctl); 1858 }}); 1859 0x1: cmp_lt_ph({{ 1860 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1861 SIGNED, CMP_LT, &dspctl); 1862 }}); 1863 0x2: cmp_le_ph({{ 1864 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1865 SIGNED, CMP_LE, &dspctl); 1866 }}); 1867 0x3: pick_ph({{ 1868 Rd.uw = dspPick(Rs.uw, Rt.uw, 1869 SIMD_FMT_PH, &dspctl); 1870 }}); 1871 0x4: precrq_qb_ph({{ 1872 Rd.uw = Rs.uw<31:24> << 24 | 1873 Rs.uw<15:8> << 16 | 1874 Rt.uw<31:24> << 8 | 1875 Rt.uw<15:8>; 1876 }}); 1877 0x5: precr_qb_ph({{ 1878 Rd.uw = Rs.uw<23:16> << 24 | 1879 Rs.uw<7:0> << 16 | 1880 Rt.uw<23:16> << 8 | 1881 Rt.uw<7:0>; 1882 }}); 1883 0x6: packrl_ph({{ 1884 Rd.uw = dspPack(Rs.uw, Rt.uw, SIMD_FMT_PH); 1885 }}); 1886 0x7: precrqu_s_qb_ph({{ 1887 Rd.uw = dspPrecrqu(Rs.uw, Rt.uw, &dspctl); 1888 }}); 1889 } 1890 } 1891 0x2: decode OP_LO { 1892 format DspIntOp { 1893 0x4: precrq_ph_w({{ 1894 Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; 1895 }}); 1896 0x5: precrq_rs_ph_w({{ 1897 Rd.uw = dspPrecrq(Rs.uw, Rt.uw, 1898 SIMD_FMT_W, &dspctl); 1899 }}); 1900 } 1901 } 1902 0x3: decode OP_LO { 1903 format DspIntOp { 1904 0x0: cmpgdu_eq_qb({{ 1905 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1906 UNSIGNED, CMP_EQ, &dspctl); 1907 }}); 1908 0x1: cmpgdu_lt_qb({{ 1909 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1910 UNSIGNED, CMP_LT, &dspctl); 1911 }}); 1912 0x2: cmpgdu_le_qb({{ 1913 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1914 UNSIGNED, CMP_LE, &dspctl); 1915 }}); 1916 0x6: precr_sra_ph_w({{ 1917 Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, 1918 SIMD_FMT_W, NOROUND); 1919 }}); 1920 0x7: precr_sra_r_ph_w({{ 1921 Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, 1922 SIMD_FMT_W, ROUND); 1923 }}); 1924 } 1925 } 1926 } 1927 1928 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1929 //(DSP ASE MANUAL) 1930 0x2: decode OP_HI { 1931 0x0: decode OP_LO { 1932 format DspIntOp { 1933 0x1: absq_s_qb({{ 1934 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_QB, &dspctl); 1935 }}); 1936 0x2: repl_qb({{ 1937 Rd.uw = RS_RT<7:0> << 24 | 1938 RS_RT<7:0> << 16 | 1939 RS_RT<7:0> << 8 | 1940 RS_RT<7:0>; 1941 }}); 1942 0x3: replv_qb({{ 1943 Rd.sw = Rt.uw<7:0> << 24 | 1944 Rt.uw<7:0> << 16 | 1945 Rt.uw<7:0> << 8 | 1946 Rt.uw<7:0>; 1947 }}); 1948 0x4: precequ_ph_qbl({{ 1949 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1950 SIMD_FMT_PH, SIGNED, MODE_L); 1951 }}); 1952 0x5: precequ_ph_qbr({{ 1953 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1954 SIMD_FMT_PH, SIGNED, MODE_R); 1955 }}); 1956 0x6: precequ_ph_qbla({{ 1957 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1958 SIMD_FMT_PH, SIGNED, MODE_LA); 1959 }}); 1960 0x7: precequ_ph_qbra({{ 1961 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1962 SIMD_FMT_PH, SIGNED, MODE_RA); 1963 }}); 1964 } 1965 } 1966 0x1: decode OP_LO { 1967 format DspIntOp { 1968 0x1: absq_s_ph({{ 1969 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_PH, &dspctl); 1970 }}); 1971 0x2: repl_ph({{ 1972 Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | 1973 (sext<10>(RS_RT))<15:0>; 1974 }}); 1975 0x3: replv_ph({{ 1976 Rd.uw = Rt.uw<15:0> << 16 | 1977 Rt.uw<15:0>; 1978 }}); 1979 0x4: preceq_w_phl({{ 1980 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, 1981 SIMD_FMT_W, SIGNED, MODE_L); 1982 }}); 1983 0x5: preceq_w_phr({{ 1984 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, 1985 SIMD_FMT_W, SIGNED, MODE_R); 1986 }}); 1987 } 1988 } 1989 0x2: decode OP_LO { 1990 format DspIntOp { 1991 0x1: absq_s_w({{ 1992 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_W, &dspctl); 1993 }}); 1994 } 1995 } 1996 0x3: decode OP_LO { 1997 0x3: IntOp::bitrev({{ 1998 Rd.uw = bitrev( Rt.uw<15:0> ); 1999 }}); 2000 format DspIntOp { 2001 0x4: preceu_ph_qbl({{ 2002 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2003 UNSIGNED, SIMD_FMT_PH, 2004 UNSIGNED, MODE_L); 2005 }}); 2006 0x5: preceu_ph_qbr({{ 2007 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2008 UNSIGNED, SIMD_FMT_PH, 2009 UNSIGNED, MODE_R ); 2010 }}); 2011 0x6: preceu_ph_qbla({{ 2012 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2013 UNSIGNED, SIMD_FMT_PH, 2014 UNSIGNED, MODE_LA ); 2015 }}); 2016 0x7: preceu_ph_qbra({{ 2017 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2018 UNSIGNED, SIMD_FMT_PH, 2019 UNSIGNED, MODE_RA); 2020 }}); 2021 } 2022 } 2023 } 2024 2025 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 2026 //(DSP ASE MANUAL) 2027 0x3: decode OP_HI { 2028 0x0: decode OP_LO { 2029 format DspIntOp { 2030 0x0: shll_qb({{ 2031 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_QB, 2032 NOSATURATE, UNSIGNED, &dspctl); 2033 }}); 2034 0x1: shrl_qb({{ 2035 Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_QB, 2036 UNSIGNED); 2037 }}); 2038 0x2: shllv_qb({{ 2039 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_QB, 2040 NOSATURATE, UNSIGNED, &dspctl); 2041 }}); 2042 0x3: shrlv_qb({{ 2043 Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_QB, 2044 UNSIGNED); 2045 }}); 2046 0x4: shra_qb({{ 2047 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, 2048 NOROUND, SIGNED, &dspctl); 2049 }}); 2050 0x5: shra_r_qb({{ 2051 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, 2052 ROUND, SIGNED, &dspctl); 2053 }}); 2054 0x6: shrav_qb({{ 2055 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, 2056 NOROUND, SIGNED, &dspctl); 2057 }}); 2058 0x7: shrav_r_qb({{ 2059 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, 2060 ROUND, SIGNED, &dspctl); 2061 }}); 2062 } 2063 } 2064 0x1: decode OP_LO { 2065 format DspIntOp { 2066 0x0: shll_ph({{ 2067 Rd.uw = dspShll(Rt.uw, RS, SIMD_FMT_PH, 2068 NOSATURATE, SIGNED, &dspctl); 2069 }}); 2070 0x1: shra_ph({{ 2071 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, 2072 NOROUND, SIGNED, &dspctl); 2073 }}); 2074 0x2: shllv_ph({{ 2075 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, 2076 NOSATURATE, SIGNED, &dspctl); 2077 }}); 2078 0x3: shrav_ph({{ 2079 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, 2080 NOROUND, SIGNED, &dspctl); 2081 }}); 2082 0x4: shll_s_ph({{ 2083 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_PH, 2084 SATURATE, SIGNED, &dspctl); 2085 }}); 2086 0x5: shra_r_ph({{ 2087 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, 2088 ROUND, SIGNED, &dspctl); 2089 }}); 2090 0x6: shllv_s_ph({{ 2091 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, 2092 SATURATE, SIGNED, &dspctl); 2093 }}); 2094 0x7: shrav_r_ph({{ 2095 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, 2096 ROUND, SIGNED, &dspctl); 2097 }}); 2098 } 2099 } 2100 0x2: decode OP_LO { 2101 format DspIntOp { 2102 0x4: shll_s_w({{ 2103 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_W, 2104 SATURATE, SIGNED, &dspctl); 2105 }}); 2106 0x5: shra_r_w({{ 2107 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_W, 2108 ROUND, SIGNED, &dspctl); 2109 }}); 2110 0x6: shllv_s_w({{ 2111 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_W, 2112 SATURATE, SIGNED, &dspctl); 2113 }}); 2114 0x7: shrav_r_w({{ 2115 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_W, 2116 ROUND, SIGNED, &dspctl); 2117 }}); 2118 } 2119 } 2120 0x3: decode OP_LO { 2121 format DspIntOp { 2122 0x1: shrl_ph({{ 2123 Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_PH, 2124 UNSIGNED); 2125 }}); 2126 0x3: shrlv_ph({{ 2127 Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_PH, 2128 UNSIGNED); 2129 }}); 2130 } 2131 } 2132 } 2133 } 2134 2135 0x3: decode FUNCTION_LO { 2136 2137 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2138 //(DSP ASE Rev2 Manual) 2139 0x0: decode OP_HI { 2140 0x0: decode OP_LO { 2141 format DspIntOp { 2142 0x0: adduh_qb({{ 2143 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2144 NOROUND, UNSIGNED); 2145 }}); 2146 0x1: subuh_qb({{ 2147 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2148 NOROUND, UNSIGNED); 2149 }}); 2150 0x2: adduh_r_qb({{ 2151 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2152 ROUND, UNSIGNED); 2153 }}); 2154 0x3: subuh_r_qb({{ 2155 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2156 ROUND, UNSIGNED); 2157 }}); 2158 } 2159 } 2160 0x1: decode OP_LO { 2161 format DspIntOp { 2162 0x0: addqh_ph({{ 2163 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2164 NOROUND, SIGNED); 2165 }}); 2166 0x1: subqh_ph({{ 2167 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2168 NOROUND, SIGNED); 2169 }}); 2170 0x2: addqh_r_ph({{ 2171 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2172 ROUND, SIGNED); 2173 }}); 2174 0x3: subqh_r_ph({{ 2175 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2176 ROUND, SIGNED); 2177 }}); 2178 0x4: mul_ph({{ 2179 Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, 2180 NOSATURATE, &dspctl); 2181 }}, IntMultOp); 2182 0x6: mul_s_ph({{ 2183 Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, 2184 SATURATE, &dspctl); 2185 }}, IntMultOp); 2186 } 2187 } 2188 0x2: decode OP_LO { 2189 format DspIntOp { 2190 0x0: addqh_w({{ 2191 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, 2192 NOROUND, SIGNED); 2193 }}); 2194 0x1: subqh_w({{ 2195 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, 2196 NOROUND, SIGNED); 2197 }}); 2198 0x2: addqh_r_w({{ 2199 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, 2200 ROUND, SIGNED); 2201 }}); 2202 0x3: subqh_r_w({{ 2203 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, 2204 ROUND, SIGNED); 2205 }}); 2206 0x6: mulq_s_w({{ 2207 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, 2208 SATURATE, NOROUND, &dspctl); 2209 }}, IntMultOp); 2210 0x7: mulq_rs_w({{ 2211 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, 2212 SATURATE, ROUND, &dspctl); 2213 }}, IntMultOp); 2214 } 2215 } 2216 } 2217 } 2218 2219 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2220 0x4: decode SA { 2221 format BasicOp { 2222 0x02: wsbh({{ 2223 Rd.uw = Rt.uw<23:16> << 24 | 2224 Rt.uw<31:24> << 16 | 2225 Rt.uw<7:0> << 8 | 2226 Rt.uw<15:8>; 2227 }}); 2228 0x10: seb({{ Rd.sw = Rt.sb; }}); 2229 0x18: seh({{ Rd.sw = Rt.sh; }}); 2230 } 2231 } 2232 2233 0x6: decode FUNCTION_LO { 2234 2235 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2236 //(DSP ASE MANUAL) 2237 0x0: decode OP_HI { 2238 0x0: decode OP_LO { 2239 format DspHiLoOp { 2240 0x0: dpa_w_ph({{ 2241 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2242 SIMD_FMT_PH, SIGNED, MODE_L); 2243 }}, IntMultOp); 2244 0x1: dps_w_ph({{ 2245 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2246 SIMD_FMT_PH, SIGNED, MODE_L); 2247 }}, IntMultOp); 2248 0x2: mulsa_w_ph({{ 2249 dspac = dspMulsa(dspac, Rs.sw, Rt.sw, 2250 ACDST, SIMD_FMT_PH ); 2251 }}, IntMultOp); 2252 0x3: dpau_h_qbl({{ 2253 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2254 SIMD_FMT_QB, UNSIGNED, MODE_L); 2255 }}, IntMultOp); 2256 0x4: dpaq_s_w_ph({{ 2257 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2258 ACDST, SIMD_FMT_PH, 2259 SIMD_FMT_W, NOSATURATE, 2260 MODE_L, &dspctl); 2261 }}, IntMultOp); 2262 0x5: dpsq_s_w_ph({{ 2263 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2264 ACDST, SIMD_FMT_PH, 2265 SIMD_FMT_W, NOSATURATE, 2266 MODE_L, &dspctl); 2267 }}, IntMultOp); 2268 0x6: mulsaq_s_w_ph({{ 2269 dspac = dspMulsaq(dspac, Rs.sw, Rt.sw, 2270 ACDST, SIMD_FMT_PH, 2271 &dspctl); 2272 }}, IntMultOp); 2273 0x7: dpau_h_qbr({{ 2274 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2275 SIMD_FMT_QB, UNSIGNED, MODE_R); 2276 }}, IntMultOp); 2277 } 2278 } 2279 0x1: decode OP_LO { 2280 format DspHiLoOp { 2281 0x0: dpax_w_ph({{ 2282 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2283 SIMD_FMT_PH, SIGNED, MODE_X); 2284 }}, IntMultOp); 2285 0x1: dpsx_w_ph({{ 2286 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2287 SIMD_FMT_PH, SIGNED, MODE_X); 2288 }}, IntMultOp); 2289 0x3: dpsu_h_qbl({{ 2290 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2291 SIMD_FMT_QB, UNSIGNED, MODE_L); 2292 }}, IntMultOp); 2293 0x4: dpaq_sa_l_w({{ 2294 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2295 ACDST, SIMD_FMT_W, 2296 SIMD_FMT_L, SATURATE, 2297 MODE_L, &dspctl); 2298 }}, IntMultOp); 2299 0x5: dpsq_sa_l_w({{ 2300 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2301 ACDST, SIMD_FMT_W, 2302 SIMD_FMT_L, SATURATE, 2303 MODE_L, &dspctl); 2304 }}, IntMultOp); 2305 0x7: dpsu_h_qbr({{ 2306 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2307 SIMD_FMT_QB, UNSIGNED, MODE_R); 2308 }}, IntMultOp); 2309 } 2310 } 2311 0x2: decode OP_LO { 2312 format DspHiLoOp { 2313 0x0: maq_sa_w_phl({{ 2314 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2315 ACDST, SIMD_FMT_PH, 2316 MODE_L, SATURATE, &dspctl); 2317 }}, IntMultOp); 2318 0x2: maq_sa_w_phr({{ 2319 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2320 ACDST, SIMD_FMT_PH, 2321 MODE_R, SATURATE, &dspctl); 2322 }}, IntMultOp); 2323 0x4: maq_s_w_phl({{ 2324 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2325 ACDST, SIMD_FMT_PH, 2326 MODE_L, NOSATURATE, &dspctl); 2327 }}, IntMultOp); 2328 0x6: maq_s_w_phr({{ 2329 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2330 ACDST, SIMD_FMT_PH, 2331 MODE_R, NOSATURATE, &dspctl); 2332 }}, IntMultOp); 2333 } 2334 } 2335 0x3: decode OP_LO { 2336 format DspHiLoOp { 2337 0x0: dpaqx_s_w_ph({{ 2338 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2339 ACDST, SIMD_FMT_PH, 2340 SIMD_FMT_W, NOSATURATE, 2341 MODE_X, &dspctl); 2342 }}, IntMultOp); 2343 0x1: dpsqx_s_w_ph({{ 2344 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2345 ACDST, SIMD_FMT_PH, 2346 SIMD_FMT_W, NOSATURATE, 2347 MODE_X, &dspctl); 2348 }}, IntMultOp); 2349 0x2: dpaqx_sa_w_ph({{ 2350 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2351 ACDST, SIMD_FMT_PH, 2352 SIMD_FMT_W, SATURATE, 2353 MODE_X, &dspctl); 2354 }}, IntMultOp); 2355 0x3: dpsqx_sa_w_ph({{ 2356 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2357 ACDST, SIMD_FMT_PH, 2358 SIMD_FMT_W, SATURATE, 2359 MODE_X, &dspctl); 2360 }}, IntMultOp); 2361 } 2362 } 2363 } 2364 2365 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2366 0x1: decode OP_HI { 2367 0x0: decode OP_LO { 2368 format IntOp { 2369 0x0: append({{ 2370 Rt.uw = (Rt.uw << RD) | bits(Rs.uw, RD - 1, 0); 2371 }}); 2372 0x1: prepend({{ 2373 Rt.uw = (Rt.uw >> RD) | 2374 (bits(Rs.uw, RD - 1, 0) << (32 - RD)); 2375 }}); 2376 } 2377 } 2378 0x2: decode OP_LO { 2379 format IntOp { 2380 0x0: balign({{ 2381 Rt.uw = (Rt.uw << (8 * BP)) | 2382 (Rs.uw >> (8 * (4 - BP))); 2383 }}); 2384 } 2385 } 2386 } 2387 2388 } 2389 0x7: decode FUNCTION_LO { 2390 2391 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2392 //(DSP ASE MANUAL) 2393 0x0: decode OP_HI { 2394 0x0: decode OP_LO { 2395 format DspHiLoOp { 2396 0x0: extr_w({{ 2397 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2398 NOROUND, NOSATURATE, &dspctl); 2399 }}); 2400 0x1: extrv_w({{ 2401 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2402 NOROUND, NOSATURATE, &dspctl); 2403 }}); 2404 0x2: extp({{ 2405 Rt.uw = dspExtp(dspac, RS, &dspctl); 2406 }}); 2407 0x3: extpv({{ 2408 Rt.uw = dspExtp(dspac, Rs.uw, &dspctl); 2409 }}); 2410 0x4: extr_r_w({{ 2411 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2412 ROUND, NOSATURATE, &dspctl); 2413 }}); 2414 0x5: extrv_r_w({{ 2415 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2416 ROUND, NOSATURATE, &dspctl); 2417 }}); 2418 0x6: extr_rs_w({{ 2419 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2420 ROUND, SATURATE, &dspctl); 2421 }}); 2422 0x7: extrv_rs_w({{ 2423 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2424 ROUND, SATURATE, &dspctl); 2425 }}); 2426 } 2427 } 2428 0x1: decode OP_LO { 2429 format DspHiLoOp { 2430 0x2: extpdp({{ 2431 Rt.uw = dspExtpd(dspac, RS, &dspctl); 2432 }}); 2433 0x3: extpdpv({{ 2434 Rt.uw = dspExtpd(dspac, Rs.uw, &dspctl); 2435 }}); 2436 0x6: extr_s_h({{ 2437 Rt.uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2438 NOROUND, SATURATE, &dspctl); 2439 }}); 2440 0x7: extrv_s_h({{ 2441 Rt.uw = dspExtr(dspac, SIMD_FMT_PH, Rs.uw, 2442 NOROUND, SATURATE, &dspctl); 2443 }}); 2444 } 2445 } 2446 0x2: decode OP_LO { 2447 format DspIntOp { 2448 0x2: rddsp({{ 2449 Rd.uw = readDSPControl(&dspctl, RDDSPMASK); 2450 }}); 2451 0x3: wrdsp({{ 2452 writeDSPControl(&dspctl, Rs.uw, WRDSPMASK); 2453 }}); 2454 } 2455 } 2456 0x3: decode OP_LO { 2457 format DspHiLoOp { 2458 0x2: shilo({{ 2459 if (sext<6>(HILOSA) < 0) { 2460 dspac = (uint64_t)dspac << 2461 -sext<6>(HILOSA); 2462 } else { 2463 dspac = (uint64_t)dspac >> 2464 sext<6>(HILOSA); 2465 } 2466 }}); 2467 0x3: shilov({{ 2468 if (sext<6>(Rs.sw<5:0>) < 0) { 2469 dspac = (uint64_t)dspac << 2470 -sext<6>(Rs.sw<5:0>); 2471 } else { 2472 dspac = (uint64_t)dspac >> 2473 sext<6>(Rs.sw<5:0>); 2474 } 2475 }}); 2476 0x7: mthlip({{ 2477 dspac = dspac << 32; 2478 dspac |= Rs.uw; 2479 dspctl = insertBits(dspctl, 5, 0, 2480 dspctl<5:0> + 32); 2481 }}); 2482 } 2483 } 2484 } 2485 0x3: decode OP { 2486#if FULL_SYSTEM 2487 0x0: FailUnimpl::rdhwr(); 2488#else 2489 0x0: decode RD { 2490 29: BasicOp::rdhwr({{ Rt = TpValue; }}); 2491 } 2492#endif 2493 } 2494 } 2495 } 2496 } 2497 2498 0x4: decode OPCODE_LO { 2499 format LoadMemory { 2500 0x0: lb({{ Rt.sw = Mem.sb; }}); 2501 0x1: lh({{ Rt.sw = Mem.sh; }}); 2502 0x3: lw({{ Rt.sw = Mem.sw; }}); 2503 0x4: lbu({{ Rt.uw = Mem.ub;}}); 2504 0x5: lhu({{ Rt.uw = Mem.uh; }}); 2505 } 2506 2507 format LoadUnalignedMemory { 2508 0x2: lwl({{ 2509 uint32_t mem_shift = 24 - (8 * byte_offset); 2510 Rt.uw = mem_word << mem_shift | (Rt.uw & mask(mem_shift)); 2511 }}); 2512 0x6: lwr({{ 2513 uint32_t mem_shift = 8 * byte_offset; 2514 Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) | 2515 (mem_word >> mem_shift); 2516 }}); 2517 } 2518 } 2519 2520 0x5: decode OPCODE_LO { 2521 format StoreMemory { 2522 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 2523 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 2524 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 2525 } 2526 2527 format StoreUnalignedMemory { 2528 0x2: swl({{ 2529 uint32_t reg_shift = 24 - (8 * byte_offset); 2530 uint32_t mem_shift = 32 - reg_shift; 2531 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2532 (Rt.uw >> reg_shift); 2533 }}); 2534 0x6: swr({{ 2535 uint32_t reg_shift = 8 * byte_offset; 2536 mem_word = Rt.uw << reg_shift | 2537 (mem_word & (mask(reg_shift))); 2538 }}); 2539 } 2540 format CP0Control { 2541 0x7: cache({{ 2542 //Addr CacheEA = Rs.uw + OFFSET; 2543 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2544 }}); 2545 } 2546 } 2547 2548 0x6: decode OPCODE_LO { 2549 format LoadMemory { 2550 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LLSC); 2551 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 2552 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 2553 } 2554 0x2: CP2Unimpl::lwc2(); 2555 0x6: CP2Unimpl::ldc2(); 2556 0x3: Prefetch::pref(); 2557 } 2558 2559 2560 0x7: decode OPCODE_LO { 2561 0x0: StoreCond::sc({{ Mem.uw = Rt.uw; }}, 2562 {{ uint64_t tmp = write_result; 2563 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; 2564 }}, mem_flags=LLSC, 2565 inst_flags = IsStoreConditional); 2566 format StoreMemory { 2567 0x1: swc1({{ Mem.uw = Ft.uw; }}); 2568 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 2569 } 2570 0x2: CP2Unimpl::swc2(); 2571 0x6: CP2Unimpl::sdc2(); 2572 } 2573} 2574 2575 2576