decoder.isa revision 7720:65d338a8dba4
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30// Brett Miller 31// Jaidev Patwardhan 32 33//////////////////////////////////////////////////////////////////// 34// 35// The actual MIPS32 ISA decoder 36// ----------------------------- 37// The following instructions are specified in the MIPS32 ISA 38// Specification. Decoding closely follows the style specified 39// in the MIPS32 ISA specification document starting with Table 40// A-2 (document available @ http://www.mips.com) 41// 42decode OPCODE_HI default Unknown::unknown() { 43 //Table A-2 44 0x0: decode OPCODE_LO { 45 0x0: decode FUNCTION_HI { 46 0x0: decode FUNCTION_LO { 47 0x1: decode MOVCI { 48 format BasicOp { 49 0: movf({{ 50 Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; 51 }}); 52 1: movt({{ 53 Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; 54 }}); 55 } 56 } 57 58 format BasicOp { 59 //Table A-3 Note: "Specific encodings of the rd, rs, and 60 //rt fields are used to distinguish SLL, SSNOP, and EHB 61 //functions 62 0x0: decode RS { 63 0x0: decode RT_RD { 64 0x0: decode SA default Nop::nop() { 65 0x1: ssnop({{;}}); 66 0x3: ehb({{;}}); 67 } 68 default: sll({{ Rd = Rt.uw << SA; }}); 69 } 70 } 71 72 0x2: decode RS_SRL { 73 0x0:decode SRL { 74 0: srl({{ Rd = Rt.uw >> SA; }}); 75 76 //Hardcoded assuming 32-bit ISA, 77 //probably need parameter here 78 1: rotr({{ 79 Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA); 80 }}); 81 } 82 } 83 84 0x3: decode RS { 85 0x0: sra({{ 86 uint32_t temp = Rt >> SA; 87 if ( (Rt & 0x80000000) > 0 ) { 88 uint32_t mask = 0x80000000; 89 for(int i=0; i < SA; i++) { 90 temp |= mask; 91 mask = mask >> 1; 92 } 93 } 94 Rd = temp; 95 }}); 96 } 97 98 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 99 100 0x6: decode SRLV { 101 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 102 103 //Hardcoded assuming 32-bit ISA, 104 //probably need parameter here 105 1: rotrv({{ 106 Rd = (Rt.uw << (32 - Rs<4:0>)) | 107 (Rt.uw >> Rs<4:0>); 108 }}); 109 } 110 111 0x7: srav({{ 112 int shift_amt = Rs<4:0>; 113 114 uint32_t temp = Rt >> shift_amt; 115 116 if ((Rt & 0x80000000) > 0) { 117 uint32_t mask = 0x80000000; 118 for (int i = 0; i < shift_amt; i++) { 119 temp |= mask; 120 mask = mask >> 1; 121 } 122 } 123 Rd = temp; 124 }}); 125 } 126 } 127 128 0x1: decode FUNCTION_LO { 129 //Table A-3 Note: "Specific encodings of the hint field are 130 //used to distinguish JR from JR.HB and JALR from JALR.HB" 131 format Jump { 132 0x0: decode HINT { 133 0x1: jr_hb({{ 134 Config1Reg config1 = Config1; 135 if (config1.ca == 0) { 136 pc.nnpc(Rs); 137 } else { 138 panic("MIPS16e not supported\n"); 139 } 140 PCS = pc; 141 }}, IsReturn, ClearHazards); 142 default: jr({{ 143 Config1Reg config1 = Config1; 144 if (config1.ca == 0) { 145 pc.nnpc(Rs); 146 } else { 147 panic("MIPS16e not supported\n"); 148 } 149 PCS = pc; 150 }}, IsReturn); 151 } 152 153 0x1: decode HINT { 154 0x1: jalr_hb({{ 155 Rd = pc.nnpc(); 156 pc.nnpc(Rs); 157 PCS = pc; 158 }}, IsCall, ClearHazards); 159 default: jalr({{ 160 Rd = pc.nnpc(); 161 pc.nnpc(Rs); 162 PCS = pc; 163 }}, IsCall); 164 } 165 } 166 167 format BasicOp { 168 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 169 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 170#if FULL_SYSTEM 171 0x4: syscall({{ fault = new SystemCallFault(); }}); 172#else 173 0x4: syscall({{ xc->syscall(R2); }}, 174 IsSerializeAfter, IsNonSpeculative); 175#endif 176 0x7: sync({{ ; }}, IsMemBarrier); 177 0x5: break({{fault = new BreakpointFault();}}); 178 } 179 180 } 181 182 0x2: decode FUNCTION_LO { 183 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, 184 IntMultOp, IsIprAccess); 185 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); 186 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, 187 IntMultOp, IsIprAccess); 188 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 189 } 190 191 0x3: decode FUNCTION_LO { 192 format HiLoRdSelValOp { 193 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp); 194 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp); 195 } 196 197 format HiLoOp { 198 0x2: div({{ 199 if (Rt.sd != 0) { 200 HI0 = Rs.sd % Rt.sd; 201 LO0 = Rs.sd / Rt.sd; 202 } 203 }}, IntDivOp); 204 205 0x3: divu({{ 206 if (Rt.ud != 0) { 207 HI0 = Rs.ud % Rt.ud; 208 LO0 = Rs.ud / Rt.ud; 209 } 210 }}, IntDivOp); 211 } 212 } 213 214 0x4: decode HINT { 215 0x0: decode FUNCTION_LO { 216 format IntOp { 217 0x0: add({{ 218 /* More complicated since an ADD can cause 219 an arithmetic overflow exception */ 220 int64_t Src1 = Rs.sw; 221 int64_t Src2 = Rt.sw; 222 int64_t temp_result; 223#if FULL_SYSTEM 224 if (((Src1 >> 31) & 1) == 1) 225 Src1 |= 0x100000000LL; 226#endif 227 temp_result = Src1 + Src2; 228#if FULL_SYSTEM 229 if (bits(temp_result, 31) == 230 bits(temp_result, 32)) { 231#endif 232 Rd.sw = temp_result; 233#if FULL_SYSTEM 234 } else { 235 fault = new ArithmeticFault(); 236 } 237#endif 238 }}); 239 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 240 0x2: sub({{ 241 /* More complicated since an SUB can cause 242 an arithmetic overflow exception */ 243 int64_t Src1 = Rs.sw; 244 int64_t Src2 = Rt.sw; 245 int64_t temp_result = Src1 - Src2; 246#if FULL_SYSTEM 247 if (bits(temp_result, 31) == 248 bits(temp_result, 32)) { 249#endif 250 Rd.sw = temp_result; 251#if FULL_SYSTEM 252 } else { 253 fault = new ArithmeticFault(); 254 } 255#endif 256 }}); 257 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw; }}); 258 0x4: and({{ Rd = Rs & Rt; }}); 259 0x5: or({{ Rd = Rs | Rt; }}); 260 0x6: xor({{ Rd = Rs ^ Rt; }}); 261 0x7: nor({{ Rd = ~(Rs | Rt); }}); 262 } 263 } 264 } 265 266 0x5: decode HINT { 267 0x0: decode FUNCTION_LO { 268 format IntOp{ 269 0x2: slt({{ Rd.sw = (Rs.sw < Rt.sw) ? 1 : 0 }}); 270 0x3: sltu({{ Rd.uw = (Rs.uw < Rt.uw) ? 1 : 0 }}); 271 } 272 } 273 } 274 275 0x6: decode FUNCTION_LO { 276 format Trap { 277 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 278 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 279 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 280 0x3: tltu({{ cond = (Rs.uw < Rt.uw); }}); 281 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 282 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 283 } 284 } 285 } 286 287 0x1: decode REGIMM_HI { 288 0x0: decode REGIMM_LO { 289 format Branch { 290 0x0: bltz({{ cond = (Rs.sw < 0); }}); 291 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 292 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely); 293 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely); 294 } 295 } 296 297 0x1: decode REGIMM_LO { 298 format TrapImm { 299 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }}); 300 0x1: tgeiu({{ 301 cond = (Rs.uw >= (uint32_t)(int32_t)(int16_t)INTIMM); 302 }}); 303 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }}); 304 0x3: tltiu({{ 305 cond = (Rs.uw < (uint32_t)(int32_t)(int16_t)INTIMM); 306 }}); 307 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM); }}); 308 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM); }}); 309 } 310 } 311 312 0x2: decode REGIMM_LO { 313 format Branch { 314 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link); 315 0x1: decode RS { 316 0x0: bal ({{ cond = 1; }}, IsCall, Link); 317 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link); 318 } 319 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely); 320 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely); 321 } 322 } 323 324 0x3: decode REGIMM_LO { 325 // from Table 5-4 MIPS32 REGIMM Encoding of rt Field 326 // (DSP ASE MANUAL) 327 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 328 format WarnUnimpl { 329 0x7: synci(); 330 } 331 } 332 } 333 334 format Jump { 335 0x2: j({{ 336 pc.nnpc((pc.npc() & 0xF0000000) | (JMPTARG << 2)); 337 PCS = pc; 338 }}); 339 0x3: jal({{ 340 pc.nnpc((pc.npc() & 0xF0000000) | (JMPTARG << 2)); 341 PCS = pc; 342 }}, IsCall, Link); 343 } 344 345 format Branch { 346 0x4: decode RS_RT { 347 0x0: b({{ cond = 1; }}); 348 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 349 } 350 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 351 0x6: blez({{ cond = (Rs.sw <= 0); }}); 352 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 353 } 354 } 355 356 0x1: decode OPCODE_LO { 357 format IntImmOp { 358 0x0: addi({{ 359 int64_t Src1 = Rs.sw; 360 int64_t Src2 = imm; 361 int64_t temp_result; 362#if FULL_SYSTEM 363 if (((Src1 >> 31) & 1) == 1) 364 Src1 |= 0x100000000LL; 365#endif 366 temp_result = Src1 + Src2; 367#if FULL_SYSTEM 368 if (bits(temp_result, 31) == bits(temp_result, 32)) { 369#endif 370 Rt.sw = temp_result; 371#if FULL_SYSTEM 372 } else { 373 fault = new ArithmeticFault(); 374 } 375#endif 376 }}); 377 0x1: addiu({{ Rt.sw = Rs.sw + imm; }}); 378 0x2: slti({{ Rt.sw = (Rs.sw < imm) ? 1 : 0 }}); 379 380 //Edited to include MIPS AVP Pass/Fail instructions and 381 //default to the sltiu instruction 382 0x3: decode RS_RT_INTIMM { 383 0xabc1: BasicOp::fail({{ 384 exitSimLoop("AVP/SRVP Test Failed"); 385 }}); 386 0xabc2: BasicOp::pass({{ 387 exitSimLoop("AVP/SRVP Test Passed"); 388 }}); 389 default: sltiu({{ 390 Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0; 391 }}); 392 } 393 394 0x4: andi({{ Rt.sw = Rs.sw & zextImm; }}); 395 0x5: ori({{ Rt.sw = Rs.sw | zextImm; }}); 396 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm; }}); 397 398 0x7: decode RS { 399 0x0: lui({{ Rt = imm << 16; }}); 400 } 401 } 402 } 403 404 0x2: decode OPCODE_LO { 405 //Table A-11 MIPS32 COP0 Encoding of rs Field 406 0x0: decode RS_MSB { 407 0x0: decode RS { 408 format CP0Control { 409 0x0: mfc0({{ 410 Config3Reg config3 = Config3; 411 PageGrainReg pageGrain = PageGrain; 412 Rt = CP0_RD_SEL; 413 /* Hack for PageMask */ 414 if (RD == 5) { 415 // PageMask 416 if (config3.sp == 0 || pageGrain.esp == 0) 417 Rt &= 0xFFFFE7FF; 418 } 419 }}); 420 0x4: mtc0({{ 421 CP0_RD_SEL = Rt; 422 CauseReg cause = Cause; 423 IntCtlReg intCtl = IntCtl; 424 if (RD == 11) { 425 // Compare 426 if (cause.ti == 1) { 427 cause.ti = 0; 428 int offset = 10; // corresponding to cause.ip0 429 offset += intCtl.ipti - 2; 430 replaceBits(cause, offset, offset, 0); 431 } 432 } 433 Cause = cause; 434 }}); 435 } 436 format CP0Unimpl { 437 0x1: dmfc0(); 438 0x5: dmtc0(); 439 default: unknown(); 440 } 441 format MT_MFTR { 442 // Decode MIPS MT MFTR instruction into sub-instructions 443 0x8: decode MT_U { 444 0x0: mftc0({{ 445 data = xc->readRegOtherThread((RT << 3 | SEL) + 446 Ctrl_Base_DepTag); 447 }}); 448 0x1: decode SEL { 449 0x0: mftgpr({{ 450 data = xc->readRegOtherThread(RT); 451 }}); 452 0x1: decode RT { 453 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }}); 454 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }}); 455 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }}); 456 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }}); 457 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }}); 458 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }}); 459 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }}); 460 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }}); 461 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }}); 462 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }}); 463 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }}); 464 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }}); 465 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }}); 466 default: CP0Unimpl::unknown(); 467 } 468 0x2: decode MT_H { 469 0x0: mftc1({{ data = xc->readRegOtherThread(RT + 470 FP_Base_DepTag); 471 }}); 472 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + 473 FP_Base_DepTag); 474 }}); 475 } 476 0x3: cftc1({{ 477 uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR + 478 FP_Base_DepTag); 479 switch (RT) { 480 case 0: 481 data = xc->readRegOtherThread(FLOATREG_FIR + 482 Ctrl_Base_DepTag); 483 break; 484 case 25: 485 data = (fcsr_val & 0xFE000000 >> 24) | 486 (fcsr_val & 0x00800000 >> 23); 487 break; 488 case 26: 489 data = fcsr_val & 0x0003F07C; 490 break; 491 case 28: 492 data = (fcsr_val & 0x00000F80) | 493 (fcsr_val & 0x01000000 >> 21) | 494 (fcsr_val & 0x00000003); 495 break; 496 case 31: 497 data = fcsr_val; 498 break; 499 default: 500 fatal("FP Control Value (%d) Not Valid"); 501 } 502 }}); 503 default: CP0Unimpl::unknown(); 504 } 505 } 506 } 507 508 format MT_MTTR { 509 // Decode MIPS MT MTTR instruction into sub-instructions 510 0xC: decode MT_U { 511 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, 512 Rt); 513 }}); 514 0x1: decode SEL { 515 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 516 0x1: decode RT { 517 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt); 518 }}); 519 0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0, 520 Rt); 521 }}); 522 0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0, 523 Rt); 524 }}); 525 0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1, 526 Rt); 527 }}); 528 0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1, 529 Rt); 530 }}); 531 0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1, 532 Rt); 533 }}); 534 0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2, 535 Rt); 536 }}); 537 0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2, 538 Rt); 539 }}); 540 0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2, 541 Rt); 542 }}); 543 0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3, 544 Rt); 545 }}); 546 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3, 547 Rt); 548 }}); 549 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt); 550 }}); 551 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }}); 552 default: CP0Unimpl::unknown(); 553 554 } 555 0x2: mttc1({{ 556 uint64_t data = xc->readRegOtherThread(RD + 557 FP_Base_DepTag); 558 data = insertBits(data, top_bit, 559 bottom_bit, Rt); 560 xc->setRegOtherThread(RD + FP_Base_DepTag, 561 data); 562 }}); 563 0x3: cttc1({{ 564 uint32_t data; 565 switch (RD) { 566 case 25: 567 data = (Rt.uw<7:1> << 25) | // move 31-25 568 (FCSR & 0x01000000) | // bit 24 569 (FCSR & 0x004FFFFF); // bit 22-0 570 break; 571 case 26: 572 data = (FCSR & 0xFFFC0000) | // move 31-18 573 Rt.uw<17:12> << 12 | // bit 17-12 574 (FCSR & 0x00000F80) << 7 | // bit 11-7 575 Rt.uw<6:2> << 2 | // bit 6-2 576 (FCSR & 0x00000002); // bit 1...0 577 break; 578 case 28: 579 data = (FCSR & 0xFE000000) | // move 31-25 580 Rt.uw<2:2> << 24 | // bit 24 581 (FCSR & 0x00FFF000) << 23 | // bit 23-12 582 Rt.uw<11:7> << 7 | // bit 24 583 (FCSR & 0x000007E) | 584 Rt.uw<1:0>; // bit 22-0 585 break; 586 case 31: 587 data = Rt.uw; 588 break; 589 default: 590 panic("FP Control Value (%d) " 591 "Not Available. Ignoring " 592 "Access to Floating Control " 593 "Status Register", FS); 594 } 595 xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); 596 }}); 597 default: CP0Unimpl::unknown(); 598 } 599 } 600 } 601 0xB: decode RD { 602 format MT_Control { 603 0x0: decode POS { 604 0x0: decode SEL { 605 0x1: decode SC { 606 0x0: dvpe({{ 607 MVPControlReg mvpControl = MVPControl; 608 VPEConf0Reg vpeConf0 = VPEConf0; 609 Rt = MVPControl; 610 if (vpeConf0.mvp == 1) 611 mvpControl.evp = 0; 612 MVPControl = mvpControl; 613 }}); 614 0x1: evpe({{ 615 MVPControlReg mvpControl = MVPControl; 616 VPEConf0Reg vpeConf0 = VPEConf0; 617 Rt = MVPControl; 618 if (vpeConf0.mvp == 1) 619 mvpControl.evp = 1; 620 MVPControl = mvpControl; 621 }}); 622 default:CP0Unimpl::unknown(); 623 } 624 default:CP0Unimpl::unknown(); 625 } 626 default:CP0Unimpl::unknown(); 627 } 628 0x1: decode POS { 629 0xF: decode SEL { 630 0x1: decode SC { 631 0x0: dmt({{ 632 VPEControlReg vpeControl = VPEControl; 633 Rt = vpeControl; 634 vpeControl.te = 0; 635 VPEControl = vpeControl; 636 }}); 637 0x1: emt({{ 638 VPEControlReg vpeControl = VPEControl; 639 Rt = vpeControl; 640 vpeControl.te = 1; 641 VPEControl = vpeControl; 642 }}); 643 default:CP0Unimpl::unknown(); 644 } 645 default:CP0Unimpl::unknown(); 646 } 647 default:CP0Unimpl::unknown(); 648 } 649 } 650 0xC: decode POS { 651 0x0: decode SC { 652 0x0: CP0Control::di({{ 653 StatusReg status = Status; 654 ConfigReg config = Config; 655 // Rev 2.0 or beyond? 656 if (config.ar >= 1) { 657 Rt = status; 658 status.ie = 0; 659 } else { 660 // Enable this else branch once we 661 // actually set values for Config on init 662 fault = new ReservedInstructionFault(); 663 } 664 Status = status; 665 }}); 666 0x1: CP0Control::ei({{ 667 StatusReg status = Status; 668 ConfigReg config = Config; 669 if (config.ar >= 1) { 670 Rt = status; 671 status.ie = 1; 672 } else { 673 fault = new ReservedInstructionFault(); 674 } 675 }}); 676 default:CP0Unimpl::unknown(); 677 } 678 } 679 default: CP0Unimpl::unknown(); 680 } 681 format CP0Control { 682 0xA: rdpgpr({{ 683 ConfigReg config = Config; 684 if (config.ar >= 1) { 685 // Rev 2 of the architecture 686 panic("Shadow Sets Not Fully Implemented.\n"); 687 } else { 688 fault = new ReservedInstructionFault(); 689 } 690 }}); 691 0xE: wrpgpr({{ 692 ConfigReg config = Config; 693 if (config.ar >= 1) { 694 // Rev 2 of the architecture 695 panic("Shadow Sets Not Fully Implemented.\n"); 696 } else { 697 fault = new ReservedInstructionFault(); 698 } 699 }}); 700 } 701 } 702 703 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 704 0x1: decode FUNCTION { 705 format CP0Control { 706 0x18: eret({{ 707 StatusReg status = Status; 708 ConfigReg config = Config; 709 SRSCtlReg srsCtl = SRSCtl; 710 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 711 MipsISA::PCState pc = PCS; 712 if (status.erl == 1) { 713 status.erl = 0; 714 pc.npc(ErrorEPC); 715 // Need to adjust NNPC, otherwise things break 716 pc.nnpc(ErrorEPC + sizeof(MachInst)); 717 } else { 718 pc.npc(EPC); 719 // Need to adjust NNPC, otherwise things break 720 pc.nnpc(EPC + sizeof(MachInst)); 721 status.exl = 0; 722 if (config.ar >=1 && 723 srsCtl.hss > 0 && 724 status.bev == 0) { 725 srsCtl.css = srsCtl.pss; 726 //xc->setShadowSet(srsCtl.pss); 727 } 728 } 729 PCS = pc; 730 LLFlag = 0; 731 Status = status; 732 SRSCtl = srsCtl; 733 }}, IsReturn, IsSerializing, IsERET); 734 735 0x1F: deret({{ 736 DebugReg debug = Debug; 737 MipsISA::PCState pc = PCS; 738 if (debug.dm == 1) { 739 debug.dm = 1; 740 debug.iexi = 0; 741 pc.npc(DEPC); 742 } else { 743 // Undefined; 744 } 745 PCS = pc; 746 Debug = debug; 747 }}, IsReturn, IsSerializing, IsERET); 748 } 749 format CP0TLB { 750 0x01: tlbr({{ 751 MipsISA::PTE *PTEntry = 752 xc->tcBase()->getITBPtr()-> 753 getEntry(Index & 0x7FFFFFFF); 754 if (PTEntry == NULL) { 755 fatal("Invalid PTE Entry received on " 756 "a TLBR instruction\n"); 757 } 758 /* Setup PageMask */ 759 // If 1KB pages are not enabled, a read of PageMask 760 // must return 0b00 in bits 12, 11 761 PageMask = (PTEntry->Mask << 11); 762 /* Setup EntryHi */ 763 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 764 /* Setup Entry Lo0 */ 765 EntryLo0 = ((PTEntry->PFN0 << 6) | 766 (PTEntry->C0 << 3) | 767 (PTEntry->D0 << 2) | 768 (PTEntry->V0 << 1) | 769 PTEntry->G); 770 /* Setup Entry Lo1 */ 771 EntryLo1 = ((PTEntry->PFN1 << 6) | 772 (PTEntry->C1 << 3) | 773 (PTEntry->D1 << 2) | 774 (PTEntry->V1 << 1) | 775 PTEntry->G); 776 }}); // Need to hook up to TLB 777 778 0x02: tlbwi({{ 779 //Create PTE 780 MipsISA::PTE newEntry; 781 //Write PTE 782 newEntry.Mask = (Addr)(PageMask >> 11); 783 newEntry.VPN = (Addr)(EntryHi >> 11); 784 /* PageGrain _ ESP Config3 _ SP */ 785 if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { 786 // If 1KB pages are *NOT* enabled, lowest bits of 787 // the mask are 0b11 for TLB writes 788 newEntry.Mask |= 0x3; 789 // Reset bits 0 and 1 if 1KB pages are not enabled 790 newEntry.VPN &= 0xFFFFFFFC; 791 } 792 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 793 794 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 795 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 796 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 797 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 798 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 799 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 800 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 801 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 802 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 803 /* Now, compute the AddrShiftAmount and OffsetMask - 804 TLB optimizations */ 805 /* Addr Shift Amount for 1KB or larger pages */ 806 if ((newEntry.Mask & 0xFFFF) == 3) { 807 newEntry.AddrShiftAmount = 12; 808 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 809 newEntry.AddrShiftAmount = 10; 810 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 811 newEntry.AddrShiftAmount = 14; 812 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 813 newEntry.AddrShiftAmount = 16; 814 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 815 newEntry.AddrShiftAmount = 18; 816 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 817 newEntry.AddrShiftAmount = 20; 818 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 819 newEntry.AddrShiftAmount = 22; 820 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 821 newEntry.AddrShiftAmount = 24; 822 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 823 newEntry.AddrShiftAmount = 26; 824 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 825 newEntry.AddrShiftAmount = 28; 826 } else { 827 fatal("Invalid Mask Pattern Detected!\n"); 828 } 829 newEntry.OffsetMask = 830 (1 << newEntry.AddrShiftAmount) - 1; 831 832 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 833 Config3Reg config3 = Config3; 834 PageGrainReg pageGrain = PageGrain; 835 int SP = 0; 836 if (bits(config3, config3.sp) == 1 && 837 bits(pageGrain, pageGrain.esp) == 1) { 838 SP = 1; 839 } 840 IndexReg index = Index; 841 Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 842 }}); 843 0x06: tlbwr({{ 844 //Create PTE 845 MipsISA::PTE newEntry; 846 //Write PTE 847 newEntry.Mask = (Addr)(PageMask >> 11); 848 newEntry.VPN = (Addr)(EntryHi >> 11); 849 /* PageGrain _ ESP Config3 _ SP */ 850 if (bits(PageGrain, 28) == 0 || 851 bits(Config3, 4) == 0) { 852 // If 1KB pages are *NOT* enabled, lowest bits of 853 // the mask are 0b11 for TLB writes 854 newEntry.Mask |= 0x3; 855 // Reset bits 0 and 1 if 1KB pages are not enabled 856 newEntry.VPN &= 0xFFFFFFFC; 857 } 858 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 859 860 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 861 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 862 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 863 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 864 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 865 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 866 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 867 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 868 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 869 /* Now, compute the AddrShiftAmount and OffsetMask - 870 TLB optimizations */ 871 /* Addr Shift Amount for 1KB or larger pages */ 872 if ((newEntry.Mask & 0xFFFF) == 3){ 873 newEntry.AddrShiftAmount = 12; 874 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 875 newEntry.AddrShiftAmount = 10; 876 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 877 newEntry.AddrShiftAmount = 14; 878 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 879 newEntry.AddrShiftAmount = 16; 880 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 881 newEntry.AddrShiftAmount = 18; 882 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 883 newEntry.AddrShiftAmount = 20; 884 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 885 newEntry.AddrShiftAmount = 22; 886 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 887 newEntry.AddrShiftAmount = 24; 888 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 889 newEntry.AddrShiftAmount = 26; 890 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 891 newEntry.AddrShiftAmount = 28; 892 } else { 893 fatal("Invalid Mask Pattern Detected!\n"); 894 } 895 newEntry.OffsetMask = 896 (1 << newEntry.AddrShiftAmount) - 1; 897 898 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 899 Config3Reg config3 = Config3; 900 PageGrainReg pageGrain = PageGrain; 901 int SP = 0; 902 if (bits(config3, config3.sp) == 1 && 903 bits(pageGrain, pageGrain.esp) == 1) { 904 SP = 1; 905 } 906 IndexReg index = Index; 907 Ptr->insertAt(newEntry, Random, SP); 908 }}); 909 910 0x08: tlbp({{ 911 Config3Reg config3 = Config3; 912 PageGrainReg pageGrain = PageGrain; 913 EntryHiReg entryHi = EntryHi; 914 int tlbIndex; 915 Addr vpn; 916 if (pageGrain.esp == 1 && config3.sp ==1) { 917 vpn = EntryHi >> 11; 918 } else { 919 // Mask off lower 2 bits 920 vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 921 } 922 tlbIndex = xc->tcBase()->getITBPtr()-> 923 probeEntry(vpn, entryHi.asid); 924 // Check TLB for entry matching EntryHi 925 if (tlbIndex != -1) { 926 Index = tlbIndex; 927 } else { 928 // else, set Index = 1 << 31 929 Index = (1 << 31); 930 } 931 }}); 932 } 933 format CP0Unimpl { 934 0x20: wait(); 935 } 936 default: CP0Unimpl::unknown(); 937 } 938 } 939 940 //Table A-13 MIPS32 COP1 Encoding of rs Field 941 0x1: decode RS_MSB { 942 0x0: decode RS_HI { 943 0x0: decode RS_LO { 944 format CP1Control { 945 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 946 947 0x2: cfc1({{ 948 switch (FS) { 949 case 0: 950 Rt = FIR; 951 break; 952 case 25: 953 Rt = (FCSR & 0xFE000000) >> 24 | 954 (FCSR & 0x00800000) >> 23; 955 break; 956 case 26: 957 Rt = (FCSR & 0x0003F07C); 958 break; 959 case 28: 960 Rt = (FCSR & 0x00000F80) | 961 (FCSR & 0x01000000) >> 21 | 962 (FCSR & 0x00000003); 963 break; 964 case 31: 965 Rt = FCSR; 966 break; 967 default: 968 warn("FP Control Value (%d) Not Valid"); 969 } 970 }}); 971 972 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>; }}); 973 974 0x4: mtc1({{ Fs.uw = Rt.uw; }}); 975 976 0x6: ctc1({{ 977 switch (FS) { 978 case 25: 979 FCSR = (Rt.uw<7:1> << 25) | // move 31-25 980 (FCSR & 0x01000000) | // bit 24 981 (FCSR & 0x004FFFFF); // bit 22-0 982 break; 983 case 26: 984 FCSR = (FCSR & 0xFFFC0000) | // move 31-18 985 Rt.uw<17:12> << 12 | // bit 17-12 986 (FCSR & 0x00000F80) << 7 | // bit 11-7 987 Rt.uw<6:2> << 2 | // bit 6-2 988 (FCSR & 0x00000002); // bit 1-0 989 break; 990 case 28: 991 FCSR = (FCSR & 0xFE000000) | // move 31-25 992 Rt.uw<2:2> << 24 | // bit 24 993 (FCSR & 0x00FFF000) << 23 | // bit 23-12 994 Rt.uw<11:7> << 7 | // bit 24 995 (FCSR & 0x000007E) | 996 Rt.uw<1:0>; // bit 22-0 997 break; 998 case 31: 999 FCSR = Rt.uw; 1000 break; 1001 1002 default: 1003 panic("FP Control Value (%d) " 1004 "Not Available. Ignoring Access " 1005 "to Floating Control Status " 1006 "Register", FS); 1007 } 1008 }}); 1009 1010 0x7: mthc1({{ 1011 uint64_t fs_hi = Rt.uw; 1012 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 1013 Fs.ud = (fs_hi << 32) | fs_lo; 1014 }}); 1015 1016 } 1017 format CP1Unimpl { 1018 0x1: dmfc1(); 1019 0x5: dmtc1(); 1020 } 1021 } 1022 1023 0x1: decode RS_LO { 1024 0x0: decode ND { 1025 format Branch { 1026 0x0: decode TF { 1027 0x0: bc1f({{ 1028 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1029 }}); 1030 0x1: bc1t({{ 1031 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1032 }}); 1033 } 1034 0x1: decode TF { 1035 0x0: bc1fl({{ 1036 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1037 }}, Likely); 1038 0x1: bc1tl({{ 1039 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1040 }}, Likely); 1041 } 1042 } 1043 } 1044 format CP1Unimpl { 1045 0x1: bc1any2(); 1046 0x2: bc1any4(); 1047 default: unknown(); 1048 } 1049 } 1050 } 1051 1052 0x1: decode RS_HI { 1053 0x2: decode RS_LO { 1054 //Table A-14 MIPS32 COP1 Encoding of Function Field When 1055 //rs=S (( single-precision floating point)) 1056 0x0: decode FUNCTION_HI { 1057 0x0: decode FUNCTION_LO { 1058 format FloatOp { 1059 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf; }}); 1060 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf; }}); 1061 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf; }}); 1062 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf; }}); 1063 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf); }}); 1064 0x5: abs_s({{ Fd.sf = fabs(Fs.sf); }}); 1065 0x7: neg_s({{ Fd.sf = -Fs.sf; }}); 1066 } 1067 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf; }}); 1068 } 1069 0x1: decode FUNCTION_LO { 1070 format FloatConvertOp { 1071 0x0: round_l_s({{ val = Fs.sf; }}, 1072 ToLong, Round); 1073 0x1: trunc_l_s({{ val = Fs.sf; }}, 1074 ToLong, Trunc); 1075 0x2: ceil_l_s({{ val = Fs.sf;}}, 1076 ToLong, Ceil); 1077 0x3: floor_l_s({{ val = Fs.sf; }}, 1078 ToLong, Floor); 1079 0x4: round_w_s({{ val = Fs.sf; }}, 1080 ToWord, Round); 1081 0x5: trunc_w_s({{ val = Fs.sf; }}, 1082 ToWord, Trunc); 1083 0x6: ceil_w_s({{ val = Fs.sf; }}, 1084 ToWord, Ceil); 1085 0x7: floor_w_s({{ val = Fs.sf; }}, 1086 ToWord, Floor); 1087 } 1088 } 1089 1090 0x2: decode FUNCTION_LO { 1091 0x1: decode MOVCF { 1092 format BasicOp { 1093 0x0: movf_s({{ 1094 Fd = (getCondCode(FCSR,CC) == 0) ? 1095 Fs : Fd; 1096 }}); 1097 0x1: movt_s({{ 1098 Fd = (getCondCode(FCSR,CC) == 1) ? 1099 Fs : Fd; 1100 }}); 1101 } 1102 } 1103 1104 format BasicOp { 1105 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1106 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1107 } 1108 1109 format FloatOp { 1110 0x5: recip_s({{ Fd = 1 / Fs; }}); 1111 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 1112 } 1113 format CP1Unimpl { 1114 default: unknown(); 1115 } 1116 } 1117 0x3: CP1Unimpl::unknown(); 1118 1119 0x4: decode FUNCTION_LO { 1120 format FloatConvertOp { 1121 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 1122 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 1123 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 1124 } 1125 1126 0x6: FloatOp::cvt_ps_s({{ 1127 Fd.ud = (uint64_t) Fs.uw << 32 | 1128 (uint64_t) Ft.uw; 1129 }}); 1130 format CP1Unimpl { 1131 default: unknown(); 1132 } 1133 } 1134 0x5: CP1Unimpl::unknown(); 1135 1136 0x6: decode FUNCTION_LO { 1137 format FloatCompareOp { 1138 0x0: c_f_s({{ cond = 0; }}, 1139 SinglePrecision, UnorderedFalse); 1140 0x1: c_un_s({{ cond = 0; }}, 1141 SinglePrecision, UnorderedTrue); 1142 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 1143 UnorderedFalse); 1144 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 1145 UnorderedTrue); 1146 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 1147 UnorderedFalse); 1148 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 1149 UnorderedTrue); 1150 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }}, 1151 UnorderedFalse); 1152 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }}, 1153 UnorderedTrue); 1154 } 1155 } 1156 1157 0x7: decode FUNCTION_LO { 1158 format FloatCompareOp { 1159 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1160 UnorderedFalse, QnanException); 1161 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1162 UnorderedTrue, QnanException); 1163 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf); }}, 1164 UnorderedFalse, QnanException); 1165 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 1166 UnorderedTrue, QnanException); 1167 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 1168 UnorderedFalse, QnanException); 1169 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 1170 UnorderedTrue, QnanException); 1171 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 1172 UnorderedFalse, QnanException); 1173 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 1174 UnorderedTrue, QnanException); 1175 } 1176 } 1177 } 1178 1179 //Table A-15 MIPS32 COP1 Encoding of Function Field When 1180 //rs=D 1181 0x1: decode FUNCTION_HI { 1182 0x0: decode FUNCTION_LO { 1183 format FloatOp { 1184 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 1185 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 1186 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 1187 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); 1188 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 1189 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 1190 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); 1191 } 1192 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); 1193 } 1194 1195 0x1: decode FUNCTION_LO { 1196 format FloatConvertOp { 1197 0x0: round_l_d({{ val = Fs.df; }}, 1198 ToLong, Round); 1199 0x1: trunc_l_d({{ val = Fs.df; }}, 1200 ToLong, Trunc); 1201 0x2: ceil_l_d({{ val = Fs.df; }}, 1202 ToLong, Ceil); 1203 0x3: floor_l_d({{ val = Fs.df; }}, 1204 ToLong, Floor); 1205 0x4: round_w_d({{ val = Fs.df; }}, 1206 ToWord, Round); 1207 0x5: trunc_w_d({{ val = Fs.df; }}, 1208 ToWord, Trunc); 1209 0x6: ceil_w_d({{ val = Fs.df; }}, 1210 ToWord, Ceil); 1211 0x7: floor_w_d({{ val = Fs.df; }}, 1212 ToWord, Floor); 1213 } 1214 } 1215 1216 0x2: decode FUNCTION_LO { 1217 0x1: decode MOVCF { 1218 format BasicOp { 1219 0x0: movf_d({{ 1220 Fd.df = (getCondCode(FCSR,CC) == 0) ? 1221 Fs.df : Fd.df; 1222 }}); 1223 0x1: movt_d({{ 1224 Fd.df = (getCondCode(FCSR,CC) == 1) ? 1225 Fs.df : Fd.df; 1226 }}); 1227 } 1228 } 1229 1230 format BasicOp { 1231 0x2: movz_d({{ 1232 Fd.df = (Rt == 0) ? Fs.df : Fd.df; 1233 }}); 1234 0x3: movn_d({{ 1235 Fd.df = (Rt != 0) ? Fs.df : Fd.df; 1236 }}); 1237 } 1238 1239 format FloatOp { 1240 0x5: recip_d({{ Fd.df = 1 / Fs.df; }}); 1241 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df); }}); 1242 } 1243 format CP1Unimpl { 1244 default: unknown(); 1245 } 1246 1247 } 1248 0x4: decode FUNCTION_LO { 1249 format FloatConvertOp { 1250 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 1251 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 1252 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 1253 } 1254 default: CP1Unimpl::unknown(); 1255 } 1256 1257 0x6: decode FUNCTION_LO { 1258 format FloatCompareOp { 1259 0x0: c_f_d({{ cond = 0; }}, 1260 DoublePrecision, UnorderedFalse); 1261 0x1: c_un_d({{ cond = 0; }}, 1262 DoublePrecision, UnorderedTrue); 1263 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 1264 UnorderedFalse); 1265 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 1266 UnorderedTrue); 1267 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 1268 UnorderedFalse); 1269 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 1270 UnorderedTrue); 1271 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }}, 1272 UnorderedFalse); 1273 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }}, 1274 UnorderedTrue); 1275 } 1276 } 1277 1278 0x7: decode FUNCTION_LO { 1279 format FloatCompareOp { 1280 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1281 UnorderedFalse, QnanException); 1282 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1283 UnorderedTrue, QnanException); 1284 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }}, 1285 UnorderedFalse, QnanException); 1286 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }}, 1287 UnorderedTrue, QnanException); 1288 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }}, 1289 UnorderedFalse, QnanException); 1290 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 1291 UnorderedTrue, QnanException); 1292 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 1293 UnorderedFalse, QnanException); 1294 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 1295 UnorderedTrue, QnanException); 1296 } 1297 } 1298 default: CP1Unimpl::unknown(); 1299 } 1300 0x2: CP1Unimpl::unknown(); 1301 0x3: CP1Unimpl::unknown(); 1302 0x7: CP1Unimpl::unknown(); 1303 1304 //Table A-16 MIPS32 COP1 Encoding of Function 1305 //Field When rs=W 1306 0x4: decode FUNCTION { 1307 format FloatConvertOp { 1308 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 1309 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 1310 0x26: CP1Unimpl::cvt_ps_w(); 1311 } 1312 default: CP1Unimpl::unknown(); 1313 } 1314 1315 //Table A-16 MIPS32 COP1 Encoding of Function Field 1316 //When rs=L1 1317 //Note: "1. Format type L is legal only if 64-bit 1318 //floating point operations are enabled." 1319 0x5: decode FUNCTION_HI { 1320 format FloatConvertOp { 1321 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 1322 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 1323 0x26: CP1Unimpl::cvt_ps_l(); 1324 } 1325 default: CP1Unimpl::unknown(); 1326 } 1327 1328 //Table A-17 MIPS64 COP1 Encoding of Function Field 1329 //When rs=PS1 1330 //Note: "1. Format type PS is legal only if 64-bit 1331 //floating point operations are enabled. " 1332 0x6: decode FUNCTION_HI { 1333 0x0: decode FUNCTION_LO { 1334 format Float64Op { 1335 0x0: add_ps({{ 1336 Fd1.sf = Fs1.sf + Ft2.sf; 1337 Fd2.sf = Fs2.sf + Ft2.sf; 1338 }}); 1339 0x1: sub_ps({{ 1340 Fd1.sf = Fs1.sf - Ft2.sf; 1341 Fd2.sf = Fs2.sf - Ft2.sf; 1342 }}); 1343 0x2: mul_ps({{ 1344 Fd1.sf = Fs1.sf * Ft2.sf; 1345 Fd2.sf = Fs2.sf * Ft2.sf; 1346 }}); 1347 0x5: abs_ps({{ 1348 Fd1.sf = fabs(Fs1.sf); 1349 Fd2.sf = fabs(Fs2.sf); 1350 }}); 1351 0x6: mov_ps({{ 1352 Fd1.sf = Fs1.sf; 1353 Fd2.sf = Fs2.sf; 1354 }}); 1355 0x7: neg_ps({{ 1356 Fd1.sf = -(Fs1.sf); 1357 Fd2.sf = -(Fs2.sf); 1358 }}); 1359 default: CP1Unimpl::unknown(); 1360 } 1361 } 1362 0x1: CP1Unimpl::unknown(); 1363 0x2: decode FUNCTION_LO { 1364 0x1: decode MOVCF { 1365 format Float64Op { 1366 0x0: movf_ps({{ 1367 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1368 Fs1 : Fd1; 1369 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1370 Fs2 : Fd2; 1371 }}); 1372 0x1: movt_ps({{ 1373 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1374 Fs1 : Fd1; 1375 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1376 Fs2 : Fd2; 1377 }}); 1378 } 1379 } 1380 1381 format Float64Op { 1382 0x2: movz_ps({{ 1383 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1384 Fs1 : Fd1; 1385 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1386 Fs2 : Fd2; 1387 }}); 1388 0x3: movn_ps({{ 1389 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1390 Fs1 : Fd1; 1391 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1392 Fs2 : Fd2; 1393 }}); 1394 } 1395 default: CP1Unimpl::unknown(); 1396 } 1397 0x3: CP1Unimpl::unknown(); 1398 0x4: decode FUNCTION_LO { 1399 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 1400 default: CP1Unimpl::unknown(); 1401 } 1402 1403 0x5: decode FUNCTION_LO { 1404 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); 1405 format Float64Op { 1406 0x4: pll({{ 1407 Fd.ud = (uint64_t)Fs1.uw << 32 | Ft1.uw; 1408 }}); 1409 0x5: plu({{ 1410 Fd.ud = (uint64_t)Fs1.uw << 32 | Ft2.uw; 1411 }}); 1412 0x6: pul({{ 1413 Fd.ud = (uint64_t)Fs2.uw << 32 | Ft1.uw; 1414 }}); 1415 0x7: puu({{ 1416 Fd.ud = (uint64_t)Fs2.uw << 32 | Ft2.uw; 1417 }}); 1418 } 1419 default: CP1Unimpl::unknown(); 1420 } 1421 1422 0x6: decode FUNCTION_LO { 1423 format FloatPSCompareOp { 1424 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1425 UnorderedFalse); 1426 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1427 UnorderedTrue); 1428 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1429 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1430 UnorderedFalse); 1431 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1432 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1433 UnorderedTrue); 1434 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1435 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1436 UnorderedFalse); 1437 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }}, 1438 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1439 UnorderedTrue); 1440 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }}, 1441 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1442 UnorderedFalse); 1443 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1444 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1445 UnorderedTrue); 1446 } 1447 } 1448 1449 0x7: decode FUNCTION_LO { 1450 format FloatPSCompareOp { 1451 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1452 UnorderedFalse, QnanException); 1453 0x1: c_ngle_ps({{ cond1 = 0; }}, 1454 {{ cond2 = 0; }}, 1455 UnorderedTrue, QnanException); 1456 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1457 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1458 UnorderedFalse, QnanException); 1459 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1460 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1461 UnorderedTrue, QnanException); 1462 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1463 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1464 UnorderedFalse, QnanException); 1465 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1466 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1467 UnorderedTrue, QnanException); 1468 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1469 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1470 UnorderedFalse, QnanException); 1471 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1472 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1473 UnorderedTrue, QnanException); 1474 } 1475 } 1476 } 1477 } 1478 default: CP1Unimpl::unknown(); 1479 } 1480 } 1481 1482 //Table A-19 MIPS32 COP2 Encoding of rs Field 1483 0x2: decode RS_MSB { 1484 format CP2Unimpl { 1485 0x0: decode RS_HI { 1486 0x0: decode RS_LO { 1487 0x0: mfc2(); 1488 0x2: cfc2(); 1489 0x3: mfhc2(); 1490 0x4: mtc2(); 1491 0x6: ctc2(); 1492 0x7: mftc2(); 1493 default: unknown(); 1494 } 1495 1496 0x1: decode ND { 1497 0x0: decode TF { 1498 0x0: bc2f(); 1499 0x1: bc2t(); 1500 default: unknown(); 1501 } 1502 1503 0x1: decode TF { 1504 0x0: bc2fl(); 1505 0x1: bc2tl(); 1506 default: unknown(); 1507 } 1508 default: unknown(); 1509 1510 } 1511 default: unknown(); 1512 } 1513 default: unknown(); 1514 } 1515 } 1516 1517 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1518 //Note: "COP1X instructions are legal only if 64-bit floating point 1519 //operations are enabled." 1520 0x3: decode FUNCTION_HI { 1521 0x0: decode FUNCTION_LO { 1522 format LoadIndexedMemory { 1523 0x0: lwxc1({{ Fd.uw = Mem.uw; }}); 1524 0x1: ldxc1({{ Fd.ud = Mem.ud; }}); 1525 0x5: luxc1({{ Fd.ud = Mem.ud; }}, 1526 {{ EA = (Rs + Rt) & ~7; }}); 1527 } 1528 } 1529 1530 0x1: decode FUNCTION_LO { 1531 format StoreIndexedMemory { 1532 0x0: swxc1({{ Mem.uw = Fs.uw; }}); 1533 0x1: sdxc1({{ Mem.ud = Fs.ud; }}); 1534 0x5: suxc1({{ Mem.ud = Fs.ud; }}, 1535 {{ EA = (Rs + Rt) & ~7; }}); 1536 } 1537 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1538 } 1539 1540 0x3: decode FUNCTION_LO { 1541 0x6: Float64Op::alnv_ps({{ 1542 if (Rs<2:0> == 0) { 1543 Fd.ud = Fs.ud; 1544 } else if (Rs<2:0> == 4) { 1545#if BYTE_ORDER == BIG_ENDIAN 1546 Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>; 1547#elif BYTE_ORDER == LITTLE_ENDIAN 1548 Fd.ud = Ft.ud<31:0> << 32 | Fs.ud<63:32>; 1549#endif 1550 } else { 1551 Fd.ud = Fd.ud; 1552 } 1553 }}); 1554 } 1555 1556 format FloatAccOp { 1557 0x4: decode FUNCTION_LO { 1558 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 1559 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 1560 0x6: madd_ps({{ 1561 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; 1562 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; 1563 }}); 1564 } 1565 1566 0x5: decode FUNCTION_LO { 1567 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); 1568 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 1569 0x6: msub_ps({{ 1570 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; 1571 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; 1572 }}); 1573 } 1574 1575 0x6: decode FUNCTION_LO { 1576 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1577 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 1578 0x6: nmadd_ps({{ 1579 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df); 1580 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df); 1581 }}); 1582 } 1583 1584 0x7: decode FUNCTION_LO { 1585 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1586 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 1587 0x6: nmsub_ps({{ 1588 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 1589 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 1590 }}); 1591 } 1592 } 1593 } 1594 1595 format Branch { 1596 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 1597 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 1598 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 1599 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 1600 } 1601 } 1602 1603 0x3: decode OPCODE_LO { 1604 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1605 0x4: decode FUNCTION_HI { 1606 0x0: decode FUNCTION_LO { 1607 0x2: IntOp::mul({{ 1608 int64_t temp1 = Rs.sd * Rt.sd; 1609 Rd.sw = temp1<31:0>; 1610 }}, IntMultOp); 1611 1612 format HiLoRdSelValOp { 1613 0x0: madd({{ 1614 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1615 (Rs.sd * Rt.sd); 1616 }}, IntMultOp); 1617 0x1: maddu({{ 1618 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1619 (Rs.ud * Rt.ud); 1620 }}, IntMultOp); 1621 0x4: msub({{ 1622 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1623 (Rs.sd * Rt.sd); 1624 }}, IntMultOp); 1625 0x5: msubu({{ 1626 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1627 (Rs.ud * Rt.ud); 1628 }}, IntMultOp); 1629 } 1630 } 1631 1632 0x4: decode FUNCTION_LO { 1633 format BasicOp { 1634 0x0: clz({{ 1635 int cnt = 32; 1636 for (int idx = 31; idx >= 0; idx--) { 1637 if (Rs<idx:idx> == 1) { 1638 cnt = 31 - idx; 1639 break; 1640 } 1641 } 1642 Rd.uw = cnt; 1643 }}); 1644 0x1: clo({{ 1645 int cnt = 32; 1646 for (int idx = 31; idx >= 0; idx--) { 1647 if (Rs<idx:idx> == 0) { 1648 cnt = 31 - idx; 1649 break; 1650 } 1651 } 1652 Rd.uw = cnt; 1653 }}); 1654 } 1655 } 1656 1657 0x7: decode FUNCTION_LO { 1658 0x7: FailUnimpl::sdbbp(); 1659 } 1660 } 1661 1662 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1663 //of the Architecture 1664 0x7: decode FUNCTION_HI { 1665 0x0: decode FUNCTION_LO { 1666 format BasicOp { 1667 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); 1668 0x4: ins({{ 1669 Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 1670 bits(Rs.uw, MSB-LSB, 0) << LSB | 1671 bits(Rt.uw, LSB-1, 0); 1672 }}); 1673 } 1674 } 1675 1676 0x1: decode FUNCTION_LO { 1677 format MT_Control { 1678 0x0: fork({{ 1679 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1680 }}, UserMode); 1681 0x1: yield({{ 1682 Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, 1683 YQMask); 1684 }}, UserMode); 1685 } 1686 1687 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1688 0x2: decode OP_HI { 1689 0x0: decode OP_LO { 1690 format LoadIndexedMemory { 1691 0x0: lwx({{ Rd.sw = Mem.sw; }}); 1692 0x4: lhx({{ Rd.sw = Mem.sh; }}); 1693 0x6: lbux({{ Rd.uw = Mem.ub; }}); 1694 } 1695 } 1696 } 1697 0x4: DspIntOp::insv({{ 1698 int pos = dspctl<5:0>; 1699 int size = dspctl<12:7> - 1; 1700 Rt.uw = insertBits(Rt.uw, pos+size, 1701 pos, Rs.uw<size:0>); 1702 }}); 1703 } 1704 1705 0x2: decode FUNCTION_LO { 1706 1707 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1708 //(DSP ASE MANUAL) 1709 0x0: decode OP_HI { 1710 0x0: decode OP_LO { 1711 format DspIntOp { 1712 0x0: addu_qb({{ 1713 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1714 NOSATURATE, UNSIGNED, &dspctl); 1715 }}); 1716 0x1: subu_qb({{ 1717 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, 1718 NOSATURATE, UNSIGNED, &dspctl); 1719 }}); 1720 0x4: addu_s_qb({{ 1721 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1722 SATURATE, UNSIGNED, &dspctl); 1723 }}); 1724 0x5: subu_s_qb({{ 1725 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, 1726 SATURATE, UNSIGNED, &dspctl); 1727 }}); 1728 0x6: muleu_s_ph_qbl({{ 1729 Rd.uw = dspMuleu(Rs.uw, Rt.uw, 1730 MODE_L, &dspctl); 1731 }}, IntMultOp); 1732 0x7: muleu_s_ph_qbr({{ 1733 Rd.uw = dspMuleu(Rs.uw, Rt.uw, 1734 MODE_R, &dspctl); 1735 }}, IntMultOp); 1736 } 1737 } 1738 0x1: decode OP_LO { 1739 format DspIntOp { 1740 0x0: addu_ph({{ 1741 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1742 NOSATURATE, UNSIGNED, &dspctl); 1743 }}); 1744 0x1: subu_ph({{ 1745 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1746 NOSATURATE, UNSIGNED, &dspctl); 1747 }}); 1748 0x2: addq_ph({{ 1749 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1750 NOSATURATE, SIGNED, &dspctl); 1751 }}); 1752 0x3: subq_ph({{ 1753 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1754 NOSATURATE, SIGNED, &dspctl); 1755 }}); 1756 0x4: addu_s_ph({{ 1757 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1758 SATURATE, UNSIGNED, &dspctl); 1759 }}); 1760 0x5: subu_s_ph({{ 1761 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1762 SATURATE, UNSIGNED, &dspctl); 1763 }}); 1764 0x6: addq_s_ph({{ 1765 Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, 1766 SATURATE, SIGNED, &dspctl); 1767 }}); 1768 0x7: subq_s_ph({{ 1769 Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, 1770 SATURATE, SIGNED, &dspctl); 1771 }}); 1772 } 1773 } 1774 0x2: decode OP_LO { 1775 format DspIntOp { 1776 0x0: addsc({{ 1777 int64_t dresult; 1778 dresult = Rs.ud + Rt.ud; 1779 Rd.sw = dresult<31:0>; 1780 dspctl = insertBits(dspctl, 13, 13, 1781 dresult<32:32>); 1782 }}); 1783 0x1: addwc({{ 1784 int64_t dresult; 1785 dresult = Rs.sd + Rt.sd + dspctl<13:13>; 1786 Rd.sw = dresult<31:0>; 1787 if (dresult<32:32> != dresult<31:31>) 1788 dspctl = insertBits(dspctl, 20, 20, 1); 1789 }}); 1790 0x2: modsub({{ 1791 Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : 1792 Rs.sw - Rt.sw<7:0>; 1793 }}); 1794 0x4: raddu_w_qb({{ 1795 Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + 1796 Rs.uw<15:8> + Rs.uw<7:0>; 1797 }}); 1798 0x6: addq_s_w({{ 1799 Rd.sw = dspAdd(Rs.sw, Rt.sw, SIMD_FMT_W, 1800 SATURATE, SIGNED, &dspctl); 1801 }}); 1802 0x7: subq_s_w({{ 1803 Rd.sw = dspSub(Rs.sw, Rt.sw, SIMD_FMT_W, 1804 SATURATE, SIGNED, &dspctl); 1805 }}); 1806 } 1807 } 1808 0x3: decode OP_LO { 1809 format DspIntOp { 1810 0x4: muleq_s_w_phl({{ 1811 Rd.sw = dspMuleq(Rs.sw, Rt.sw, 1812 MODE_L, &dspctl); 1813 }}, IntMultOp); 1814 0x5: muleq_s_w_phr({{ 1815 Rd.sw = dspMuleq(Rs.sw, Rt.sw, 1816 MODE_R, &dspctl); 1817 }}, IntMultOp); 1818 0x6: mulq_s_ph({{ 1819 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, 1820 SATURATE, NOROUND, &dspctl); 1821 }}, IntMultOp); 1822 0x7: mulq_rs_ph({{ 1823 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, 1824 SATURATE, ROUND, &dspctl); 1825 }}, IntMultOp); 1826 } 1827 } 1828 } 1829 1830 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1831 //(DSP ASE MANUAL) 1832 0x1: decode OP_HI { 1833 0x0: decode OP_LO { 1834 format DspIntOp { 1835 0x0: cmpu_eq_qb({{ 1836 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1837 UNSIGNED, CMP_EQ, &dspctl); 1838 }}); 1839 0x1: cmpu_lt_qb({{ 1840 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1841 UNSIGNED, CMP_LT, &dspctl); 1842 }}); 1843 0x2: cmpu_le_qb({{ 1844 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, 1845 UNSIGNED, CMP_LE, &dspctl); 1846 }}); 1847 0x3: pick_qb({{ 1848 Rd.uw = dspPick(Rs.uw, Rt.uw, 1849 SIMD_FMT_QB, &dspctl); 1850 }}); 1851 0x4: cmpgu_eq_qb({{ 1852 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1853 UNSIGNED, CMP_EQ ); 1854 }}); 1855 0x5: cmpgu_lt_qb({{ 1856 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1857 UNSIGNED, CMP_LT); 1858 }}); 1859 0x6: cmpgu_le_qb({{ 1860 Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, 1861 UNSIGNED, CMP_LE); 1862 }}); 1863 } 1864 } 1865 0x1: decode OP_LO { 1866 format DspIntOp { 1867 0x0: cmp_eq_ph({{ 1868 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1869 SIGNED, CMP_EQ, &dspctl); 1870 }}); 1871 0x1: cmp_lt_ph({{ 1872 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1873 SIGNED, CMP_LT, &dspctl); 1874 }}); 1875 0x2: cmp_le_ph({{ 1876 dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, 1877 SIGNED, CMP_LE, &dspctl); 1878 }}); 1879 0x3: pick_ph({{ 1880 Rd.uw = dspPick(Rs.uw, Rt.uw, 1881 SIMD_FMT_PH, &dspctl); 1882 }}); 1883 0x4: precrq_qb_ph({{ 1884 Rd.uw = Rs.uw<31:24> << 24 | 1885 Rs.uw<15:8> << 16 | 1886 Rt.uw<31:24> << 8 | 1887 Rt.uw<15:8>; 1888 }}); 1889 0x5: precr_qb_ph({{ 1890 Rd.uw = Rs.uw<23:16> << 24 | 1891 Rs.uw<7:0> << 16 | 1892 Rt.uw<23:16> << 8 | 1893 Rt.uw<7:0>; 1894 }}); 1895 0x6: packrl_ph({{ 1896 Rd.uw = dspPack(Rs.uw, Rt.uw, SIMD_FMT_PH); 1897 }}); 1898 0x7: precrqu_s_qb_ph({{ 1899 Rd.uw = dspPrecrqu(Rs.uw, Rt.uw, &dspctl); 1900 }}); 1901 } 1902 } 1903 0x2: decode OP_LO { 1904 format DspIntOp { 1905 0x4: precrq_ph_w({{ 1906 Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; 1907 }}); 1908 0x5: precrq_rs_ph_w({{ 1909 Rd.uw = dspPrecrq(Rs.uw, Rt.uw, 1910 SIMD_FMT_W, &dspctl); 1911 }}); 1912 } 1913 } 1914 0x3: decode OP_LO { 1915 format DspIntOp { 1916 0x0: cmpgdu_eq_qb({{ 1917 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1918 UNSIGNED, CMP_EQ, &dspctl); 1919 }}); 1920 0x1: cmpgdu_lt_qb({{ 1921 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1922 UNSIGNED, CMP_LT, &dspctl); 1923 }}); 1924 0x2: cmpgdu_le_qb({{ 1925 Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, 1926 UNSIGNED, CMP_LE, &dspctl); 1927 }}); 1928 0x6: precr_sra_ph_w({{ 1929 Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, 1930 SIMD_FMT_W, NOROUND); 1931 }}); 1932 0x7: precr_sra_r_ph_w({{ 1933 Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, 1934 SIMD_FMT_W, ROUND); 1935 }}); 1936 } 1937 } 1938 } 1939 1940 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1941 //(DSP ASE MANUAL) 1942 0x2: decode OP_HI { 1943 0x0: decode OP_LO { 1944 format DspIntOp { 1945 0x1: absq_s_qb({{ 1946 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_QB, &dspctl); 1947 }}); 1948 0x2: repl_qb({{ 1949 Rd.uw = RS_RT<7:0> << 24 | 1950 RS_RT<7:0> << 16 | 1951 RS_RT<7:0> << 8 | 1952 RS_RT<7:0>; 1953 }}); 1954 0x3: replv_qb({{ 1955 Rd.sw = Rt.uw<7:0> << 24 | 1956 Rt.uw<7:0> << 16 | 1957 Rt.uw<7:0> << 8 | 1958 Rt.uw<7:0>; 1959 }}); 1960 0x4: precequ_ph_qbl({{ 1961 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1962 SIMD_FMT_PH, SIGNED, MODE_L); 1963 }}); 1964 0x5: precequ_ph_qbr({{ 1965 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1966 SIMD_FMT_PH, SIGNED, MODE_R); 1967 }}); 1968 0x6: precequ_ph_qbla({{ 1969 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1970 SIMD_FMT_PH, SIGNED, MODE_LA); 1971 }}); 1972 0x7: precequ_ph_qbra({{ 1973 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, 1974 SIMD_FMT_PH, SIGNED, MODE_RA); 1975 }}); 1976 } 1977 } 1978 0x1: decode OP_LO { 1979 format DspIntOp { 1980 0x1: absq_s_ph({{ 1981 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_PH, &dspctl); 1982 }}); 1983 0x2: repl_ph({{ 1984 Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | 1985 (sext<10>(RS_RT))<15:0>; 1986 }}); 1987 0x3: replv_ph({{ 1988 Rd.uw = Rt.uw<15:0> << 16 | 1989 Rt.uw<15:0>; 1990 }}); 1991 0x4: preceq_w_phl({{ 1992 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, 1993 SIMD_FMT_W, SIGNED, MODE_L); 1994 }}); 1995 0x5: preceq_w_phr({{ 1996 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, 1997 SIMD_FMT_W, SIGNED, MODE_R); 1998 }}); 1999 } 2000 } 2001 0x2: decode OP_LO { 2002 format DspIntOp { 2003 0x1: absq_s_w({{ 2004 Rd.sw = dspAbs(Rt.sw, SIMD_FMT_W, &dspctl); 2005 }}); 2006 } 2007 } 2008 0x3: decode OP_LO { 2009 0x3: IntOp::bitrev({{ 2010 Rd.uw = bitrev( Rt.uw<15:0> ); 2011 }}); 2012 format DspIntOp { 2013 0x4: preceu_ph_qbl({{ 2014 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2015 UNSIGNED, SIMD_FMT_PH, 2016 UNSIGNED, MODE_L); 2017 }}); 2018 0x5: preceu_ph_qbr({{ 2019 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2020 UNSIGNED, SIMD_FMT_PH, 2021 UNSIGNED, MODE_R ); 2022 }}); 2023 0x6: preceu_ph_qbla({{ 2024 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2025 UNSIGNED, SIMD_FMT_PH, 2026 UNSIGNED, MODE_LA ); 2027 }}); 2028 0x7: preceu_ph_qbra({{ 2029 Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, 2030 UNSIGNED, SIMD_FMT_PH, 2031 UNSIGNED, MODE_RA); 2032 }}); 2033 } 2034 } 2035 } 2036 2037 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 2038 //(DSP ASE MANUAL) 2039 0x3: decode OP_HI { 2040 0x0: decode OP_LO { 2041 format DspIntOp { 2042 0x0: shll_qb({{ 2043 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_QB, 2044 NOSATURATE, UNSIGNED, &dspctl); 2045 }}); 2046 0x1: shrl_qb({{ 2047 Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_QB, 2048 UNSIGNED); 2049 }}); 2050 0x2: shllv_qb({{ 2051 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_QB, 2052 NOSATURATE, UNSIGNED, &dspctl); 2053 }}); 2054 0x3: shrlv_qb({{ 2055 Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_QB, 2056 UNSIGNED); 2057 }}); 2058 0x4: shra_qb({{ 2059 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, 2060 NOROUND, SIGNED, &dspctl); 2061 }}); 2062 0x5: shra_r_qb({{ 2063 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, 2064 ROUND, SIGNED, &dspctl); 2065 }}); 2066 0x6: shrav_qb({{ 2067 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, 2068 NOROUND, SIGNED, &dspctl); 2069 }}); 2070 0x7: shrav_r_qb({{ 2071 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, 2072 ROUND, SIGNED, &dspctl); 2073 }}); 2074 } 2075 } 2076 0x1: decode OP_LO { 2077 format DspIntOp { 2078 0x0: shll_ph({{ 2079 Rd.uw = dspShll(Rt.uw, RS, SIMD_FMT_PH, 2080 NOSATURATE, SIGNED, &dspctl); 2081 }}); 2082 0x1: shra_ph({{ 2083 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, 2084 NOROUND, SIGNED, &dspctl); 2085 }}); 2086 0x2: shllv_ph({{ 2087 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, 2088 NOSATURATE, SIGNED, &dspctl); 2089 }}); 2090 0x3: shrav_ph({{ 2091 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, 2092 NOROUND, SIGNED, &dspctl); 2093 }}); 2094 0x4: shll_s_ph({{ 2095 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_PH, 2096 SATURATE, SIGNED, &dspctl); 2097 }}); 2098 0x5: shra_r_ph({{ 2099 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, 2100 ROUND, SIGNED, &dspctl); 2101 }}); 2102 0x6: shllv_s_ph({{ 2103 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, 2104 SATURATE, SIGNED, &dspctl); 2105 }}); 2106 0x7: shrav_r_ph({{ 2107 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, 2108 ROUND, SIGNED, &dspctl); 2109 }}); 2110 } 2111 } 2112 0x2: decode OP_LO { 2113 format DspIntOp { 2114 0x4: shll_s_w({{ 2115 Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_W, 2116 SATURATE, SIGNED, &dspctl); 2117 }}); 2118 0x5: shra_r_w({{ 2119 Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_W, 2120 ROUND, SIGNED, &dspctl); 2121 }}); 2122 0x6: shllv_s_w({{ 2123 Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_W, 2124 SATURATE, SIGNED, &dspctl); 2125 }}); 2126 0x7: shrav_r_w({{ 2127 Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_W, 2128 ROUND, SIGNED, &dspctl); 2129 }}); 2130 } 2131 } 2132 0x3: decode OP_LO { 2133 format DspIntOp { 2134 0x1: shrl_ph({{ 2135 Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_PH, 2136 UNSIGNED); 2137 }}); 2138 0x3: shrlv_ph({{ 2139 Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_PH, 2140 UNSIGNED); 2141 }}); 2142 } 2143 } 2144 } 2145 } 2146 2147 0x3: decode FUNCTION_LO { 2148 2149 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2150 //(DSP ASE Rev2 Manual) 2151 0x0: decode OP_HI { 2152 0x0: decode OP_LO { 2153 format DspIntOp { 2154 0x0: adduh_qb({{ 2155 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2156 NOROUND, UNSIGNED); 2157 }}); 2158 0x1: subuh_qb({{ 2159 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2160 NOROUND, UNSIGNED); 2161 }}); 2162 0x2: adduh_r_qb({{ 2163 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2164 ROUND, UNSIGNED); 2165 }}); 2166 0x3: subuh_r_qb({{ 2167 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, 2168 ROUND, UNSIGNED); 2169 }}); 2170 } 2171 } 2172 0x1: decode OP_LO { 2173 format DspIntOp { 2174 0x0: addqh_ph({{ 2175 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2176 NOROUND, SIGNED); 2177 }}); 2178 0x1: subqh_ph({{ 2179 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2180 NOROUND, SIGNED); 2181 }}); 2182 0x2: addqh_r_ph({{ 2183 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2184 ROUND, SIGNED); 2185 }}); 2186 0x3: subqh_r_ph({{ 2187 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, 2188 ROUND, SIGNED); 2189 }}); 2190 0x4: mul_ph({{ 2191 Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, 2192 NOSATURATE, &dspctl); 2193 }}, IntMultOp); 2194 0x6: mul_s_ph({{ 2195 Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, 2196 SATURATE, &dspctl); 2197 }}, IntMultOp); 2198 } 2199 } 2200 0x2: decode OP_LO { 2201 format DspIntOp { 2202 0x0: addqh_w({{ 2203 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, 2204 NOROUND, SIGNED); 2205 }}); 2206 0x1: subqh_w({{ 2207 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, 2208 NOROUND, SIGNED); 2209 }}); 2210 0x2: addqh_r_w({{ 2211 Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, 2212 ROUND, SIGNED); 2213 }}); 2214 0x3: subqh_r_w({{ 2215 Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, 2216 ROUND, SIGNED); 2217 }}); 2218 0x6: mulq_s_w({{ 2219 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, 2220 SATURATE, NOROUND, &dspctl); 2221 }}, IntMultOp); 2222 0x7: mulq_rs_w({{ 2223 Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, 2224 SATURATE, ROUND, &dspctl); 2225 }}, IntMultOp); 2226 } 2227 } 2228 } 2229 } 2230 2231 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2232 0x4: decode SA { 2233 format BasicOp { 2234 0x02: wsbh({{ 2235 Rd.uw = Rt.uw<23:16> << 24 | 2236 Rt.uw<31:24> << 16 | 2237 Rt.uw<7:0> << 8 | 2238 Rt.uw<15:8>; 2239 }}); 2240 0x10: seb({{ Rd.sw = Rt.sb; }}); 2241 0x18: seh({{ Rd.sw = Rt.sh; }}); 2242 } 2243 } 2244 2245 0x6: decode FUNCTION_LO { 2246 2247 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2248 //(DSP ASE MANUAL) 2249 0x0: decode OP_HI { 2250 0x0: decode OP_LO { 2251 format DspHiLoOp { 2252 0x0: dpa_w_ph({{ 2253 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2254 SIMD_FMT_PH, SIGNED, MODE_L); 2255 }}, IntMultOp); 2256 0x1: dps_w_ph({{ 2257 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2258 SIMD_FMT_PH, SIGNED, MODE_L); 2259 }}, IntMultOp); 2260 0x2: mulsa_w_ph({{ 2261 dspac = dspMulsa(dspac, Rs.sw, Rt.sw, 2262 ACDST, SIMD_FMT_PH ); 2263 }}, IntMultOp); 2264 0x3: dpau_h_qbl({{ 2265 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2266 SIMD_FMT_QB, UNSIGNED, MODE_L); 2267 }}, IntMultOp); 2268 0x4: dpaq_s_w_ph({{ 2269 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2270 ACDST, SIMD_FMT_PH, 2271 SIMD_FMT_W, NOSATURATE, 2272 MODE_L, &dspctl); 2273 }}, IntMultOp); 2274 0x5: dpsq_s_w_ph({{ 2275 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2276 ACDST, SIMD_FMT_PH, 2277 SIMD_FMT_W, NOSATURATE, 2278 MODE_L, &dspctl); 2279 }}, IntMultOp); 2280 0x6: mulsaq_s_w_ph({{ 2281 dspac = dspMulsaq(dspac, Rs.sw, Rt.sw, 2282 ACDST, SIMD_FMT_PH, 2283 &dspctl); 2284 }}, IntMultOp); 2285 0x7: dpau_h_qbr({{ 2286 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2287 SIMD_FMT_QB, UNSIGNED, MODE_R); 2288 }}, IntMultOp); 2289 } 2290 } 2291 0x1: decode OP_LO { 2292 format DspHiLoOp { 2293 0x0: dpax_w_ph({{ 2294 dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, 2295 SIMD_FMT_PH, SIGNED, MODE_X); 2296 }}, IntMultOp); 2297 0x1: dpsx_w_ph({{ 2298 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2299 SIMD_FMT_PH, SIGNED, MODE_X); 2300 }}, IntMultOp); 2301 0x3: dpsu_h_qbl({{ 2302 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2303 SIMD_FMT_QB, UNSIGNED, MODE_L); 2304 }}, IntMultOp); 2305 0x4: dpaq_sa_l_w({{ 2306 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2307 ACDST, SIMD_FMT_W, 2308 SIMD_FMT_L, SATURATE, 2309 MODE_L, &dspctl); 2310 }}, IntMultOp); 2311 0x5: dpsq_sa_l_w({{ 2312 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2313 ACDST, SIMD_FMT_W, 2314 SIMD_FMT_L, SATURATE, 2315 MODE_L, &dspctl); 2316 }}, IntMultOp); 2317 0x7: dpsu_h_qbr({{ 2318 dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, 2319 SIMD_FMT_QB, UNSIGNED, MODE_R); 2320 }}, IntMultOp); 2321 } 2322 } 2323 0x2: decode OP_LO { 2324 format DspHiLoOp { 2325 0x0: maq_sa_w_phl({{ 2326 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2327 ACDST, SIMD_FMT_PH, 2328 MODE_L, SATURATE, &dspctl); 2329 }}, IntMultOp); 2330 0x2: maq_sa_w_phr({{ 2331 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2332 ACDST, SIMD_FMT_PH, 2333 MODE_R, SATURATE, &dspctl); 2334 }}, IntMultOp); 2335 0x4: maq_s_w_phl({{ 2336 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2337 ACDST, SIMD_FMT_PH, 2338 MODE_L, NOSATURATE, &dspctl); 2339 }}, IntMultOp); 2340 0x6: maq_s_w_phr({{ 2341 dspac = dspMaq(dspac, Rs.uw, Rt.uw, 2342 ACDST, SIMD_FMT_PH, 2343 MODE_R, NOSATURATE, &dspctl); 2344 }}, IntMultOp); 2345 } 2346 } 2347 0x3: decode OP_LO { 2348 format DspHiLoOp { 2349 0x0: dpaqx_s_w_ph({{ 2350 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2351 ACDST, SIMD_FMT_PH, 2352 SIMD_FMT_W, NOSATURATE, 2353 MODE_X, &dspctl); 2354 }}, IntMultOp); 2355 0x1: dpsqx_s_w_ph({{ 2356 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2357 ACDST, SIMD_FMT_PH, 2358 SIMD_FMT_W, NOSATURATE, 2359 MODE_X, &dspctl); 2360 }}, IntMultOp); 2361 0x2: dpaqx_sa_w_ph({{ 2362 dspac = dspDpaq(dspac, Rs.sw, Rt.sw, 2363 ACDST, SIMD_FMT_PH, 2364 SIMD_FMT_W, SATURATE, 2365 MODE_X, &dspctl); 2366 }}, IntMultOp); 2367 0x3: dpsqx_sa_w_ph({{ 2368 dspac = dspDpsq(dspac, Rs.sw, Rt.sw, 2369 ACDST, SIMD_FMT_PH, 2370 SIMD_FMT_W, SATURATE, 2371 MODE_X, &dspctl); 2372 }}, IntMultOp); 2373 } 2374 } 2375 } 2376 2377 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2378 0x1: decode OP_HI { 2379 0x0: decode OP_LO { 2380 format IntOp { 2381 0x0: append({{ 2382 Rt.uw = (Rt.uw << RD) | bits(Rs.uw, RD - 1, 0); 2383 }}); 2384 0x1: prepend({{ 2385 Rt.uw = (Rt.uw >> RD) | 2386 (bits(Rs.uw, RD - 1, 0) << (32 - RD)); 2387 }}); 2388 } 2389 } 2390 0x2: decode OP_LO { 2391 format IntOp { 2392 0x0: balign({{ 2393 Rt.uw = (Rt.uw << (8 * BP)) | 2394 (Rs.uw >> (8 * (4 - BP))); 2395 }}); 2396 } 2397 } 2398 } 2399 2400 } 2401 0x7: decode FUNCTION_LO { 2402 2403 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2404 //(DSP ASE MANUAL) 2405 0x0: decode OP_HI { 2406 0x0: decode OP_LO { 2407 format DspHiLoOp { 2408 0x0: extr_w({{ 2409 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2410 NOROUND, NOSATURATE, &dspctl); 2411 }}); 2412 0x1: extrv_w({{ 2413 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2414 NOROUND, NOSATURATE, &dspctl); 2415 }}); 2416 0x2: extp({{ 2417 Rt.uw = dspExtp(dspac, RS, &dspctl); 2418 }}); 2419 0x3: extpv({{ 2420 Rt.uw = dspExtp(dspac, Rs.uw, &dspctl); 2421 }}); 2422 0x4: extr_r_w({{ 2423 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2424 ROUND, NOSATURATE, &dspctl); 2425 }}); 2426 0x5: extrv_r_w({{ 2427 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2428 ROUND, NOSATURATE, &dspctl); 2429 }}); 2430 0x6: extr_rs_w({{ 2431 Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, 2432 ROUND, SATURATE, &dspctl); 2433 }}); 2434 0x7: extrv_rs_w({{ 2435 Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, 2436 ROUND, SATURATE, &dspctl); 2437 }}); 2438 } 2439 } 2440 0x1: decode OP_LO { 2441 format DspHiLoOp { 2442 0x2: extpdp({{ 2443 Rt.uw = dspExtpd(dspac, RS, &dspctl); 2444 }}); 2445 0x3: extpdpv({{ 2446 Rt.uw = dspExtpd(dspac, Rs.uw, &dspctl); 2447 }}); 2448 0x6: extr_s_h({{ 2449 Rt.uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2450 NOROUND, SATURATE, &dspctl); 2451 }}); 2452 0x7: extrv_s_h({{ 2453 Rt.uw = dspExtr(dspac, SIMD_FMT_PH, Rs.uw, 2454 NOROUND, SATURATE, &dspctl); 2455 }}); 2456 } 2457 } 2458 0x2: decode OP_LO { 2459 format DspIntOp { 2460 0x2: rddsp({{ 2461 Rd.uw = readDSPControl(&dspctl, RDDSPMASK); 2462 }}); 2463 0x3: wrdsp({{ 2464 writeDSPControl(&dspctl, Rs.uw, WRDSPMASK); 2465 }}); 2466 } 2467 } 2468 0x3: decode OP_LO { 2469 format DspHiLoOp { 2470 0x2: shilo({{ 2471 if (sext<6>(HILOSA) < 0) { 2472 dspac = (uint64_t)dspac << 2473 -sext<6>(HILOSA); 2474 } else { 2475 dspac = (uint64_t)dspac >> 2476 sext<6>(HILOSA); 2477 } 2478 }}); 2479 0x3: shilov({{ 2480 if (sext<6>(Rs.sw<5:0>) < 0) { 2481 dspac = (uint64_t)dspac << 2482 -sext<6>(Rs.sw<5:0>); 2483 } else { 2484 dspac = (uint64_t)dspac >> 2485 sext<6>(Rs.sw<5:0>); 2486 } 2487 }}); 2488 0x7: mthlip({{ 2489 dspac = dspac << 32; 2490 dspac |= Rs.uw; 2491 dspctl = insertBits(dspctl, 5, 0, 2492 dspctl<5:0> + 32); 2493 }}); 2494 } 2495 } 2496 } 2497 0x3: decode OP { 2498#if FULL_SYSTEM 2499 0x0: FailUnimpl::rdhwr(); 2500#else 2501 0x0: decode RD { 2502 29: BasicOp::rdhwr({{ Rt = TpValue; }}); 2503 } 2504#endif 2505 } 2506 } 2507 } 2508 } 2509 2510 0x4: decode OPCODE_LO { 2511 format LoadMemory { 2512 0x0: lb({{ Rt.sw = Mem.sb; }}); 2513 0x1: lh({{ Rt.sw = Mem.sh; }}); 2514 0x3: lw({{ Rt.sw = Mem.sw; }}); 2515 0x4: lbu({{ Rt.uw = Mem.ub;}}); 2516 0x5: lhu({{ Rt.uw = Mem.uh; }}); 2517 } 2518 2519 format LoadUnalignedMemory { 2520 0x2: lwl({{ 2521 uint32_t mem_shift = 24 - (8 * byte_offset); 2522 Rt.uw = mem_word << mem_shift | (Rt.uw & mask(mem_shift)); 2523 }}); 2524 0x6: lwr({{ 2525 uint32_t mem_shift = 8 * byte_offset; 2526 Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) | 2527 (mem_word >> mem_shift); 2528 }}); 2529 } 2530 } 2531 2532 0x5: decode OPCODE_LO { 2533 format StoreMemory { 2534 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 2535 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 2536 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 2537 } 2538 2539 format StoreUnalignedMemory { 2540 0x2: swl({{ 2541 uint32_t reg_shift = 24 - (8 * byte_offset); 2542 uint32_t mem_shift = 32 - reg_shift; 2543 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2544 (Rt.uw >> reg_shift); 2545 }}); 2546 0x6: swr({{ 2547 uint32_t reg_shift = 8 * byte_offset; 2548 mem_word = Rt.uw << reg_shift | 2549 (mem_word & (mask(reg_shift))); 2550 }}); 2551 } 2552 format CP0Control { 2553 0x7: cache({{ 2554 //Addr CacheEA = Rs.uw + OFFSET; 2555 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2556 }}); 2557 } 2558 } 2559 2560 0x6: decode OPCODE_LO { 2561 format LoadMemory { 2562 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LLSC); 2563 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 2564 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 2565 } 2566 0x2: CP2Unimpl::lwc2(); 2567 0x6: CP2Unimpl::ldc2(); 2568 0x3: Prefetch::pref(); 2569 } 2570 2571 2572 0x7: decode OPCODE_LO { 2573 0x0: StoreCond::sc({{ Mem.uw = Rt.uw; }}, 2574 {{ uint64_t tmp = write_result; 2575 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; 2576 }}, mem_flags=LLSC, 2577 inst_flags = IsStoreConditional); 2578 format StoreMemory { 2579 0x1: swc1({{ Mem.uw = Ft.uw; }}); 2580 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 2581 } 2582 0x2: CP2Unimpl::swc2(); 2583 0x6: CP2Unimpl::sdc2(); 2584 } 2585} 2586 2587 2588