decoder.isa revision 6376:eaf61ef6a8f2
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30// Brett Miller 31// Jaidev Patwardhan 32 33//////////////////////////////////////////////////////////////////// 34// 35// The actual MIPS32 ISA decoder 36// ----------------------------- 37// The following instructions are specified in the MIPS32 ISA 38// Specification. Decoding closely follows the style specified 39// in the MIPS32 ISA specification document starting with Table 40// A-2 (document available @ http://www.mips.com) 41// 42decode OPCODE_HI default Unknown::unknown() { 43 //Table A-2 44 0x0: decode OPCODE_LO { 45 0x0: decode FUNCTION_HI { 46 0x0: decode FUNCTION_LO { 47 0x1: decode MOVCI { 48 format BasicOp { 49 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }}); 50 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }}); 51 } 52 } 53 54 format BasicOp { 55 //Table A-3 Note: "Specific encodings of the rd, rs, and 56 //rt fields are used to distinguish SLL, SSNOP, and EHB 57 //functions 58 0x0: decode RS { 59 0x0: decode RT_RD { 60 0x0: decode SA default Nop::nop() { 61 0x1: ssnop({{;}}); 62 0x3: ehb({{;}}); 63 } 64 default: sll({{ Rd = Rt.uw << SA; }}); 65 } 66 } 67 68 0x2: decode RS_SRL { 69 0x0:decode SRL { 70 0: srl({{ Rd = Rt.uw >> SA; }}); 71 72 //Hardcoded assuming 32-bit ISA, probably need parameter here 73 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 74 } 75 } 76 77 0x3: decode RS { 78 0x0: sra({{ 79 uint32_t temp = Rt >> SA; 80 if ( (Rt & 0x80000000) > 0 ) { 81 uint32_t mask = 0x80000000; 82 for(int i=0; i < SA; i++) { 83 temp |= mask; 84 mask = mask >> 1; 85 } 86 } 87 Rd = temp; 88 }}); 89 } 90 91 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 92 93 0x6: decode SRLV { 94 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 95 96 //Hardcoded assuming 32-bit ISA, probably need parameter here 97 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 98 } 99 100 0x7: srav({{ 101 int shift_amt = Rs<4:0>; 102 103 uint32_t temp = Rt >> shift_amt; 104 105 if ( (Rt & 0x80000000) > 0 ) { 106 uint32_t mask = 0x80000000; 107 for(int i=0; i < shift_amt; i++) { 108 temp |= mask; 109 mask = mask >> 1; 110 } 111 } 112 113 Rd = temp; 114 }}); 115 } 116 } 117 118 0x1: decode FUNCTION_LO { 119 //Table A-3 Note: "Specific encodings of the hint field are 120 //used to distinguish JR from JR.HB and JALR from JALR.HB" 121 format Jump { 122 0x0: decode HINT { 123 0x1: jr_hb({{ 124 Config1Reg config1 = Config1; 125 if (config1.ca == 0) { 126 NNPC = Rs; 127 } else { 128 panic("MIPS16e not supported\n"); 129 } 130 }}, IsReturn, ClearHazards); 131 default: jr({{ 132 Config1Reg config1 = Config1; 133 if (config1.ca == 0) { 134 NNPC = Rs; 135 } else { 136 panic("MIPS16e not supported\n"); 137 } 138 }}, IsReturn); 139 } 140 141 0x1: decode HINT { 142 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall 143 , ClearHazards); 144 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall); 145 } 146 } 147 148 format BasicOp { 149 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 150 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 151#if FULL_SYSTEM 152 0x4: syscall({{ 153 fault = new SystemCallFault(); 154 }}); 155#else 156 0x4: syscall({{ xc->syscall(R2); }}, 157 IsSerializeAfter, IsNonSpeculative); 158#endif 159 0x7: sync({{ ; }}, IsMemBarrier); 160 0x5: break({{fault = new BreakpointFault();}}); 161 } 162 163 } 164 165 0x2: decode FUNCTION_LO { 166 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess); 167 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); 168 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess); 169 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 170 } 171 172 0x3: decode FUNCTION_LO { 173 format HiLoRdSelValOp { 174 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp); 175 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp); 176 } 177 178 format HiLoOp { 179 0x2: div({{ if (Rt.sd != 0) { 180 HI0 = Rs.sd % Rt.sd; 181 LO0 = Rs.sd / Rt.sd; 182 } 183 }}, IntDivOp); 184 185 0x3: divu({{ if (Rt.ud != 0) { 186 HI0 = Rs.ud % Rt.ud; 187 LO0 = Rs.ud / Rt.ud; 188 } 189 }}, IntDivOp); 190 } 191 } 192 193 0x4: decode HINT { 194 0x0: decode FUNCTION_LO { 195 format IntOp { 196 0x0: add({{ /* More complicated since an ADD can cause an arithmetic overflow exception */ 197 int64_t Src1 = Rs.sw; 198 int64_t Src2 = Rt.sw; 199 int64_t temp_result; 200#if FULL_SYSTEM 201 if(((Src1 >> 31) & 1) == 1) 202 Src1 |= 0x100000000LL; 203#endif 204 temp_result = Src1 + Src2; 205#if FULL_SYSTEM 206 if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ 207#endif 208 Rd.sw = temp_result; 209#if FULL_SYSTEM 210 } else{ 211 fault = new ArithmeticFault(); 212 } 213#endif 214 215 }}); 216 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 217 0x2: sub({{ 218 /* More complicated since an SUB can cause an arithmetic overflow exception */ 219 int64_t Src1 = Rs.sw; 220 int64_t Src2 = Rt.sw; 221 int64_t temp_result = Src1 - Src2; 222#if FULL_SYSTEM 223 if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){ 224#endif 225 Rd.sw = temp_result; 226#if FULL_SYSTEM 227 } else{ 228 fault = new ArithmeticFault(); 229 } 230#endif 231 }}); 232 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 233 0x4: and({{ Rd = Rs & Rt;}}); 234 0x5: or({{ Rd = Rs | Rt;}}); 235 0x6: xor({{ Rd = Rs ^ Rt;}}); 236 0x7: nor({{ Rd = ~(Rs | Rt);}}); 237 } 238 } 239 } 240 241 0x5: decode HINT { 242 0x0: decode FUNCTION_LO { 243 format IntOp{ 244 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 245 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 246 } 247 } 248 } 249 250 0x6: decode FUNCTION_LO { 251 format Trap { 252 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 253 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 254 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 255 0x3: tltu({{ cond = (Rs.uw < Rt.uw); }}); 256 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 257 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 258 } 259 } 260 } 261 262 0x1: decode REGIMM_HI { 263 0x0: decode REGIMM_LO { 264 format Branch { 265 0x0: bltz({{ cond = (Rs.sw < 0); }}); 266 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 267 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely); 268 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely); 269 } 270 } 271 272 0x1: decode REGIMM_LO { 273 format TrapImm { 274 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }}); 275 0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }}); 276 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }}); 277 0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }}); 278 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}}); 279 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}}); 280 } 281 } 282 283 0x2: decode REGIMM_LO { 284 format Branch { 285 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link); 286 0x1: decode RS { 287 0x0: bal ({{ cond = 1; }}, IsCall, Link); 288 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link); 289 } 290 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely); 291 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely); 292 } 293 } 294 295 0x3: decode REGIMM_LO { 296 // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL) 297 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 298 format WarnUnimpl { 299 0x7: synci(); 300 } 301 } 302 } 303 304 format Jump { 305 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 306 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall, 307 Link); 308 } 309 310 format Branch { 311 0x4: decode RS_RT { 312 0x0: b({{ cond = 1; }}); 313 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 314 } 315 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 316 0x6: blez({{ cond = (Rs.sw <= 0); }}); 317 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 318 } 319 } 320 321 0x1: decode OPCODE_LO { 322 format IntImmOp { 323 0x0: addi({{ 324 int64_t Src1 = Rs.sw; 325 int64_t Src2 = imm; 326 int64_t temp_result; 327#if FULL_SYSTEM 328 if(((Src1 >> 31) & 1) == 1) 329 Src1 |= 0x100000000LL; 330#endif 331 temp_result = Src1 + Src2; 332#if FULL_SYSTEM 333 if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ 334#endif 335 Rt.sw = temp_result; 336#if FULL_SYSTEM 337 } else{ 338 fault = new ArithmeticFault(); 339 } 340#endif 341 }}); 342 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 343 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 344 345 //Edited to include MIPS AVP Pass/Fail instructions and 346 //default to the sltiu instruction 347 0x3: decode RS_RT_INTIMM { 348 0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }}); 349 0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }}); 350 default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 351 } 352 353 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 354 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 355 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 356 357 0x7: decode RS { 358 0x0: lui({{ Rt = imm << 16}}); 359 } 360 } 361 } 362 363 0x2: decode OPCODE_LO { 364 //Table A-11 MIPS32 COP0 Encoding of rs Field 365 0x0: decode RS_MSB { 366 0x0: decode RS { 367 format CP0Control { 368 0x0: mfc0({{ 369 Config3Reg config3 = Config3; 370 PageGrainReg pageGrain = PageGrain; 371 Rt = CP0_RD_SEL; 372 /* Hack for PageMask */ 373 if (RD == 5) { 374 // PageMask 375 if(config3.sp == 0 || pageGrain.esp == 0) 376 Rt &= 0xFFFFE7FF; 377 } 378 }}); 379 0x4: mtc0({{ 380 CP0_RD_SEL = Rt; 381 CauseReg cause = Cause; 382 IntCtlReg intCtl = IntCtl; 383 if (RD == 11) { 384 // Compare 385 if (cause.ti == 1) { 386 cause.ti = 0; 387 int offset = 10; // corresponding to cause.ip0 388 offset += intCtl.ipti - 2; 389 replaceBits(cause, offset, offset, 0); 390 } 391 } 392 Cause = cause; 393 }}); 394 } 395 format CP0Unimpl { 396 0x1: dmfc0(); 397 0x5: dmtc0(); 398 default: unknown(); 399 } 400 format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions 401 0x8: decode MT_U { 402 0x0: mftc0({{ 403 data = xc->readRegOtherThread((RT << 3 | SEL) + 404 Ctrl_Base_DepTag); 405 }}); 406 0x1: decode SEL { 407 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }}); 408 0x1: decode RT { 409 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }}); 410 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }}); 411 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }}); 412 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }}); 413 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }}); 414 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }}); 415 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }}); 416 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }}); 417 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }}); 418 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }}); 419 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }}); 420 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }}); 421 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }}); 422 default: CP0Unimpl::unknown(); 423 } 424 0x2: decode MT_H { 425 0x0: mftc1({{ data = xc->readRegOtherThread(RT + 426 FP_Base_DepTag); 427 }}); 428 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + 429 FP_Base_DepTag); 430 }}); 431 } 432 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR + 433 FP_Base_DepTag); 434 switch (RT) 435 { 436 case 0: 437 data = xc->readRegOtherThread(MipsISA::FIR + 438 Ctrl_Base_DepTag); 439 break; 440 case 25: 441 data = (fcsr_val & 0xFE000000 >> 24) 442 | (fcsr_val & 0x00800000 >> 23); 443 break; 444 case 26: 445 data = fcsr_val & 0x0003F07C; 446 break; 447 case 28: 448 data = (fcsr_val & 0x00000F80) 449 | (fcsr_val & 0x01000000 >> 21) 450 | (fcsr_val & 0x00000003); 451 break; 452 case 31: 453 data = fcsr_val; 454 break; 455 default: 456 fatal("FP Control Value (%d) Not Valid"); 457 } 458 }}); 459 default: CP0Unimpl::unknown(); 460 } 461 } 462 } 463 464 format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions 465 0xC: decode MT_U { 466 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, 467 Rt); 468 }}); 469 0x1: decode SEL { 470 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 471 0x1: decode RT { 472 0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt); 473 }}); 474 0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0, 475 Rt); 476 }}); 477 0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0, 478 Rt); 479 }}); 480 0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1, 481 Rt); 482 }}); 483 0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1, 484 Rt); 485 }}); 486 0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1, 487 Rt); 488 }}); 489 0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2, 490 Rt); 491 }}); 492 0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2, 493 Rt); 494 }}); 495 0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2, 496 Rt); 497 }}); 498 0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3, 499 Rt); 500 }}); 501 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3, 502 Rt); 503 }}); 504 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt); 505 }}); 506 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }}); 507 default: CP0Unimpl::unknown(); 508 509 } 510 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + 511 FP_Base_DepTag); 512 data = insertBits(data, top_bit, bottom_bit, Rt); 513 xc->setRegOtherThread(RD + FP_Base_DepTag, data); 514 }}); 515 0x3: cttc1({{ uint32_t data; 516 switch (RD) 517 { 518 case 25: 519 data = 0 | (Rt.uw<7:1> << 25) // move 31...25 520 | (FCSR & 0x01000000) // bit 24 521 | (FCSR & 0x004FFFFF);// bit 22...0 522 break; 523 524 case 26: 525 data = 0 | (FCSR & 0xFFFC0000) // move 31...18 526 | Rt.uw<17:12> << 12 // bit 17...12 527 | (FCSR & 0x00000F80) << 7// bit 11...7 528 | Rt.uw<6:2> << 2 // bit 6...2 529 | (FCSR & 0x00000002); // bit 1...0 530 break; 531 532 case 28: 533 data = 0 | (FCSR & 0xFE000000) // move 31...25 534 | Rt.uw<2:2> << 24 // bit 24 535 | (FCSR & 0x00FFF000) << 23// bit 23...12 536 | Rt.uw<11:7> << 7 // bit 24 537 | (FCSR & 0x000007E) 538 | Rt.uw<1:0>;// bit 22...0 539 break; 540 541 case 31: 542 data = Rt.uw; 543 break; 544 545 default: 546 panic("FP Control Value (%d) Not Available. Ignoring Access to" 547 "Floating Control Status Register", FS); 548 } 549 xc->setRegOtherThread(FCSR, data); 550 }}); 551 default: CP0Unimpl::unknown(); 552 } 553 } 554 } 555 556 557 0xB: decode RD { 558 format MT_Control { 559 0x0: decode POS { 560 0x0: decode SEL { 561 0x1: decode SC { 562 0x0: dvpe({{ 563 MVPControlReg mvpControl = MVPControl; 564 VPEConf0Reg vpeConf0 = VPEConf0; 565 Rt = MVPControl; 566 if (vpeConf0.mvp == 1) 567 mvpControl.evp = 0; 568 MVPControl = mvpControl; 569 }}); 570 0x1: evpe({{ 571 MVPControlReg mvpControl = MVPControl; 572 VPEConf0Reg vpeConf0 = VPEConf0; 573 Rt = MVPControl; 574 if (vpeConf0.mvp == 1) 575 mvpControl.evp = 1; 576 MVPControl = mvpControl; 577 }}); 578 default:CP0Unimpl::unknown(); 579 } 580 default:CP0Unimpl::unknown(); 581 } 582 default:CP0Unimpl::unknown(); 583 } 584 585 0x1: decode POS { 586 0xF: decode SEL { 587 0x1: decode SC { 588 0x0: dmt({{ 589 VPEControlReg vpeControl = VPEControl; 590 Rt = vpeControl; 591 vpeControl.te = 0; 592 VPEControl = vpeControl; 593 }}); 594 0x1: emt({{ 595 VPEControlReg vpeControl = VPEControl; 596 Rt = vpeControl; 597 vpeControl.te = 1; 598 VPEControl = vpeControl; 599 }}); 600 default:CP0Unimpl::unknown(); 601 } 602 default:CP0Unimpl::unknown(); 603 } 604 default:CP0Unimpl::unknown(); 605 } 606 } 607 0xC: decode POS { 608 0x0: decode SC { 609 0x0: CP0Control::di({{ 610 StatusReg status = Status; 611 ConfigReg config = Config; 612 // Rev 2.0 or beyond? 613 if (config.ar >= 1) { 614 Rt = status; 615 status.ie = 0; 616 } else { 617 // Enable this else branch once we 618 // actually set values for Config on init 619 fault = new ReservedInstructionFault(); 620 } 621 Status = status; 622 }}); 623 0x1: CP0Control::ei({{ 624 StatusReg status = Status; 625 ConfigReg config = Config; 626 if (config.ar >= 1) { 627 Rt = status; 628 status.ie = 1; 629 } else { 630 fault = new ReservedInstructionFault(); 631 } 632 }}); 633 default:CP0Unimpl::unknown(); 634 } 635 } 636 default: CP0Unimpl::unknown(); 637 } 638 format CP0Control { 639 0xA: rdpgpr({{ 640 ConfigReg config = Config; 641 if (config.ar >= 1) { 642 // Rev 2 of the architecture 643 panic("Shadow Sets Not Fully Implemented.\n"); 644 } else { 645 fault = new ReservedInstructionFault(); 646 } 647 }}); 648 0xE: wrpgpr({{ 649 ConfigReg config = Config; 650 if (config.ar >= 1) { 651 // Rev 2 of the architecture 652 panic("Shadow Sets Not Fully Implemented.\n"); 653 } else { 654 fault = new ReservedInstructionFault(); 655 } 656 }}); 657 } 658 659 } 660 661 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 662 0x1: decode FUNCTION { 663 format CP0Control { 664 0x18: eret({{ 665 StatusReg status = Status; 666 ConfigReg config = Config; 667 SRSCtlReg srsCtl = SRSCtl; 668 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 669 if (status.erl == 1) { 670 status.erl = 0; 671 NPC = ErrorEPC; 672 // Need to adjust NNPC, otherwise things break 673 NNPC = ErrorEPC + sizeof(MachInst); 674 } else { 675 NPC = EPC; 676 // Need to adjust NNPC, otherwise things break 677 NNPC = EPC + sizeof(MachInst); 678 status.exl = 0; 679 if (config.ar >=1 && 680 srsCtl.hss > 0 && 681 status.bev == 0) { 682 srsCtl.css = srsCtl.pss; 683 //xc->setShadowSet(srsCtl.pss); 684 } 685 } 686 LLFlag = 0; 687 Status = status; 688 SRSCtl = srsCtl; 689 }},IsReturn,IsSerializing,IsERET); 690 691 0x1F: deret({{ 692 DebugReg debug = Debug; 693 if (debug.dm == 1) { 694 debug.dm = 1; 695 debug.iexi = 0; 696 NPC = DEPC; 697 } else { 698 // Undefined; 699 } 700 Debug = debug; 701 }}, IsReturn, IsSerializing, IsERET); 702 } 703 format CP0TLB { 704 0x01: tlbr({{ 705 MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF); 706 if(PTEntry == NULL) 707 { 708 fatal("Invalid PTE Entry received on a TLBR instruction\n"); 709 } 710 /* Setup PageMask */ 711 PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11 712 /* Setup EntryHi */ 713 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 714 /* Setup Entry Lo0 */ 715 EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G); 716 /* Setup Entry Lo1 */ 717 EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G); 718 }}); // Need to hook up to TLB 719 720 0x02: tlbwi({{ 721 //Create PTE 722 MipsISA::PTE NewEntry; 723 //Write PTE 724 NewEntry.Mask = (Addr)(PageMask >> 11); 725 NewEntry.VPN = (Addr)(EntryHi >> 11); 726 /* PageGrain _ ESP Config3 _ SP */ 727 if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) { 728 // If 1KB pages are *NOT* enabled, lowest bits of the 729 // mask are 0b11 for TLB writes 730 NewEntry.Mask |= 0x3; 731 // Reset bits 0 and 1 if 1KB pages are not enabled 732 NewEntry.VPN &= 0xFFFFFFFC; 733 } 734 NewEntry.asid = (uint8_t)(EntryHi & 0xFF); 735 736 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); 737 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); 738 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 739 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 740 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 741 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 742 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 743 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 744 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 745 /* Now, compute the AddrShiftAmount and OffsetMask - TLB 746 optimizations */ 747 /* Addr Shift Amount for 1KB or larger pages */ 748 if ((NewEntry.Mask & 0xFFFF) == 3) { 749 NewEntry.AddrShiftAmount = 12; 750 } else if ((NewEntry.Mask & 0xFFFF) == 0x0000) { 751 NewEntry.AddrShiftAmount = 10; 752 } else if ((NewEntry.Mask & 0xFFFC) == 0x000C) { 753 NewEntry.AddrShiftAmount = 14; 754 } else if ((NewEntry.Mask & 0xFFF0) == 0x0030) { 755 NewEntry.AddrShiftAmount = 16; 756 } else if ((NewEntry.Mask & 0xFFC0) == 0x00C0) { 757 NewEntry.AddrShiftAmount = 18; 758 } else if ((NewEntry.Mask & 0xFF00) == 0x0300) { 759 NewEntry.AddrShiftAmount = 20; 760 } else if ((NewEntry.Mask & 0xFC00) == 0x0C00) { 761 NewEntry.AddrShiftAmount = 22; 762 } else if ((NewEntry.Mask & 0xF000) == 0x3000) { 763 NewEntry.AddrShiftAmount = 24; 764 } else if ((NewEntry.Mask & 0xC000) == 0xC000) { 765 NewEntry.AddrShiftAmount = 26; 766 } else if ((NewEntry.Mask & 0x30000) == 0x30000) { 767 NewEntry.AddrShiftAmount = 28; 768 } else { 769 fatal("Invalid Mask Pattern Detected!\n"); 770 } 771 NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1); 772 773 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 774 Config3Reg config3 = Config3 775 PageGrainReg pageGrain = PageGrain; 776 int SP = 0; 777 if (bits(config3, config3.sp) == 1 && 778 bits(pageGrain, pageGrain.esp) == 1) { 779 SP = 1; 780 } 781 IndexReg index = Index; 782 Ptr->insertAt(NewEntry, Index & 0x7FFFFFFF, SP); 783 }}); 784 0x06: tlbwr({{ 785 //Create PTE 786 MipsISA::PTE NewEntry; 787 //Write PTE 788 NewEntry.Mask = (Addr)(PageMask >> 11); 789 NewEntry.VPN = (Addr)(EntryHi >> 11); 790 /* PageGrain _ ESP Config3 _ SP */ 791 if (((PageGrain >> 28) & 1) == 0 || 792 (( Config3 >> 4) & 1) ==0) { 793 // If 1KB pages are *NOT* enabled, lowest bits of 794 // the mask are 0b11 for TLB writes 795 NewEntry.Mask |= 0x3; 796 // Reset bits 0 and 1 if 1KB pages are not enabled 797 NewEntry.VPN &= 0xFFFFFFFC; 798 } 799 NewEntry.asid = (uint8_t)(EntryHi & 0xFF); 800 801 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); 802 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); 803 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 804 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 805 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 806 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 807 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 808 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 809 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 810 /* Now, compute the AddrShiftAmount and OffsetMask - 811 TLB optimizations */ 812 /* Addr Shift Amount for 1KB or larger pages */ 813 if ((NewEntry.Mask & 0xFFFF) == 3){ 814 NewEntry.AddrShiftAmount = 12; 815 } else if ((NewEntry.Mask & 0xFFFF) == 0x0000) { 816 NewEntry.AddrShiftAmount = 10; 817 } else if ((NewEntry.Mask & 0xFFFC) == 0x000C) { 818 NewEntry.AddrShiftAmount = 14; 819 } else if ((NewEntry.Mask & 0xFFF0) == 0x0030) { 820 NewEntry.AddrShiftAmount = 16; 821 } else if ((NewEntry.Mask & 0xFFC0) == 0x00C0) { 822 NewEntry.AddrShiftAmount = 18; 823 } else if ((NewEntry.Mask & 0xFF00) == 0x0300) { 824 NewEntry.AddrShiftAmount = 20; 825 } else if ((NewEntry.Mask & 0xFC00) == 0x0C00) { 826 NewEntry.AddrShiftAmount = 22; 827 } else if ((NewEntry.Mask & 0xF000) == 0x3000) { 828 NewEntry.AddrShiftAmount = 24; 829 } else if ((NewEntry.Mask & 0xC000) == 0xC000) { 830 NewEntry.AddrShiftAmount = 26; 831 } else if ((NewEntry.Mask & 0x30000) == 0x30000) { 832 NewEntry.AddrShiftAmount = 28; 833 } else { 834 fatal("Invalid Mask Pattern Detected!\n"); 835 } 836 NewEntry.OffsetMask = ((1 << NewEntry.AddrShiftAmount) - 1); 837 838 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 839 Config3Reg config3 = Config3 840 PageGrainReg pageGrain = PageGrain; 841 int SP = 0; 842 if (bits(config3, config3.sp) == 1 && 843 bits(pageGrain, pageGrain.esp) == 1) { 844 SP = 1; 845 } 846 IndexReg index = Index; 847 Ptr->insertAt(NewEntry, Random, SP); 848 }}); 849 850 0x08: tlbp({{ 851 Config3Reg config3 = Config3; 852 PageGrainReg pageGrain = PageGrain; 853 EntryHiReg entryHi = EntryHi; 854 int TLB_Index; 855 Addr VPN; 856 if (pageGrain.esp == 1 && config3.sp ==1) { 857 VPN = EntryHi >> 11; 858 } else { 859 // Mask off lower 2 bits 860 VPN = ((EntryHi >> 11) & 0xFFFFFFFC); 861 } 862 TLB_Index = xc->tcBase()->getITBPtr()-> 863 probeEntry(VPN, entryHi.asid); 864 // Check TLB for entry matching EntryHi 865 if (TLB_Index != -1) { 866 Index = TLB_Index; 867 } else { 868 // else, set Index = 1 << 31 869 Index = (1 << 31); 870 } 871 }}); 872 } 873 format CP0Unimpl { 874 0x20: wait(); 875 } 876 default: CP0Unimpl::unknown(); 877 878 } 879 } 880 881 //Table A-13 MIPS32 COP1 Encoding of rs Field 882 0x1: decode RS_MSB { 883 884 0x0: decode RS_HI { 885 0x0: decode RS_LO { 886 format CP1Control { 887 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 888 889 0x2: cfc1({{ 890 switch (FS) 891 { 892 case 0: 893 Rt = FIR; 894 break; 895 case 25: 896 Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23; 897 break; 898 case 26: 899 Rt = 0 | (FCSR & 0x0003F07C); 900 break; 901 case 28: 902 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003); 903 break; 904 case 31: 905 Rt = FCSR; 906 break; 907 default: 908 warn("FP Control Value (%d) Not Valid"); 909 } 910 // warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt); 911 }}); 912 913 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 914 915 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 916 917 0x6: ctc1({{ 918 switch (FS) 919 { 920 case 25: 921 FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25 922 | (FCSR & 0x01000000) // bit 24 923 | (FCSR & 0x004FFFFF);// bit 22...0 924 break; 925 926 case 26: 927 FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18 928 | Rt.uw<17:12> << 12 // bit 17...12 929 | (FCSR & 0x00000F80) << 7// bit 11...7 930 | Rt.uw<6:2> << 2 // bit 6...2 931 | (FCSR & 0x00000002); // bit 1...0 932 break; 933 934 case 28: 935 FCSR = 0 | (FCSR & 0xFE000000) // move 31...25 936 | Rt.uw<2:2> << 24 // bit 24 937 | (FCSR & 0x00FFF000) << 23// bit 23...12 938 | Rt.uw<11:7> << 7 // bit 24 939 | (FCSR & 0x000007E) 940 | Rt.uw<1:0>;// bit 22...0 941 break; 942 943 case 31: 944 FCSR = Rt.uw; 945 break; 946 947 default: 948 panic("FP Control Value (%d) Not Available. Ignoring Access to" 949 "Floating Control Status Register", FS); 950 } 951 }}); 952 953 0x7: mthc1({{ 954 uint64_t fs_hi = Rt.uw; 955 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 956 Fs.ud = (fs_hi << 32) | fs_lo; 957 }}); 958 959 } 960 format CP1Unimpl { 961 0x1: dmfc1(); 962 0x5: dmtc1(); 963 } 964 } 965 966 0x1: 967 decode RS_LO { 968 0x0: 969 decode ND { 970 format Branch { 971 0x0: decode TF { 972 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 973 }}); 974 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 975 }}); 976 } 977 0x1: decode TF { 978 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 979 }}, Likely); 980 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 981 }}, Likely); 982 } 983 } 984 } 985 format CP1Unimpl { 986 0x1: bc1any2(); 987 0x2: bc1any4(); 988 default: unknown(); 989 } 990 } 991 } 992 993 0x1: decode RS_HI { 994 0x2: decode RS_LO { 995 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 996 //(( single-precision floating point)) 997 0x0: decode FUNCTION_HI { 998 0x0: decode FUNCTION_LO { 999 format FloatOp { 1000 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 1001 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 1002 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 1003 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 1004 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 1005 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 1006 0x7: neg_s({{ Fd.sf = -Fs.sf;}}); 1007 } 1008 1009 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}}); 1010 } 1011 1012 0x1: decode FUNCTION_LO { 1013 format FloatConvertOp { 1014 0x0: round_l_s({{ val = Fs.sf; }}, ToLong, 1015 Round); 1016 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong, 1017 Trunc); 1018 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong, 1019 Ceil); 1020 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong, 1021 Floor); 1022 0x4: round_w_s({{ val = Fs.sf; }}, ToWord, 1023 Round); 1024 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord, 1025 Trunc); 1026 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord, 1027 Ceil); 1028 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord, 1029 Floor); 1030 } 1031 } 1032 1033 0x2: decode FUNCTION_LO { 1034 0x1: decode MOVCF { 1035 format BasicOp { 1036 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }}); 1037 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }}); 1038 } 1039 } 1040 1041 format BasicOp { 1042 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1043 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1044 } 1045 1046 format FloatOp { 1047 0x5: recip_s({{ Fd = 1 / Fs; }}); 1048 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); 1049 } 1050 format CP1Unimpl { 1051 default: unknown(); 1052 } 1053 } 1054 0x3: CP1Unimpl::unknown(); 1055 1056 0x4: decode FUNCTION_LO { 1057 format FloatConvertOp { 1058 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 1059 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 1060 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 1061 } 1062 1063 0x6: FloatOp::cvt_ps_s({{ 1064 Fd.ud = (uint64_t) Fs.uw << 32 | 1065 (uint64_t) Ft.uw; 1066 }}); 1067 format CP1Unimpl { 1068 default: unknown(); 1069 } 1070 } 1071 0x5: CP1Unimpl::unknown(); 1072 1073 0x6: decode FUNCTION_LO { 1074 format FloatCompareOp { 1075 0x0: c_f_s({{ cond = 0; }}, SinglePrecision, 1076 UnorderedFalse); 1077 0x1: c_un_s({{ cond = 0; }}, SinglePrecision, 1078 UnorderedTrue); 1079 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 1080 UnorderedFalse); 1081 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 1082 UnorderedTrue); 1083 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 1084 UnorderedFalse); 1085 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 1086 UnorderedTrue); 1087 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }}, 1088 UnorderedFalse); 1089 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }}, 1090 UnorderedTrue); 1091 } 1092 } 1093 1094 0x7: decode FUNCTION_LO { 1095 format FloatCompareOp { 1096 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1097 UnorderedFalse, QnanException); 1098 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1099 UnorderedTrue, QnanException); 1100 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}}, 1101 UnorderedFalse, QnanException); 1102 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 1103 UnorderedTrue, QnanException); 1104 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 1105 UnorderedFalse, QnanException); 1106 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 1107 UnorderedTrue, QnanException); 1108 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 1109 UnorderedFalse, QnanException); 1110 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 1111 UnorderedTrue, QnanException); 1112 } 1113 } 1114 } 1115 1116 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 1117 0x1: decode FUNCTION_HI { 1118 0x0: decode FUNCTION_LO { 1119 format FloatOp { 1120 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 1121 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 1122 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 1123 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); 1124 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 1125 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 1126 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); 1127 } 1128 1129 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); 1130 } 1131 1132 0x1: decode FUNCTION_LO { 1133 format FloatConvertOp { 1134 0x0: round_l_d({{ val = Fs.df; }}, ToLong, 1135 Round); 1136 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong, 1137 Trunc); 1138 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong, 1139 Ceil); 1140 0x3: floor_l_d({{ val = Fs.df; }}, ToLong, 1141 Floor); 1142 0x4: round_w_d({{ val = Fs.df; }}, ToWord, 1143 Round); 1144 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord, 1145 Trunc); 1146 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord, 1147 Ceil); 1148 0x7: floor_w_d({{ val = Fs.df; }}, ToWord, 1149 Floor); 1150 } 1151 } 1152 1153 0x2: decode FUNCTION_LO { 1154 0x1: decode MOVCF { 1155 format BasicOp { 1156 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ? 1157 Fs.df : Fd.df; 1158 }}); 1159 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ? 1160 Fs.df : Fd.df; 1161 }}); 1162 } 1163 } 1164 1165 format BasicOp { 1166 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }}); 1167 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }}); 1168 } 1169 1170 format FloatOp { 1171 0x5: recip_d({{ Fd.df = 1 / Fs.df }}); 1172 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }}); 1173 } 1174 format CP1Unimpl { 1175 default: unknown(); 1176 } 1177 1178 } 1179 0x4: decode FUNCTION_LO { 1180 format FloatConvertOp { 1181 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 1182 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 1183 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 1184 } 1185 default: CP1Unimpl::unknown(); 1186 } 1187 1188 0x6: decode FUNCTION_LO { 1189 format FloatCompareOp { 1190 0x0: c_f_d({{ cond = 0; }}, DoublePrecision, 1191 UnorderedFalse); 1192 0x1: c_un_d({{ cond = 0; }}, DoublePrecision, 1193 UnorderedTrue); 1194 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 1195 UnorderedFalse); 1196 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 1197 UnorderedTrue); 1198 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 1199 UnorderedFalse); 1200 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 1201 UnorderedTrue); 1202 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }}, 1203 UnorderedFalse); 1204 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }}, 1205 UnorderedTrue); 1206 } 1207 } 1208 1209 0x7: decode FUNCTION_LO { 1210 format FloatCompareOp { 1211 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1212 UnorderedFalse, QnanException); 1213 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1214 UnorderedTrue, QnanException); 1215 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }}, 1216 UnorderedFalse, QnanException); 1217 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }}, 1218 UnorderedTrue, QnanException); 1219 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }}, 1220 UnorderedFalse, QnanException); 1221 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 1222 UnorderedTrue, QnanException); 1223 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 1224 UnorderedFalse, QnanException); 1225 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 1226 UnorderedTrue, QnanException); 1227 } 1228 } 1229 default: CP1Unimpl::unknown(); 1230 } 1231 0x2: CP1Unimpl::unknown(); 1232 0x3: CP1Unimpl::unknown(); 1233 0x7: CP1Unimpl::unknown(); 1234 1235 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 1236 0x4: decode FUNCTION { 1237 format FloatConvertOp { 1238 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 1239 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 1240 0x26: CP1Unimpl::cvt_ps_w(); 1241 } 1242 default: CP1Unimpl::unknown(); 1243 } 1244 1245 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 1246 //Note: "1. Format type L is legal only if 64-bit floating point operations 1247 //are enabled." 1248 0x5: decode FUNCTION_HI { 1249 format FloatConvertOp { 1250 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 1251 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 1252 0x26: CP1Unimpl::cvt_ps_l(); 1253 } 1254 default: CP1Unimpl::unknown(); 1255 } 1256 1257 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 1258 //Note: "1. Format type PS is legal only if 64-bit floating point operations 1259 //are enabled. " 1260 0x6: decode FUNCTION_HI { 1261 0x0: decode FUNCTION_LO { 1262 format Float64Op { 1263 0x0: add_ps({{ 1264 Fd1.sf = Fs1.sf + Ft2.sf; 1265 Fd2.sf = Fs2.sf + Ft2.sf; 1266 }}); 1267 0x1: sub_ps({{ 1268 Fd1.sf = Fs1.sf - Ft2.sf; 1269 Fd2.sf = Fs2.sf - Ft2.sf; 1270 }}); 1271 0x2: mul_ps({{ 1272 Fd1.sf = Fs1.sf * Ft2.sf; 1273 Fd2.sf = Fs2.sf * Ft2.sf; 1274 }}); 1275 0x5: abs_ps({{ 1276 Fd1.sf = fabs(Fs1.sf); 1277 Fd2.sf = fabs(Fs2.sf); 1278 }}); 1279 0x6: mov_ps({{ 1280 Fd1.sf = Fs1.sf; 1281 Fd2.sf = Fs2.sf; 1282 }}); 1283 0x7: neg_ps({{ 1284 Fd1.sf = -(Fs1.sf); 1285 Fd2.sf = -(Fs2.sf); 1286 }}); 1287 default: CP1Unimpl::unknown(); 1288 } 1289 } 1290 0x1: CP1Unimpl::unknown(); 1291 0x2: decode FUNCTION_LO { 1292 0x1: decode MOVCF { 1293 format Float64Op { 1294 0x0: movf_ps({{ 1295 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1296 Fs1 : Fd1; 1297 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1298 Fs2 : Fd2; 1299 }}); 1300 0x1: movt_ps({{ 1301 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1302 Fs1 : Fd1; 1303 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1304 Fs2 : Fd2; 1305 }}); 1306 } 1307 } 1308 1309 format Float64Op { 1310 0x2: movz_ps({{ 1311 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1312 Fs1 : Fd1; 1313 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1314 Fs2 : Fd2; 1315 }}); 1316 0x3: movn_ps({{ 1317 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1318 Fs1 : Fd1; 1319 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1320 Fs2 : Fd2; 1321 }}); 1322 } 1323 default: CP1Unimpl::unknown(); 1324 1325 } 1326 0x3: CP1Unimpl::unknown(); 1327 0x4: decode FUNCTION_LO { 1328 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 1329 default: CP1Unimpl::unknown(); 1330 } 1331 1332 0x5: decode FUNCTION_LO { 1333 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); 1334 1335 format Float64Op { 1336 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 1337 Ft1.uw; 1338 }}); 1339 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 1340 Ft2.uw; 1341 }}); 1342 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 1343 Ft1.uw; 1344 }}); 1345 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 1346 Ft2.uw; 1347 }}); 1348 } 1349 default: CP1Unimpl::unknown(); 1350 } 1351 1352 0x6: decode FUNCTION_LO { 1353 format FloatPSCompareOp { 1354 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1355 UnorderedFalse); 1356 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1357 UnorderedTrue); 1358 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1359 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1360 UnorderedFalse); 1361 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1362 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1363 UnorderedTrue); 1364 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1365 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1366 UnorderedFalse); 1367 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }}, 1368 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1369 UnorderedTrue); 1370 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }}, 1371 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1372 UnorderedFalse); 1373 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1374 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1375 UnorderedTrue); 1376 } 1377 } 1378 1379 0x7: decode FUNCTION_LO { 1380 format FloatPSCompareOp { 1381 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1382 UnorderedFalse, QnanException); 1383 0x1: c_ngle_ps({{ cond1 = 0; }}, 1384 {{ cond2 = 0; }}, 1385 UnorderedTrue, QnanException); 1386 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1387 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1388 UnorderedFalse, QnanException); 1389 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1390 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1391 UnorderedTrue, QnanException); 1392 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1393 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1394 UnorderedFalse, QnanException); 1395 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1396 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1397 UnorderedTrue, QnanException); 1398 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1399 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1400 UnorderedFalse, QnanException); 1401 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1402 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1403 UnorderedTrue, QnanException); 1404 } 1405 } 1406 } 1407 } 1408 default: CP1Unimpl::unknown(); 1409 } 1410 } 1411 1412 //Table A-19 MIPS32 COP2 Encoding of rs Field 1413 0x2: decode RS_MSB { 1414 format CP2Unimpl { 1415 0x0: decode RS_HI { 1416 0x0: decode RS_LO { 1417 0x0: mfc2(); 1418 0x2: cfc2(); 1419 0x3: mfhc2(); 1420 0x4: mtc2(); 1421 0x6: ctc2(); 1422 0x7: mftc2(); 1423 default: unknown(); 1424 } 1425 1426 0x1: decode ND { 1427 0x0: decode TF { 1428 0x0: bc2f(); 1429 0x1: bc2t(); 1430 default: unknown(); 1431 } 1432 1433 0x1: decode TF { 1434 0x0: bc2fl(); 1435 0x1: bc2tl(); 1436 default: unknown(); 1437 } 1438 default: unknown(); 1439 1440 } 1441 default: unknown(); 1442 1443 } 1444 default: unknown(); 1445 } 1446 } 1447 1448 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1449 //Note: "COP1X instructions are legal only if 64-bit floating point 1450 //operations are enabled." 1451 0x3: decode FUNCTION_HI { 1452 0x0: decode FUNCTION_LO { 1453 format LoadIndexedMemory { 1454 0x0: lwxc1({{ Fd.uw = Mem.uw;}}); 1455 0x1: ldxc1({{ Fd.ud = Mem.ud;}}); 1456 0x5: luxc1({{ Fd.ud = Mem.ud;}}, 1457 {{ EA = (Rs + Rt) & ~7; }}); 1458 } 1459 } 1460 1461 0x1: decode FUNCTION_LO { 1462 format StoreIndexedMemory { 1463 0x0: swxc1({{ Mem.uw = Fs.uw;}}); 1464 0x1: sdxc1({{ Mem.ud = Fs.ud;}}); 1465 0x5: suxc1({{ Mem.ud = Fs.ud;}}, 1466 {{ EA = (Rs + Rt) & ~7; }}); 1467 } 1468 1469 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1470 } 1471 1472 0x3: decode FUNCTION_LO { 1473 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) { 1474 Fd.ud = Fs.ud; 1475 } else if (Rs<2:0> == 4) { 1476 #if BYTE_ORDER == BIG_ENDIAN 1477 Fd.ud = Fs.ud<31:0> << 32 | 1478 Ft.ud<63:32>; 1479 #elif BYTE_ORDER == LITTLE_ENDIAN 1480 Fd.ud = Ft.ud<31:0> << 32 | 1481 Fs.ud<63:32>; 1482 #endif 1483 } else { 1484 Fd.ud = Fd.ud; 1485 } 1486 }}); 1487 } 1488 1489 format FloatAccOp { 1490 0x4: decode FUNCTION_LO { 1491 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 1492 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 1493 0x6: madd_ps({{ 1494 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; 1495 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; 1496 }}); 1497 } 1498 1499 0x5: decode FUNCTION_LO { 1500 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); 1501 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 1502 0x6: msub_ps({{ 1503 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; 1504 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; 1505 }}); 1506 } 1507 1508 0x6: decode FUNCTION_LO { 1509 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1510 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 1511 0x6: nmadd_ps({{ 1512 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df); 1513 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df); 1514 }}); 1515 } 1516 1517 0x7: decode FUNCTION_LO { 1518 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1519 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 1520 0x6: nmsub_ps({{ 1521 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 1522 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 1523 }}); 1524 } 1525 1526 } 1527 } 1528 1529 format Branch { 1530 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 1531 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 1532 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 1533 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 1534 } 1535 } 1536 1537 0x3: decode OPCODE_LO { 1538 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1539 0x4: decode FUNCTION_HI { 1540 0x0: decode FUNCTION_LO { 1541 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd; 1542 Rd.sw = temp1<31:0>; 1543 }}, IntMultOp); 1544 1545 format HiLoRdSelValOp { 1546 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}, IntMultOp); 1547 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}, IntMultOp); 1548 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}, IntMultOp); 1549 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}, IntMultOp); 1550 } 1551 } 1552 1553 0x4: decode FUNCTION_LO { 1554 format BasicOp { 1555 0x0: clz({{ int cnt = 32; 1556 for (int idx = 31; idx >= 0; idx--) { 1557 if( Rs<idx:idx> == 1) { 1558 cnt = 31 - idx; 1559 break; 1560 } 1561 } 1562 Rd.uw = cnt; 1563 }}); 1564 0x1: clo({{ int cnt = 32; 1565 for (int idx = 31; idx >= 0; idx--) { 1566 if( Rs<idx:idx> == 0) { 1567 cnt = 31 - idx; 1568 break; 1569 } 1570 } 1571 Rd.uw = cnt; 1572 }}); 1573 } 1574 } 1575 1576 0x7: decode FUNCTION_LO { 1577 0x7: FailUnimpl::sdbbp(); 1578 } 1579 } 1580 1581 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1582 //of the Architecture 1583 0x7: decode FUNCTION_HI { 1584 0x0: decode FUNCTION_LO { 1585 format BasicOp { 1586 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); 1587 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 1588 bits(Rs.uw, MSB-LSB, 0) << LSB | 1589 bits(Rt.uw, LSB-1, 0); 1590 }}); 1591 } 1592 } 1593 1594 0x1: decode FUNCTION_LO { 1595 format MT_Control { 1596 0x0: fork({{ forkThread(xc->tcBase(), fault, RD, Rs, Rt); }}, 1597 UserMode); 1598 0x1: yield({{ Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, YQMask); }}, 1599 UserMode); 1600 } 1601 1602 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1603 0x2: decode OP_HI { 1604 0x0: decode OP_LO { 1605 format LoadIndexedMemory { 1606 0x0: lwx({{ Rd.sw = Mem.sw; }}); 1607 0x4: lhx({{ Rd.sw = Mem.sh; }}); 1608 0x6: lbux({{ Rd.uw = Mem.ub; }}); 1609 } 1610 } 1611 } 1612 0x4: DspIntOp::insv({{ int pos = dspctl<5:0>; 1613 int size = dspctl<12:7>-1; 1614 Rt.uw = insertBits( Rt.uw, pos+size, pos, Rs.uw<size:0> ); }}); 1615 } 1616 1617 0x2: decode FUNCTION_LO { 1618 1619 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field (DSP ASE MANUAL) 1620 0x0: decode OP_HI { 1621 0x0: decode OP_LO { 1622 format DspIntOp { 1623 0x0: addu_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1624 NOSATURATE, UNSIGNED, &dspctl ); }}); 1625 0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, 1626 NOSATURATE, UNSIGNED, &dspctl ); }}); 1627 0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1628 SATURATE, UNSIGNED, &dspctl ); }}); 1629 0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, 1630 SATURATE, UNSIGNED, &dspctl ); }}); 1631 0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, 1632 MODE_L, &dspctl ); }}, IntMultOp); 1633 0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, 1634 MODE_R, &dspctl ); }}, IntMultOp); 1635 } 1636 } 1637 0x1: decode OP_LO { 1638 format DspIntOp { 1639 0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1640 NOSATURATE, UNSIGNED, &dspctl ); }}); 1641 0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1642 NOSATURATE, UNSIGNED, &dspctl ); }}); 1643 0x2: addq_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1644 NOSATURATE, SIGNED, &dspctl ); }}); 1645 0x3: subq_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1646 NOSATURATE, SIGNED, &dspctl ); }}); 1647 0x4: addu_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1648 SATURATE, UNSIGNED, &dspctl ); }}); 1649 0x5: subu_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1650 SATURATE, UNSIGNED, &dspctl ); }}); 1651 0x6: addq_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1652 SATURATE, SIGNED, &dspctl ); }}); 1653 0x7: subq_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1654 SATURATE, SIGNED, &dspctl ); }}); 1655 } 1656 } 1657 0x2: decode OP_LO { 1658 format DspIntOp { 1659 0x0: addsc({{ int64_t dresult; 1660 dresult = Rs.ud + Rt.ud; 1661 Rd.sw = dresult<31:0>; 1662 dspctl = insertBits( dspctl, 13, 13, 1663 dresult<32:32> ); }}); 1664 0x1: addwc({{ int64_t dresult; 1665 dresult = Rs.sd + Rt.sd + dspctl<13:13>; 1666 Rd.sw = dresult<31:0>; 1667 if( dresult<32:32> != dresult<31:31> ) 1668 dspctl = insertBits( dspctl, 20, 20, 1 ); }}); 1669 0x2: modsub({{ Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : Rs.sw - Rt.sw<7:0>; }}); 1670 0x4: raddu_w_qb({{ Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + 1671 Rs.uw<15:8> + Rs.uw<7:0>; }}); 1672 0x6: addq_s_w({{ Rd.sw = dspAdd( Rs.sw, Rt.sw, SIMD_FMT_W, 1673 SATURATE, SIGNED, &dspctl ); }}); 1674 0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W, 1675 SATURATE, SIGNED, &dspctl ); }}); 1676 } 1677 } 1678 0x3: decode OP_LO { 1679 format DspIntOp { 1680 0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, 1681 MODE_L, &dspctl ); }}, IntMultOp); 1682 0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, 1683 MODE_R, &dspctl ); }}, IntMultOp); 1684 0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, 1685 SATURATE, NOROUND, &dspctl ); }}, IntMultOp); 1686 0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, 1687 SATURATE, ROUND, &dspctl ); }}, IntMultOp); 1688 } 1689 } 1690 } 1691 1692 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL) 1693 0x1: decode OP_HI { 1694 0x0: decode OP_LO { 1695 format DspIntOp { 1696 0x0: cmpu_eq_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1697 UNSIGNED, CMP_EQ, &dspctl ); }}); 1698 0x1: cmpu_lt_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1699 UNSIGNED, CMP_LT, &dspctl ); }}); 1700 0x2: cmpu_le_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1701 UNSIGNED, CMP_LE, &dspctl ); }}); 1702 0x3: pick_qb({{ Rd.uw = dspPick( Rs.uw, Rt.uw, 1703 SIMD_FMT_QB, &dspctl ); }}); 1704 0x4: cmpgu_eq_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1705 UNSIGNED, CMP_EQ ); }}); 1706 0x5: cmpgu_lt_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1707 UNSIGNED, CMP_LT ); }}); 1708 0x6: cmpgu_le_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1709 UNSIGNED, CMP_LE ); }}); 1710 } 1711 } 1712 0x1: decode OP_LO { 1713 format DspIntOp { 1714 0x0: cmp_eq_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1715 SIGNED, CMP_EQ, &dspctl ); }}); 1716 0x1: cmp_lt_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1717 SIGNED, CMP_LT, &dspctl ); }}); 1718 0x2: cmp_le_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1719 SIGNED, CMP_LE, &dspctl ); }}); 1720 0x3: pick_ph({{ Rd.uw = dspPick( Rs.uw, Rt.uw, 1721 SIMD_FMT_PH, &dspctl ); }}); 1722 0x4: precrq_qb_ph({{ Rd.uw = Rs.uw<31:24> << 24 | 1723 Rs.uw<15:8> << 16 | 1724 Rt.uw<31:24> << 8 | 1725 Rt.uw<15:8>; }}); 1726 0x5: precr_qb_ph({{ Rd.uw = Rs.uw<23:16> << 24 | 1727 Rs.uw<7:0> << 16 | 1728 Rt.uw<23:16> << 8 | 1729 Rt.uw<7:0>; }}); 1730 0x6: packrl_ph({{ Rd.uw = dspPack( Rs.uw, Rt.uw, 1731 SIMD_FMT_PH ); }}); 1732 0x7: precrqu_s_qb_ph({{ Rd.uw = dspPrecrqu( Rs.uw, Rt.uw, &dspctl ); }}); 1733 } 1734 } 1735 0x2: decode OP_LO { 1736 format DspIntOp { 1737 0x4: precrq_ph_w({{ Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; }}); 1738 0x5: precrq_rs_ph_w({{ Rd.uw = dspPrecrq( Rs.uw, Rt.uw, SIMD_FMT_W, &dspctl ); }}); 1739 } 1740 } 1741 0x3: decode OP_LO { 1742 format DspIntOp { 1743 0x0: cmpgdu_eq_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1744 UNSIGNED, CMP_EQ, &dspctl ); }}); 1745 0x1: cmpgdu_lt_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1746 UNSIGNED, CMP_LT, &dspctl ); }}); 1747 0x2: cmpgdu_le_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1748 UNSIGNED, CMP_LE, &dspctl ); }}); 1749 0x6: precr_sra_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, 1750 SIMD_FMT_W, NOROUND ); }}); 1751 0x7: precr_sra_r_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, 1752 SIMD_FMT_W, ROUND ); }}); 1753 } 1754 } 1755 } 1756 1757 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field (DSP ASE MANUAL) 1758 0x2: decode OP_HI { 1759 0x0: decode OP_LO { 1760 format DspIntOp { 1761 0x1: absq_s_qb({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_QB, &dspctl );}}); 1762 0x2: repl_qb({{ Rd.uw = RS_RT<7:0> << 24 | 1763 RS_RT<7:0> << 16 | 1764 RS_RT<7:0> << 8 | 1765 RS_RT<7:0>; }}); 1766 0x3: replv_qb({{ Rd.sw = Rt.uw<7:0> << 24 | 1767 Rt.uw<7:0> << 16 | 1768 Rt.uw<7:0> << 8 | 1769 Rt.uw<7:0>; }}); 1770 0x4: precequ_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1771 SIMD_FMT_PH, SIGNED, MODE_L ); }}); 1772 0x5: precequ_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1773 SIMD_FMT_PH, SIGNED, MODE_R ); }}); 1774 0x6: precequ_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1775 SIMD_FMT_PH, SIGNED, MODE_LA ); }}); 1776 0x7: precequ_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1777 SIMD_FMT_PH, SIGNED, MODE_RA ); }}); 1778 } 1779 } 1780 0x1: decode OP_LO { 1781 format DspIntOp { 1782 0x1: absq_s_ph({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_PH, &dspctl ); }}); 1783 0x2: repl_ph({{ Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | 1784 (sext<10>(RS_RT))<15:0>; }}); 1785 0x3: replv_ph({{ Rd.uw = Rt.uw<15:0> << 16 | 1786 Rt.uw<15:0>; }}); 1787 0x4: preceq_w_phl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, 1788 SIMD_FMT_W, SIGNED, MODE_L ); }}); 1789 0x5: preceq_w_phr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, 1790 SIMD_FMT_W, SIGNED, MODE_R ); }}); 1791 } 1792 } 1793 0x2: decode OP_LO { 1794 format DspIntOp { 1795 0x1: absq_s_w({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_W, &dspctl ); }}); 1796 } 1797 } 1798 0x3: decode OP_LO { 1799 0x3: IntOp::bitrev({{ Rd.uw = bitrev( Rt.uw<15:0> ); }}); 1800 format DspIntOp { 1801 0x4: preceu_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1802 SIMD_FMT_PH, UNSIGNED, MODE_L ); }}); 1803 0x5: preceu_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1804 SIMD_FMT_PH, UNSIGNED, MODE_R ); }}); 1805 0x6: preceu_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1806 SIMD_FMT_PH, UNSIGNED, MODE_LA ); }}); 1807 0x7: preceu_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1808 SIMD_FMT_PH, UNSIGNED, MODE_RA ); }}); 1809 } 1810 } 1811 } 1812 1813 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field (DSP ASE MANUAL) 1814 0x3: decode OP_HI { 1815 0x0: decode OP_LO { 1816 format DspIntOp { 1817 0x0: shll_qb({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_QB, 1818 NOSATURATE, UNSIGNED, &dspctl ); }}); 1819 0x1: shrl_qb({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_QB, 1820 UNSIGNED ); }}); 1821 0x2: shllv_qb({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_QB, 1822 NOSATURATE, UNSIGNED, &dspctl ); }}); 1823 0x3: shrlv_qb({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_QB, 1824 UNSIGNED ); }}); 1825 0x4: shra_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, 1826 NOROUND, SIGNED, &dspctl ); }}); 1827 0x5: shra_r_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, 1828 ROUND, SIGNED, &dspctl ); }}); 1829 0x6: shrav_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, 1830 NOROUND, SIGNED, &dspctl ); }}); 1831 0x7: shrav_r_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, 1832 ROUND, SIGNED, &dspctl ); }}); 1833 } 1834 } 1835 0x1: decode OP_LO { 1836 format DspIntOp { 1837 0x0: shll_ph({{ Rd.uw = dspShll( Rt.uw, RS, SIMD_FMT_PH, 1838 NOSATURATE, SIGNED, &dspctl ); }}); 1839 0x1: shra_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, 1840 NOROUND, SIGNED, &dspctl ); }}); 1841 0x2: shllv_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, 1842 NOSATURATE, SIGNED, &dspctl ); }}); 1843 0x3: shrav_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, 1844 NOROUND, SIGNED, &dspctl ); }}); 1845 0x4: shll_s_ph({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_PH, 1846 SATURATE, SIGNED, &dspctl ); }}); 1847 0x5: shra_r_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, 1848 ROUND, SIGNED, &dspctl ); }}); 1849 0x6: shllv_s_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, 1850 SATURATE, SIGNED, &dspctl ); }}); 1851 0x7: shrav_r_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, 1852 ROUND, SIGNED, &dspctl ); }}); 1853 } 1854 } 1855 0x2: decode OP_LO { 1856 format DspIntOp { 1857 0x4: shll_s_w({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_W, 1858 SATURATE, SIGNED, &dspctl ); }}); 1859 0x5: shra_r_w({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_W, 1860 ROUND, SIGNED, &dspctl ); }}); 1861 0x6: shllv_s_w({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_W, 1862 SATURATE, SIGNED, &dspctl ); }}); 1863 0x7: shrav_r_w({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_W, 1864 ROUND, SIGNED, &dspctl ); }}); 1865 } 1866 } 1867 0x3: decode OP_LO { 1868 format DspIntOp { 1869 0x1: shrl_ph({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_PH, 1870 UNSIGNED ); }}); 1871 0x3: shrlv_ph({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_PH, 1872 UNSIGNED ); }}); 1873 } 1874 } 1875 } 1876 } 1877 1878 0x3: decode FUNCTION_LO { 1879 1880 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field (DSP ASE Rev2 Manual) 1881 0x0: decode OP_HI { 1882 0x0: decode OP_LO { 1883 format DspIntOp { 1884 0x0: adduh_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1885 NOROUND, UNSIGNED ); }}); 1886 0x1: subuh_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1887 NOROUND, UNSIGNED ); }}); 1888 0x2: adduh_r_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1889 ROUND, UNSIGNED ); }}); 1890 0x3: subuh_r_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1891 ROUND, UNSIGNED ); }}); 1892 } 1893 } 1894 0x1: decode OP_LO { 1895 format DspIntOp { 1896 0x0: addqh_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1897 NOROUND, SIGNED ); }}); 1898 0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1899 NOROUND, SIGNED ); }}); 1900 0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1901 ROUND, SIGNED ); }}); 1902 0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1903 ROUND, SIGNED ); }}); 1904 0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, 1905 NOSATURATE, &dspctl ); }}, IntMultOp); 1906 0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, 1907 SATURATE, &dspctl ); }}, IntMultOp); 1908 1909 } 1910 } 1911 0x2: decode OP_LO { 1912 format DspIntOp { 1913 0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, 1914 NOROUND, SIGNED ); }}); 1915 0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, 1916 NOROUND, SIGNED ); }}); 1917 0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, 1918 ROUND, SIGNED ); }}); 1919 0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, 1920 ROUND, SIGNED ); }}); 1921 0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, 1922 SATURATE, NOROUND, &dspctl ); }}, IntMultOp); 1923 0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, 1924 SATURATE, ROUND, &dspctl ); }}, IntMultOp); 1925 } 1926 } 1927 } 1928 } 1929 1930 //Table A-10 MIPS32 BSHFL Encoding of sa Field 1931 0x4: decode SA { 1932 format BasicOp { 1933 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 | 1934 Rt.uw<31:24> << 16 | 1935 Rt.uw<7:0> << 8 | 1936 Rt.uw<15:8>; 1937 }}); 1938 0x10: seb({{ Rd.sw = Rt.sb; }}); 1939 0x18: seh({{ Rd.sw = Rt.sh; }}); 1940 } 1941 } 1942 1943 0x6: decode FUNCTION_LO { 1944 1945 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL) 1946 0x0: decode OP_HI { 1947 0x0: decode OP_LO { 1948 format DspHiLoOp { 1949 0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1950 SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); 1951 0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1952 SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); 1953 0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw, 1954 ACDST, SIMD_FMT_PH ); }}, IntMultOp); 1955 0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1956 SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); 1957 0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1958 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1959 0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1960 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1961 0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw, 1962 ACDST, SIMD_FMT_PH, &dspctl ); }}, IntMultOp); 1963 0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1964 SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); 1965 } 1966 } 1967 0x1: decode OP_LO { 1968 format DspHiLoOp { 1969 0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1970 SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); 1971 0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1972 SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); 1973 0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1974 SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); 1975 0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, 1976 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1977 0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, 1978 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1979 0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1980 SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); 1981 } 1982 } 1983 0x2: decode OP_LO { 1984 format DspHiLoOp { 1985 0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1986 MODE_L, SATURATE, &dspctl ); }}, IntMultOp); 1987 0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1988 MODE_R, SATURATE, &dspctl ); }}, IntMultOp); 1989 0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1990 MODE_L, NOSATURATE, &dspctl ); }}, IntMultOp); 1991 0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1992 MODE_R, NOSATURATE, &dspctl ); }}, IntMultOp); 1993 } 1994 } 1995 0x3: decode OP_LO { 1996 format DspHiLoOp { 1997 0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1998 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); 1999 0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 2000 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); 2001 0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 2002 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); 2003 0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 2004 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); 2005 } 2006 } 2007 } 2008 2009 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2010 0x1: decode OP_HI { 2011 0x0: decode OP_LO { 2012 format IntOp { 2013 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }}); 2014 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw, RD - 1, 0) << (32 - RD)); }}); 2015 } 2016 } 2017 0x2: decode OP_LO { 2018 format IntOp { 2019 0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }}); 2020 } 2021 } 2022 } 2023 2024 } 2025 0x7: decode FUNCTION_LO { 2026 2027 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL) 2028 0x0: decode OP_HI { 2029 0x0: decode OP_LO { 2030 format DspHiLoOp { 2031 0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 2032 NOROUND, NOSATURATE, &dspctl ); }}); 2033 0x1: extrv_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 2034 NOROUND, NOSATURATE, &dspctl ); }}); 2035 0x2: extp({{ Rt.uw = dspExtp( dspac, RS, &dspctl ); }}); 2036 0x3: extpv({{ Rt.uw = dspExtp( dspac, Rs.uw, &dspctl ); }}); 2037 0x4: extr_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 2038 ROUND, NOSATURATE, &dspctl ); }}); 2039 0x5: extrv_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 2040 ROUND, NOSATURATE, &dspctl ); }}); 2041 0x6: extr_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 2042 ROUND, SATURATE, &dspctl ); }}); 2043 0x7: extrv_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 2044 ROUND, SATURATE, &dspctl ); }}); 2045 } 2046 } 2047 0x1: decode OP_LO { 2048 format DspHiLoOp { 2049 0x2: extpdp({{ Rt.uw = dspExtpd( dspac, RS, &dspctl ); }}); 2050 0x3: extpdpv({{ Rt.uw = dspExtpd( dspac, Rs.uw, &dspctl ); }}); 2051 0x6: extr_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, RS, 2052 NOROUND, SATURATE, &dspctl ); }}); 2053 0x7: extrv_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, Rs.uw, 2054 NOROUND, SATURATE, &dspctl ); }}); 2055 } 2056 } 2057 0x2: decode OP_LO { 2058 format DspIntOp { 2059 0x2: rddsp({{ Rd.uw = readDSPControl( &dspctl, RDDSPMASK ); }}); 2060 0x3: wrdsp({{ writeDSPControl( &dspctl, Rs.uw, WRDSPMASK ); }}); 2061 } 2062 } 2063 0x3: decode OP_LO { 2064 format DspHiLoOp { 2065 0x2: shilo({{ if( sext<6>(HILOSA) < 0 ) 2066 dspac = (uint64_t)dspac << -sext<6>(HILOSA); 2067 else 2068 dspac = (uint64_t)dspac >> sext<6>(HILOSA); }}); 2069 0x3: shilov({{ if( sext<6>(Rs.sw<5:0>) < 0 ) 2070 dspac = (uint64_t)dspac << -sext<6>(Rs.sw<5:0>); 2071 else 2072 dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }}); 2073 0x7: mthlip({{ dspac = dspac << 32; 2074 dspac |= Rs.uw; 2075 dspctl = insertBits( dspctl, 5, 0, 2076 dspctl<5:0>+32 ); }}); 2077 } 2078 } 2079 } 2080 0x3: decode OP_HI { 2081 0x2: decode OP_LO { 2082 0x3: FailUnimpl::rdhwr(); 2083 } 2084 } 2085 } 2086 } 2087 } 2088 2089 0x4: decode OPCODE_LO { 2090 format LoadMemory { 2091 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT); 2092 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 2093 0x3: lw({{ Rt.sw = Mem.sw; }}); 2094 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT); 2095 0x5: lhu({{ Rt.uw = Mem.uh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 2096 } 2097 2098 format LoadUnalignedMemory { 2099 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset); 2100 Rt.uw = mem_word << mem_shift | 2101 (Rt.uw & mask(mem_shift)); 2102 }}); 2103 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset; 2104 Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) | 2105 (mem_word >> mem_shift); 2106 }}); 2107 } 2108 } 2109 2110 0x5: decode OPCODE_LO { 2111 format StoreMemory { 2112 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT); 2113 0x1: sh({{ Mem.uh = Rt<15:0>; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 2114 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 2115 } 2116 2117 format StoreUnalignedMemory { 2118 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset); 2119 uint32_t mem_shift = 32 - reg_shift; 2120 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2121 (Rt.uw >> reg_shift); 2122 }}); 2123 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset; 2124 mem_word = Rt.uw << reg_shift | 2125 (mem_word & (mask(reg_shift))); 2126 }}); 2127 } 2128 format CP0Control { 2129 0x7: cache({{ 2130 //Addr CacheEA = Rs.uw + OFFSET; 2131 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2132 }}); 2133 } 2134 } 2135 2136 0x6: decode OPCODE_LO { 2137 format LoadMemory { 2138 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LLSC); 2139 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 2140 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 2141 } 2142 0x2: CP2Unimpl::lwc2(); 2143 0x6: CP2Unimpl::ldc2(); 2144 0x3: Prefetch::pref(); 2145 } 2146 2147 2148 0x7: decode OPCODE_LO { 2149 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, 2150 {{ uint64_t tmp = write_result; 2151 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; 2152 }}, mem_flags=LLSC, inst_flags = IsStoreConditional); 2153 2154 format StoreMemory { 2155 0x1: swc1({{ Mem.uw = Ft.uw;}}); 2156 0x5: sdc1({{ Mem.ud = Ft.ud;}}); 2157 } 2158 2159 0x2: CP2Unimpl::swc2(); 2160 0x6: CP2Unimpl::sdc2(); 2161 2162 } 2163} 2164 2165 2166