decoder.isa revision 6076:e141cc7896ce
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30// Brett Miller 31// Jaidev Patwardhan 32 33//////////////////////////////////////////////////////////////////// 34// 35// The actual MIPS32 ISA decoder 36// ----------------------------- 37// The following instructions are specified in the MIPS32 ISA 38// Specification. Decoding closely follows the style specified 39// in the MIPS32 ISA specification document starting with Table 40// A-2 (document available @ http://www.mips.com) 41// 42decode OPCODE_HI default Unknown::unknown() { 43 //Table A-2 44 0x0: decode OPCODE_LO { 45 0x0: decode FUNCTION_HI { 46 0x0: decode FUNCTION_LO { 47 0x1: decode MOVCI { 48 format BasicOp { 49 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }}); 50 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }}); 51 } 52 } 53 54 format BasicOp { 55 //Table A-3 Note: "Specific encodings of the rd, rs, and 56 //rt fields are used to distinguish SLL, SSNOP, and EHB 57 //functions 58 0x0: decode RS { 59 0x0: decode RT_RD { 60 0x0: decode SA default Nop::nop() { 61 0x1: ssnop({{;}}); 62 0x3: ehb({{;}}); 63 } 64 default: sll({{ Rd = Rt.uw << SA; }}); 65 } 66 } 67 68 0x2: decode RS_SRL { 69 0x0:decode SRL { 70 0: srl({{ Rd = Rt.uw >> SA; }}); 71 72 //Hardcoded assuming 32-bit ISA, probably need parameter here 73 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 74 } 75 } 76 77 0x3: decode RS { 78 0x0: sra({{ 79 uint32_t temp = Rt >> SA; 80 if ( (Rt & 0x80000000) > 0 ) { 81 uint32_t mask = 0x80000000; 82 for(int i=0; i < SA; i++) { 83 temp |= mask; 84 mask = mask >> 1; 85 } 86 } 87 Rd = temp; 88 }}); 89 } 90 91 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 92 93 0x6: decode SRLV { 94 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 95 96 //Hardcoded assuming 32-bit ISA, probably need parameter here 97 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 98 } 99 100 0x7: srav({{ 101 int shift_amt = Rs<4:0>; 102 103 uint32_t temp = Rt >> shift_amt; 104 105 if ( (Rt & 0x80000000) > 0 ) { 106 uint32_t mask = 0x80000000; 107 for(int i=0; i < shift_amt; i++) { 108 temp |= mask; 109 mask = mask >> 1; 110 } 111 } 112 113 Rd = temp; 114 }}); 115 } 116 } 117 118 0x1: decode FUNCTION_LO { 119 //Table A-3 Note: "Specific encodings of the hint field are 120 //used to distinguish JR from JR.HB and JALR from JALR.HB" 121 format Jump { 122 0x0: decode HINT { 123 0x1: jr_hb({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");}; }}, IsReturn, ClearHazards); 124 default: jr({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");};}}, IsReturn); 125 } 126 127 0x1: decode HINT { 128 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall 129 , ClearHazards); 130 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall); 131 } 132 } 133 134 format BasicOp { 135 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 136 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 137#if FULL_SYSTEM 138 0x4: syscall({{ 139 fault = new SystemCallFault(); 140 }}); 141#else 142 0x4: syscall({{ xc->syscall(R2); }}, 143 IsSerializeAfter, IsNonSpeculative); 144#endif 145 0x7: sync({{ ; }}, IsMemBarrier); 146 0x5: break({{fault = new BreakpointFault();}}); 147 } 148 149 } 150 151 0x2: decode FUNCTION_LO { 152 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess); 153 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); 154 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess); 155 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 156 } 157 158 0x3: decode FUNCTION_LO { 159 format HiLoRdSelValOp { 160 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp); 161 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp); 162 } 163 164 format HiLoOp { 165 0x2: div({{ if (Rt.sd != 0) { 166 HI0 = Rs.sd % Rt.sd; 167 LO0 = Rs.sd / Rt.sd; 168 } 169 }}, IntDivOp); 170 171 0x3: divu({{ if (Rt.ud != 0) { 172 HI0 = Rs.ud % Rt.ud; 173 LO0 = Rs.ud / Rt.ud; 174 } 175 }}, IntDivOp); 176 } 177 } 178 179 0x4: decode HINT { 180 0x0: decode FUNCTION_LO { 181 format IntOp { 182 0x0: add({{ /* More complicated since an ADD can cause an arithmetic overflow exception */ 183 int64_t Src1 = Rs.sw; 184 int64_t Src2 = Rt.sw; 185 int64_t temp_result; 186#if FULL_SYSTEM 187 if(((Src1 >> 31) & 1) == 1) 188 Src1 |= 0x100000000LL; 189#endif 190 temp_result = Src1 + Src2; 191#if FULL_SYSTEM 192 if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ 193#endif 194 Rd.sw = temp_result; 195#if FULL_SYSTEM 196 } else{ 197 fault = new ArithmeticFault(); 198 } 199#endif 200 201 }}); 202 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 203 0x2: sub({{ 204 /* More complicated since an SUB can cause an arithmetic overflow exception */ 205 int64_t Src1 = Rs.sw; 206 int64_t Src2 = Rt.sw; 207 int64_t temp_result = Src1 - Src2; 208#if FULL_SYSTEM 209 if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){ 210#endif 211 Rd.sw = temp_result; 212#if FULL_SYSTEM 213 } else{ 214 fault = new ArithmeticFault(); 215 } 216#endif 217 }}); 218 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 219 0x4: and({{ Rd = Rs & Rt;}}); 220 0x5: or({{ Rd = Rs | Rt;}}); 221 0x6: xor({{ Rd = Rs ^ Rt;}}); 222 0x7: nor({{ Rd = ~(Rs | Rt);}}); 223 } 224 } 225 } 226 227 0x5: decode HINT { 228 0x0: decode FUNCTION_LO { 229 format IntOp{ 230 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 231 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 232 } 233 } 234 } 235 236 0x6: decode FUNCTION_LO { 237 format Trap { 238 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 239 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 240 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 241 0x3: tltu({{ cond = (Rs.uw < Rt.uw); }}); 242 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 243 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 244 } 245 } 246 } 247 248 0x1: decode REGIMM_HI { 249 0x0: decode REGIMM_LO { 250 format Branch { 251 0x0: bltz({{ cond = (Rs.sw < 0); }}); 252 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 253 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely); 254 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely); 255 } 256 } 257 258 0x1: decode REGIMM_LO { 259 format TrapImm { 260 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }}); 261 0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }}); 262 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }}); 263 0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }}); 264 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}}); 265 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}}); 266 } 267 } 268 269 0x2: decode REGIMM_LO { 270 format Branch { 271 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link); 272 0x1: decode RS { 273 0x0: bal ({{ cond = 1; }}, IsCall, Link); 274 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link); 275 } 276 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely); 277 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely); 278 } 279 } 280 281 0x3: decode REGIMM_LO { 282 // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL) 283 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 284 format WarnUnimpl { 285 0x7: synci(); 286 } 287 } 288 } 289 290 format Jump { 291 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 292 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall, 293 Link); 294 } 295 296 format Branch { 297 0x4: decode RS_RT { 298 0x0: b({{ cond = 1; }}); 299 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 300 } 301 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 302 0x6: blez({{ cond = (Rs.sw <= 0); }}); 303 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 304 } 305 } 306 307 0x1: decode OPCODE_LO { 308 format IntImmOp { 309 0x0: addi({{ 310 int64_t Src1 = Rs.sw; 311 int64_t Src2 = imm; 312 int64_t temp_result; 313#if FULL_SYSTEM 314 if(((Src1 >> 31) & 1) == 1) 315 Src1 |= 0x100000000LL; 316#endif 317 temp_result = Src1 + Src2; 318#if FULL_SYSTEM 319 if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ 320#endif 321 Rt.sw = temp_result; 322#if FULL_SYSTEM 323 } else{ 324 fault = new ArithmeticFault(); 325 } 326#endif 327 }}); 328 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 329 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 330 331 //Edited to include MIPS AVP Pass/Fail instructions and 332 //default to the sltiu instruction 333 0x3: decode RS_RT_INTIMM { 334 0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }}); 335 0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }}); 336 default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 337 } 338 339 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 340 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 341 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 342 343 0x7: decode RS { 344 0x0: lui({{ Rt = imm << 16}}); 345 } 346 } 347 } 348 349 0x2: decode OPCODE_LO { 350 //Table A-11 MIPS32 COP0 Encoding of rs Field 351 0x0: decode RS_MSB { 352 0x0: decode RS { 353 format CP0Control { 354 0x0: mfc0({{ Rt = CP0_RD_SEL; 355 /* Hack for PageMask */ 356 if(RD == 5) // PageMask 357 if(Config3_SP == 0 || PageGrain_ESP == 0) 358 Rt &= 0xFFFFE7FF; 359 }}); 360 0x4: mtc0({{ CP0_RD_SEL = Rt; 361 362 if(RD == 11) // Compare{ 363 if(Cause_TI == 1){ 364 Cause_TI = 0; 365 MiscReg cause = xc->readMiscRegNoEffect(MipsISA::Cause); 366 int Offset = 10; // corresponding to Cause_IP0 367 Offset += ((IntCtl_IPTI) - 2); 368 replaceBits(cause,Offset,Offset,0); 369 xc->setMiscRegNoEffect(MipsISA::Cause,cause); 370 } 371 372 }}); 373 } 374 format CP0Unimpl { 375 0x1: dmfc0(); 376 0x5: dmtc0(); 377 default: unknown(); 378 } 379 format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions 380 0x8: decode MT_U { 381 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) + 382 Ctrl_Base_DepTag); 383 }}); 384 0x1: decode SEL { 385 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }}); 386 0x1: decode RT { 387 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }}); 388 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }}); 389 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }}); 390 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }}); 391 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }}); 392 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }}); 393 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }}); 394 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }}); 395 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }}); 396 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }}); 397 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }}); 398 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }}); 399 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }}); 400 default: CP0Unimpl::unknown(); 401 } 402 0x2: decode MT_H { 403 0x0: mftc1({{ data = xc->readRegOtherThread(RT + 404 FP_Base_DepTag); 405 }}); 406 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + 407 FP_Base_DepTag); 408 }}); 409 } 410 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR + 411 FP_Base_DepTag); 412 switch (RT) 413 { 414 case 0: 415 data = xc->readRegOtherThread(MipsISA::FIR + 416 Ctrl_Base_DepTag); 417 break; 418 case 25: 419 data = (fcsr_val & 0xFE000000 >> 24) 420 | (fcsr_val & 0x00800000 >> 23); 421 break; 422 case 26: 423 data = fcsr_val & 0x0003F07C; 424 break; 425 case 28: 426 data = (fcsr_val & 0x00000F80) 427 | (fcsr_val & 0x01000000 >> 21) 428 | (fcsr_val & 0x00000003); 429 break; 430 case 31: 431 data = fcsr_val; 432 break; 433 default: 434 fatal("FP Control Value (%d) Not Valid"); 435 } 436 }}); 437 default: CP0Unimpl::unknown(); 438 } 439 } 440 } 441 442 format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions 443 0xC: decode MT_U { 444 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, 445 Rt); 446 }}); 447 0x1: decode SEL { 448 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 449 0x1: decode RT { 450 0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt); 451 }}); 452 0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0, 453 Rt); 454 }}); 455 0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0, 456 Rt); 457 }}); 458 0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1, 459 Rt); 460 }}); 461 0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1, 462 Rt); 463 }}); 464 0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1, 465 Rt); 466 }}); 467 0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2, 468 Rt); 469 }}); 470 0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2, 471 Rt); 472 }}); 473 0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2, 474 Rt); 475 }}); 476 0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3, 477 Rt); 478 }}); 479 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3, 480 Rt); 481 }}); 482 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt); 483 }}); 484 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }}); 485 default: CP0Unimpl::unknown(); 486 487 } 488 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + 489 FP_Base_DepTag); 490 data = insertBits(data, top_bit, bottom_bit, Rt); 491 xc->setRegOtherThread(RD + FP_Base_DepTag, data); 492 }}); 493 0x3: cttc1({{ uint32_t data; 494 switch (RD) 495 { 496 case 25: 497 data = 0 | (Rt.uw<7:1> << 25) // move 31...25 498 | (FCSR & 0x01000000) // bit 24 499 | (FCSR & 0x004FFFFF);// bit 22...0 500 break; 501 502 case 26: 503 data = 0 | (FCSR & 0xFFFC0000) // move 31...18 504 | Rt.uw<17:12> << 12 // bit 17...12 505 | (FCSR & 0x00000F80) << 7// bit 11...7 506 | Rt.uw<6:2> << 2 // bit 6...2 507 | (FCSR & 0x00000002); // bit 1...0 508 break; 509 510 case 28: 511 data = 0 | (FCSR & 0xFE000000) // move 31...25 512 | Rt.uw<2:2> << 24 // bit 24 513 | (FCSR & 0x00FFF000) << 23// bit 23...12 514 | Rt.uw<11:7> << 7 // bit 24 515 | (FCSR & 0x000007E) 516 | Rt.uw<1:0>;// bit 22...0 517 break; 518 519 case 31: 520 data = Rt.uw; 521 break; 522 523 default: 524 panic("FP Control Value (%d) Not Available. Ignoring Access to" 525 "Floating Control Status Register", FS); 526 } 527 xc->setRegOtherThread(FCSR, data); 528 }}); 529 default: CP0Unimpl::unknown(); 530 } 531 } 532 } 533 534 535 0xB: decode RD { 536 format MT_Control { 537 0x0: decode POS { 538 0x0: decode SEL { 539 0x1: decode SC { 540 0x0: dvpe({{ Rt = MVPControl; 541 if (VPEConf0<VPEC0_MVP:> == 1) { 542 MVPControl = insertBits(MVPControl, MVPC_EVP, 0); 543 } 544 }}); 545 0x1: evpe({{ Rt = MVPControl; 546 if (VPEConf0<VPEC0_MVP:> == 1) { 547 MVPControl = insertBits(MVPControl, MVPC_EVP, 1); 548 } 549 }}); 550 default:CP0Unimpl::unknown(); 551 } 552 default:CP0Unimpl::unknown(); 553 } 554 default:CP0Unimpl::unknown(); 555 } 556 557 0x1: decode POS { 558 0xF: decode SEL { 559 0x1: decode SC { 560 0x0: dmt({{ Rt = VPEControl; 561 VPEControl = insertBits(VPEControl, VPEC_TE, 0); 562 }}); 563 0x1: emt({{ Rt = VPEControl; 564 VPEControl = insertBits(VPEControl, VPEC_TE, 1); 565 }}); 566 default:CP0Unimpl::unknown(); 567 } 568 default:CP0Unimpl::unknown(); 569 } 570 default:CP0Unimpl::unknown(); 571 } 572 } 573 0xC: decode POS { 574 0x0: decode SC { 575 0x0: CP0Control::di({{ 576 if(Config_AR >= 1) // Rev 2.0 or beyond? 577 { 578 Rt = Status; 579 Status_IE = 0; 580 } 581 else // Enable this else branch once we actually set values for Config on init 582 { 583 fault = new ReservedInstructionFault(); 584 } 585 }}); 586 0x1: CP0Control::ei({{ 587 if(Config_AR >= 1) 588 { 589 Rt = Status; 590 Status_IE = 1; 591 } 592 else 593 { 594 fault = new ReservedInstructionFault(); 595 } 596 }}); 597 default:CP0Unimpl::unknown(); 598 } 599 } 600 default: CP0Unimpl::unknown(); 601 } 602 format CP0Control { 603 0xA: rdpgpr({{ 604 if(Config_AR >= 1) 605 { // Rev 2 of the architecture 606 panic("Shadow Sets Not Fully Implemented.\n"); 607 //Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS); 608 } 609 else 610 { 611 fault = new ReservedInstructionFault(); 612 } 613 }}); 614 0xE: wrpgpr({{ 615 if(Config_AR >= 1) 616 { // Rev 2 of the architecture 617 panic("Shadow Sets Not Fully Implemented.\n"); 618 //xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt); 619 // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl); 620 } 621 else 622 { 623 fault = new ReservedInstructionFault(); 624 } 625 626 }}); 627 } 628 629 } 630 631 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 632 0x1: decode FUNCTION { 633 format CP0Control { 634 0x18: eret({{ 635 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 636 // Ugly hack to get the value of Status_EXL 637 if(Status_EXL == 1){ 638 DPRINTF(MipsPRA,"ERET EXL Hack\n"); 639 } 640 if(Status_ERL == 1){ 641 Status_ERL = 0; 642 NPC = ErrorEPC; 643 NNPC = ErrorEPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break 644 } 645 else { 646 NPC = EPC; 647 NNPC = EPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break 648 Status_EXL = 0; 649 if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){ 650 SRSCtl_CSS = SRSCtl_PSS; 651 //xc->setShadowSet(SRSCtl_PSS); 652 } 653 } 654 LLFlag = 0; 655 }},IsReturn,IsSerializing,IsERET); 656 657 0x1F: deret({{ 658 // if(EJTagImplemented()) { 659 if(Debug_DM == 1){ 660 Debug_DM = 1; 661 Debug_IEXI = 0; 662 NPC = DEPC; 663 } 664 else 665 { 666 // Undefined; 667 } 668 //} // EJTag Implemented 669 //else { 670 // Reserved Instruction Exception 671 //} 672 }},IsReturn,IsSerializing,IsERET); 673 } 674 format CP0TLB { 675 0x01: tlbr({{ 676 MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF); 677 if(PTEntry == NULL) 678 { 679 fatal("Invalid PTE Entry received on a TLBR instruction\n"); 680 } 681 /* Setup PageMask */ 682 PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11 683 /* Setup EntryHi */ 684 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 685 /* Setup Entry Lo0 */ 686 EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G); 687 /* Setup Entry Lo1 */ 688 EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G); 689 }}); // Need to hook up to TLB 690 691 0x02: tlbwi({{ 692 //Create PTE 693 MipsISA::PTE NewEntry; 694 //Write PTE 695 NewEntry.Mask = (Addr)(PageMask >> 11); 696 NewEntry.VPN = (Addr)(EntryHi >> 11); 697 /* PageGrain _ ESP Config3 _ SP */ 698 if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) { 699 NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes 700 NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled 701 } 702 NewEntry.asid = (uint8_t)(EntryHi & 0xFF); 703 704 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); 705 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); 706 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 707 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 708 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 709 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 710 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 711 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 712 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 713 /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */ 714 /* Addr Shift Amount for 1KB or larger pages */ 715 // warn("PTE->Mask: %x\n",pte->Mask); 716 if((NewEntry.Mask & 0xFFFF) == 3){ 717 NewEntry.AddrShiftAmount = 12; 718 } else if((NewEntry.Mask & 0xFFFF) == 0x0000){ 719 NewEntry.AddrShiftAmount = 10; 720 } else if((NewEntry.Mask & 0xFFFC) == 0x000C){ 721 NewEntry.AddrShiftAmount = 14; 722 } else if((NewEntry.Mask & 0xFFF0) == 0x0030){ 723 NewEntry.AddrShiftAmount = 16; 724 } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){ 725 NewEntry.AddrShiftAmount = 18; 726 } else if((NewEntry.Mask & 0xFF00) == 0x0300){ 727 NewEntry.AddrShiftAmount = 20; 728 } else if((NewEntry.Mask & 0xFC00) == 0x0C00){ 729 NewEntry.AddrShiftAmount = 22; 730 } else if((NewEntry.Mask & 0xF000) == 0x3000){ 731 NewEntry.AddrShiftAmount = 24; 732 } else if((NewEntry.Mask & 0xC000) == 0xC000){ 733 NewEntry.AddrShiftAmount = 26; 734 } else if((NewEntry.Mask & 0x30000) == 0x30000){ 735 NewEntry.AddrShiftAmount = 28; 736 } else { 737 fatal("Invalid Mask Pattern Detected!\n"); 738 } 739 NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1); 740 741 MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr(); 742 MiscReg c3=xc->readMiscReg(MipsISA::Config3); 743 MiscReg pg=xc->readMiscReg(MipsISA::PageGrain); 744 int SP=0; 745 if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){ 746 SP=1; 747 } 748 Ptr->insertAt(NewEntry,Index & 0x7FFFFFFF,SP); 749 }}); 750 0x06: tlbwr({{ 751 //Create PTE 752 MipsISA::PTE NewEntry; 753 //Write PTE 754 NewEntry.Mask = (Addr)(PageMask >> 11); 755 NewEntry.VPN = (Addr)(EntryHi >> 11); 756 /* PageGrain _ ESP Config3 _ SP */ 757 if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) { 758 NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes 759 NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled 760 } 761 NewEntry.asid = (uint8_t)(EntryHi & 0xFF); 762 763 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); 764 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); 765 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 766 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 767 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 768 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 769 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 770 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 771 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 772 /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */ 773 /* Addr Shift Amount for 1KB or larger pages */ 774 // warn("PTE->Mask: %x\n",pte->Mask); 775 if((NewEntry.Mask & 0xFFFF) == 3){ 776 NewEntry.AddrShiftAmount = 12; 777 } else if((NewEntry.Mask & 0xFFFF) == 0x0000){ 778 NewEntry.AddrShiftAmount = 10; 779 } else if((NewEntry.Mask & 0xFFFC) == 0x000C){ 780 NewEntry.AddrShiftAmount = 14; 781 } else if((NewEntry.Mask & 0xFFF0) == 0x0030){ 782 NewEntry.AddrShiftAmount = 16; 783 } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){ 784 NewEntry.AddrShiftAmount = 18; 785 } else if((NewEntry.Mask & 0xFF00) == 0x0300){ 786 NewEntry.AddrShiftAmount = 20; 787 } else if((NewEntry.Mask & 0xFC00) == 0x0C00){ 788 NewEntry.AddrShiftAmount = 22; 789 } else if((NewEntry.Mask & 0xF000) == 0x3000){ 790 NewEntry.AddrShiftAmount = 24; 791 } else if((NewEntry.Mask & 0xC000) == 0xC000){ 792 NewEntry.AddrShiftAmount = 26; 793 } else if((NewEntry.Mask & 0x30000) == 0x30000){ 794 NewEntry.AddrShiftAmount = 28; 795 } else { 796 fatal("Invalid Mask Pattern Detected!\n"); 797 } 798 NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1); 799 800 MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr(); 801 MiscReg c3=xc->readMiscReg(MipsISA::Config3); 802 MiscReg pg=xc->readMiscReg(MipsISA::PageGrain); 803 int SP=0; 804 if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){ 805 SP=1; 806 } 807 Ptr->insertAt(NewEntry,Random,SP); 808 }}); 809 810 0x08: tlbp({{ 811 int TLB_Index; 812 Addr VPN; 813 if(PageGrain_ESP == 1 && Config3_SP ==1){ 814 VPN = EntryHi >> 11; 815 } else { 816 VPN = ((EntryHi >> 11) & 0xFFFFFFFC); // Mask off lower 2 bits 817 } 818 TLB_Index = xc->tcBase()->getITBPtr()->probeEntry(VPN,EntryHi_ASID); 819 if(TLB_Index != -1){ // Check TLB for entry matching EntryHi 820 Index=TLB_Index; 821 // warn("\ntlbp: Match Found!\n"); 822 } else {// else, set Index = 1<<31 823 Index = (1<<31); 824 } 825 }}); 826 } 827 format CP0Unimpl { 828 0x20: wait(); 829 } 830 default: CP0Unimpl::unknown(); 831 832 } 833 } 834 835 //Table A-13 MIPS32 COP1 Encoding of rs Field 836 0x1: decode RS_MSB { 837 838 0x0: decode RS_HI { 839 0x0: decode RS_LO { 840 format CP1Control { 841 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 842 843 0x2: cfc1({{ 844 switch (FS) 845 { 846 case 0: 847 Rt = FIR; 848 break; 849 case 25: 850 Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23; 851 break; 852 case 26: 853 Rt = 0 | (FCSR & 0x0003F07C); 854 break; 855 case 28: 856 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003); 857 break; 858 case 31: 859 Rt = FCSR; 860 break; 861 default: 862 warn("FP Control Value (%d) Not Valid"); 863 } 864 // warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt); 865 }}); 866 867 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 868 869 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 870 871 0x6: ctc1({{ 872 switch (FS) 873 { 874 case 25: 875 FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25 876 | (FCSR & 0x01000000) // bit 24 877 | (FCSR & 0x004FFFFF);// bit 22...0 878 break; 879 880 case 26: 881 FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18 882 | Rt.uw<17:12> << 12 // bit 17...12 883 | (FCSR & 0x00000F80) << 7// bit 11...7 884 | Rt.uw<6:2> << 2 // bit 6...2 885 | (FCSR & 0x00000002); // bit 1...0 886 break; 887 888 case 28: 889 FCSR = 0 | (FCSR & 0xFE000000) // move 31...25 890 | Rt.uw<2:2> << 24 // bit 24 891 | (FCSR & 0x00FFF000) << 23// bit 23...12 892 | Rt.uw<11:7> << 7 // bit 24 893 | (FCSR & 0x000007E) 894 | Rt.uw<1:0>;// bit 22...0 895 break; 896 897 case 31: 898 FCSR = Rt.uw; 899 break; 900 901 default: 902 panic("FP Control Value (%d) Not Available. Ignoring Access to" 903 "Floating Control Status Register", FS); 904 } 905 }}); 906 907 0x7: mthc1({{ 908 uint64_t fs_hi = Rt.uw; 909 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 910 Fs.ud = (fs_hi << 32) | fs_lo; 911 }}); 912 913 } 914 format CP1Unimpl { 915 0x1: dmfc1(); 916 0x5: dmtc1(); 917 } 918 } 919 920 0x1: 921 decode RS_LO { 922 0x0: 923 decode ND { 924 format Branch { 925 0x0: decode TF { 926 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 927 }}); 928 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 929 }}); 930 } 931 0x1: decode TF { 932 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 933 }}, Likely); 934 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 935 }}, Likely); 936 } 937 } 938 } 939 format CP1Unimpl { 940 0x1: bc1any2(); 941 0x2: bc1any4(); 942 default: unknown(); 943 } 944 } 945 } 946 947 0x1: decode RS_HI { 948 0x2: decode RS_LO { 949 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 950 //(( single-precision floating point)) 951 0x0: decode FUNCTION_HI { 952 0x0: decode FUNCTION_LO { 953 format FloatOp { 954 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 955 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 956 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 957 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 958 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 959 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 960 0x7: neg_s({{ Fd.sf = -Fs.sf;}}); 961 } 962 963 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}}); 964 } 965 966 0x1: decode FUNCTION_LO { 967 format FloatConvertOp { 968 0x0: round_l_s({{ val = Fs.sf; }}, ToLong, 969 Round); 970 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong, 971 Trunc); 972 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong, 973 Ceil); 974 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong, 975 Floor); 976 0x4: round_w_s({{ val = Fs.sf; }}, ToWord, 977 Round); 978 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord, 979 Trunc); 980 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord, 981 Ceil); 982 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord, 983 Floor); 984 } 985 } 986 987 0x2: decode FUNCTION_LO { 988 0x1: decode MOVCF { 989 format BasicOp { 990 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }}); 991 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }}); 992 } 993 } 994 995 format BasicOp { 996 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 997 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 998 } 999 1000 format FloatOp { 1001 0x5: recip_s({{ Fd = 1 / Fs; }}); 1002 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); 1003 } 1004 format CP1Unimpl { 1005 default: unknown(); 1006 } 1007 } 1008 0x3: CP1Unimpl::unknown(); 1009 1010 0x4: decode FUNCTION_LO { 1011 format FloatConvertOp { 1012 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 1013 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 1014 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 1015 } 1016 1017 0x6: FloatOp::cvt_ps_s({{ 1018 Fd.ud = (uint64_t) Fs.uw << 32 | 1019 (uint64_t) Ft.uw; 1020 }}); 1021 format CP1Unimpl { 1022 default: unknown(); 1023 } 1024 } 1025 0x5: CP1Unimpl::unknown(); 1026 1027 0x6: decode FUNCTION_LO { 1028 format FloatCompareOp { 1029 0x0: c_f_s({{ cond = 0; }}, SinglePrecision, 1030 UnorderedFalse); 1031 0x1: c_un_s({{ cond = 0; }}, SinglePrecision, 1032 UnorderedTrue); 1033 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 1034 UnorderedFalse); 1035 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 1036 UnorderedTrue); 1037 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 1038 UnorderedFalse); 1039 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 1040 UnorderedTrue); 1041 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }}, 1042 UnorderedFalse); 1043 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }}, 1044 UnorderedTrue); 1045 } 1046 } 1047 1048 0x7: decode FUNCTION_LO { 1049 format FloatCompareOp { 1050 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1051 UnorderedFalse, QnanException); 1052 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1053 UnorderedTrue, QnanException); 1054 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}}, 1055 UnorderedFalse, QnanException); 1056 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 1057 UnorderedTrue, QnanException); 1058 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 1059 UnorderedFalse, QnanException); 1060 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 1061 UnorderedTrue, QnanException); 1062 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 1063 UnorderedFalse, QnanException); 1064 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 1065 UnorderedTrue, QnanException); 1066 } 1067 } 1068 } 1069 1070 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 1071 0x1: decode FUNCTION_HI { 1072 0x0: decode FUNCTION_LO { 1073 format FloatOp { 1074 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 1075 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 1076 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 1077 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); 1078 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 1079 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 1080 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); 1081 } 1082 1083 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); 1084 } 1085 1086 0x1: decode FUNCTION_LO { 1087 format FloatConvertOp { 1088 0x0: round_l_d({{ val = Fs.df; }}, ToLong, 1089 Round); 1090 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong, 1091 Trunc); 1092 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong, 1093 Ceil); 1094 0x3: floor_l_d({{ val = Fs.df; }}, ToLong, 1095 Floor); 1096 0x4: round_w_d({{ val = Fs.df; }}, ToWord, 1097 Round); 1098 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord, 1099 Trunc); 1100 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord, 1101 Ceil); 1102 0x7: floor_w_d({{ val = Fs.df; }}, ToWord, 1103 Floor); 1104 } 1105 } 1106 1107 0x2: decode FUNCTION_LO { 1108 0x1: decode MOVCF { 1109 format BasicOp { 1110 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ? 1111 Fs.df : Fd.df; 1112 }}); 1113 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ? 1114 Fs.df : Fd.df; 1115 }}); 1116 } 1117 } 1118 1119 format BasicOp { 1120 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }}); 1121 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }}); 1122 } 1123 1124 format FloatOp { 1125 0x5: recip_d({{ Fd.df = 1 / Fs.df }}); 1126 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }}); 1127 } 1128 format CP1Unimpl { 1129 default: unknown(); 1130 } 1131 1132 } 1133 0x4: decode FUNCTION_LO { 1134 format FloatConvertOp { 1135 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 1136 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 1137 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 1138 } 1139 default: CP1Unimpl::unknown(); 1140 } 1141 1142 0x6: decode FUNCTION_LO { 1143 format FloatCompareOp { 1144 0x0: c_f_d({{ cond = 0; }}, DoublePrecision, 1145 UnorderedFalse); 1146 0x1: c_un_d({{ cond = 0; }}, DoublePrecision, 1147 UnorderedTrue); 1148 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 1149 UnorderedFalse); 1150 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 1151 UnorderedTrue); 1152 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 1153 UnorderedFalse); 1154 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 1155 UnorderedTrue); 1156 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }}, 1157 UnorderedFalse); 1158 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }}, 1159 UnorderedTrue); 1160 } 1161 } 1162 1163 0x7: decode FUNCTION_LO { 1164 format FloatCompareOp { 1165 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1166 UnorderedFalse, QnanException); 1167 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1168 UnorderedTrue, QnanException); 1169 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }}, 1170 UnorderedFalse, QnanException); 1171 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }}, 1172 UnorderedTrue, QnanException); 1173 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }}, 1174 UnorderedFalse, QnanException); 1175 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 1176 UnorderedTrue, QnanException); 1177 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 1178 UnorderedFalse, QnanException); 1179 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 1180 UnorderedTrue, QnanException); 1181 } 1182 } 1183 default: CP1Unimpl::unknown(); 1184 } 1185 0x2: CP1Unimpl::unknown(); 1186 0x3: CP1Unimpl::unknown(); 1187 0x7: CP1Unimpl::unknown(); 1188 1189 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 1190 0x4: decode FUNCTION { 1191 format FloatConvertOp { 1192 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 1193 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 1194 0x26: CP1Unimpl::cvt_ps_w(); 1195 } 1196 default: CP1Unimpl::unknown(); 1197 } 1198 1199 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 1200 //Note: "1. Format type L is legal only if 64-bit floating point operations 1201 //are enabled." 1202 0x5: decode FUNCTION_HI { 1203 format FloatConvertOp { 1204 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 1205 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 1206 0x26: CP1Unimpl::cvt_ps_l(); 1207 } 1208 default: CP1Unimpl::unknown(); 1209 } 1210 1211 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 1212 //Note: "1. Format type PS is legal only if 64-bit floating point operations 1213 //are enabled. " 1214 0x6: decode FUNCTION_HI { 1215 0x0: decode FUNCTION_LO { 1216 format Float64Op { 1217 0x0: add_ps({{ 1218 Fd1.sf = Fs1.sf + Ft2.sf; 1219 Fd2.sf = Fs2.sf + Ft2.sf; 1220 }}); 1221 0x1: sub_ps({{ 1222 Fd1.sf = Fs1.sf - Ft2.sf; 1223 Fd2.sf = Fs2.sf - Ft2.sf; 1224 }}); 1225 0x2: mul_ps({{ 1226 Fd1.sf = Fs1.sf * Ft2.sf; 1227 Fd2.sf = Fs2.sf * Ft2.sf; 1228 }}); 1229 0x5: abs_ps({{ 1230 Fd1.sf = fabs(Fs1.sf); 1231 Fd2.sf = fabs(Fs2.sf); 1232 }}); 1233 0x6: mov_ps({{ 1234 Fd1.sf = Fs1.sf; 1235 Fd2.sf = Fs2.sf; 1236 }}); 1237 0x7: neg_ps({{ 1238 Fd1.sf = -(Fs1.sf); 1239 Fd2.sf = -(Fs2.sf); 1240 }}); 1241 default: CP1Unimpl::unknown(); 1242 } 1243 } 1244 0x1: CP1Unimpl::unknown(); 1245 0x2: decode FUNCTION_LO { 1246 0x1: decode MOVCF { 1247 format Float64Op { 1248 0x0: movf_ps({{ 1249 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1250 Fs1 : Fd1; 1251 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1252 Fs2 : Fd2; 1253 }}); 1254 0x1: movt_ps({{ 1255 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1256 Fs1 : Fd1; 1257 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1258 Fs2 : Fd2; 1259 }}); 1260 } 1261 } 1262 1263 format Float64Op { 1264 0x2: movz_ps({{ 1265 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1266 Fs1 : Fd1; 1267 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1268 Fs2 : Fd2; 1269 }}); 1270 0x3: movn_ps({{ 1271 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1272 Fs1 : Fd1; 1273 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1274 Fs2 : Fd2; 1275 }}); 1276 } 1277 default: CP1Unimpl::unknown(); 1278 1279 } 1280 0x3: CP1Unimpl::unknown(); 1281 0x4: decode FUNCTION_LO { 1282 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 1283 default: CP1Unimpl::unknown(); 1284 } 1285 1286 0x5: decode FUNCTION_LO { 1287 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); 1288 1289 format Float64Op { 1290 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 1291 Ft1.uw; 1292 }}); 1293 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 1294 Ft2.uw; 1295 }}); 1296 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 1297 Ft1.uw; 1298 }}); 1299 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 1300 Ft2.uw; 1301 }}); 1302 } 1303 default: CP1Unimpl::unknown(); 1304 } 1305 1306 0x6: decode FUNCTION_LO { 1307 format FloatPSCompareOp { 1308 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1309 UnorderedFalse); 1310 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1311 UnorderedTrue); 1312 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1313 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1314 UnorderedFalse); 1315 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1316 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1317 UnorderedTrue); 1318 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1319 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1320 UnorderedFalse); 1321 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }}, 1322 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1323 UnorderedTrue); 1324 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }}, 1325 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1326 UnorderedFalse); 1327 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1328 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1329 UnorderedTrue); 1330 } 1331 } 1332 1333 0x7: decode FUNCTION_LO { 1334 format FloatPSCompareOp { 1335 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1336 UnorderedFalse, QnanException); 1337 0x1: c_ngle_ps({{ cond1 = 0; }}, 1338 {{ cond2 = 0; }}, 1339 UnorderedTrue, QnanException); 1340 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1341 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1342 UnorderedFalse, QnanException); 1343 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1344 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1345 UnorderedTrue, QnanException); 1346 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1347 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1348 UnorderedFalse, QnanException); 1349 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1350 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1351 UnorderedTrue, QnanException); 1352 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1353 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1354 UnorderedFalse, QnanException); 1355 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1356 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1357 UnorderedTrue, QnanException); 1358 } 1359 } 1360 } 1361 } 1362 default: CP1Unimpl::unknown(); 1363 } 1364 } 1365 1366 //Table A-19 MIPS32 COP2 Encoding of rs Field 1367 0x2: decode RS_MSB { 1368 format CP2Unimpl { 1369 0x0: decode RS_HI { 1370 0x0: decode RS_LO { 1371 0x0: mfc2(); 1372 0x2: cfc2(); 1373 0x3: mfhc2(); 1374 0x4: mtc2(); 1375 0x6: ctc2(); 1376 0x7: mftc2(); 1377 default: unknown(); 1378 } 1379 1380 0x1: decode ND { 1381 0x0: decode TF { 1382 0x0: bc2f(); 1383 0x1: bc2t(); 1384 default: unknown(); 1385 } 1386 1387 0x1: decode TF { 1388 0x0: bc2fl(); 1389 0x1: bc2tl(); 1390 default: unknown(); 1391 } 1392 default: unknown(); 1393 1394 } 1395 default: unknown(); 1396 1397 } 1398 default: unknown(); 1399 } 1400 } 1401 1402 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1403 //Note: "COP1X instructions are legal only if 64-bit floating point 1404 //operations are enabled." 1405 0x3: decode FUNCTION_HI { 1406 0x0: decode FUNCTION_LO { 1407 format LoadIndexedMemory { 1408 0x0: lwxc1({{ Fd.uw = Mem.uw;}}); 1409 0x1: ldxc1({{ Fd.ud = Mem.ud;}}); 1410 0x5: luxc1({{ Fd.ud = Mem.ud;}}, 1411 {{ EA = (Rs + Rt) & ~7; }}); 1412 } 1413 } 1414 1415 0x1: decode FUNCTION_LO { 1416 format StoreIndexedMemory { 1417 0x0: swxc1({{ Mem.uw = Fs.uw;}}); 1418 0x1: sdxc1({{ Mem.ud = Fs.ud;}}); 1419 0x5: suxc1({{ Mem.ud = Fs.ud;}}, 1420 {{ EA = (Rs + Rt) & ~7; }}); 1421 } 1422 1423 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1424 } 1425 1426 0x3: decode FUNCTION_LO { 1427 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) { 1428 Fd.ud = Fs.ud; 1429 } else if (Rs<2:0> == 4) { 1430 #if BYTE_ORDER == BIG_ENDIAN 1431 Fd.ud = Fs.ud<31:0> << 32 | 1432 Ft.ud<63:32>; 1433 #elif BYTE_ORDER == LITTLE_ENDIAN 1434 Fd.ud = Ft.ud<31:0> << 32 | 1435 Fs.ud<63:32>; 1436 #endif 1437 } else { 1438 Fd.ud = Fd.ud; 1439 } 1440 }}); 1441 } 1442 1443 format FloatAccOp { 1444 0x4: decode FUNCTION_LO { 1445 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 1446 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 1447 0x6: madd_ps({{ 1448 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; 1449 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; 1450 }}); 1451 } 1452 1453 0x5: decode FUNCTION_LO { 1454 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); 1455 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 1456 0x6: msub_ps({{ 1457 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; 1458 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; 1459 }}); 1460 } 1461 1462 0x6: decode FUNCTION_LO { 1463 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1464 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 1465 0x6: nmadd_ps({{ 1466 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df); 1467 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df); 1468 }}); 1469 } 1470 1471 0x7: decode FUNCTION_LO { 1472 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1473 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 1474 0x6: nmsub_ps({{ 1475 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 1476 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 1477 }}); 1478 } 1479 1480 } 1481 } 1482 1483 format Branch { 1484 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 1485 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 1486 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 1487 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 1488 } 1489 } 1490 1491 0x3: decode OPCODE_LO { 1492 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1493 0x4: decode FUNCTION_HI { 1494 0x0: decode FUNCTION_LO { 1495 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd; 1496 Rd.sw = temp1<31:0>; 1497 }}, IntMultOp); 1498 1499 format HiLoRdSelValOp { 1500 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}, IntMultOp); 1501 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}, IntMultOp); 1502 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}, IntMultOp); 1503 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}, IntMultOp); 1504 } 1505 } 1506 1507 0x4: decode FUNCTION_LO { 1508 format BasicOp { 1509 0x0: clz({{ int cnt = 32; 1510 for (int idx = 31; idx >= 0; idx--) { 1511 if( Rs<idx:idx> == 1) { 1512 cnt = 31 - idx; 1513 break; 1514 } 1515 } 1516 Rd.uw = cnt; 1517 }}); 1518 0x1: clo({{ int cnt = 32; 1519 for (int idx = 31; idx >= 0; idx--) { 1520 if( Rs<idx:idx> == 0) { 1521 cnt = 31 - idx; 1522 break; 1523 } 1524 } 1525 Rd.uw = cnt; 1526 }}); 1527 } 1528 } 1529 1530 0x7: decode FUNCTION_LO { 1531 0x7: FailUnimpl::sdbbp(); 1532 } 1533 } 1534 1535 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1536 //of the Architecture 1537 0x7: decode FUNCTION_HI { 1538 0x0: decode FUNCTION_LO { 1539 format BasicOp { 1540 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); 1541 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 1542 bits(Rs.uw, MSB-LSB, 0) << LSB | 1543 bits(Rt.uw, LSB-1, 0); 1544 }}); 1545 } 1546 } 1547 1548 0x1: decode FUNCTION_LO { 1549 format MT_Control { 1550 0x0: fork({{ forkThread(xc->tcBase(), fault, RD, Rs, Rt); }}, 1551 UserMode); 1552 0x1: yield({{ Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, YQMask); }}, 1553 UserMode); 1554 } 1555 1556 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1557 0x2: decode OP_HI { 1558 0x0: decode OP_LO { 1559 format LoadIndexedMemory { 1560 0x0: lwx({{ Rd.sw = Mem.sw; }}); 1561 0x4: lhx({{ Rd.sw = Mem.sh; }}); 1562 0x6: lbux({{ Rd.uw = Mem.ub; }}); 1563 } 1564 } 1565 } 1566 0x4: DspIntOp::insv({{ int pos = dspctl<5:0>; 1567 int size = dspctl<12:7>-1; 1568 Rt.uw = insertBits( Rt.uw, pos+size, pos, Rs.uw<size:0> ); }}); 1569 } 1570 1571 0x2: decode FUNCTION_LO { 1572 1573 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field (DSP ASE MANUAL) 1574 0x0: decode OP_HI { 1575 0x0: decode OP_LO { 1576 format DspIntOp { 1577 0x0: addu_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1578 NOSATURATE, UNSIGNED, &dspctl ); }}); 1579 0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, 1580 NOSATURATE, UNSIGNED, &dspctl ); }}); 1581 0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1582 SATURATE, UNSIGNED, &dspctl ); }}); 1583 0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, 1584 SATURATE, UNSIGNED, &dspctl ); }}); 1585 0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, 1586 MODE_L, &dspctl ); }}, IntMultOp); 1587 0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, 1588 MODE_R, &dspctl ); }}, IntMultOp); 1589 } 1590 } 1591 0x1: decode OP_LO { 1592 format DspIntOp { 1593 0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1594 NOSATURATE, UNSIGNED, &dspctl ); }}); 1595 0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1596 NOSATURATE, UNSIGNED, &dspctl ); }}); 1597 0x2: addq_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1598 NOSATURATE, SIGNED, &dspctl ); }}); 1599 0x3: subq_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1600 NOSATURATE, SIGNED, &dspctl ); }}); 1601 0x4: addu_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1602 SATURATE, UNSIGNED, &dspctl ); }}); 1603 0x5: subu_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1604 SATURATE, UNSIGNED, &dspctl ); }}); 1605 0x6: addq_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1606 SATURATE, SIGNED, &dspctl ); }}); 1607 0x7: subq_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1608 SATURATE, SIGNED, &dspctl ); }}); 1609 } 1610 } 1611 0x2: decode OP_LO { 1612 format DspIntOp { 1613 0x0: addsc({{ int64_t dresult; 1614 dresult = Rs.ud + Rt.ud; 1615 Rd.sw = dresult<31:0>; 1616 dspctl = insertBits( dspctl, 13, 13, 1617 dresult<32:32> ); }}); 1618 0x1: addwc({{ int64_t dresult; 1619 dresult = Rs.sd + Rt.sd + dspctl<13:13>; 1620 Rd.sw = dresult<31:0>; 1621 if( dresult<32:32> != dresult<31:31> ) 1622 dspctl = insertBits( dspctl, 20, 20, 1 ); }}); 1623 0x2: modsub({{ Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : Rs.sw - Rt.sw<7:0>; }}); 1624 0x4: raddu_w_qb({{ Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + 1625 Rs.uw<15:8> + Rs.uw<7:0>; }}); 1626 0x6: addq_s_w({{ Rd.sw = dspAdd( Rs.sw, Rt.sw, SIMD_FMT_W, 1627 SATURATE, SIGNED, &dspctl ); }}); 1628 0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W, 1629 SATURATE, SIGNED, &dspctl ); }}); 1630 } 1631 } 1632 0x3: decode OP_LO { 1633 format DspIntOp { 1634 0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, 1635 MODE_L, &dspctl ); }}, IntMultOp); 1636 0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, 1637 MODE_R, &dspctl ); }}, IntMultOp); 1638 0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, 1639 SATURATE, NOROUND, &dspctl ); }}, IntMultOp); 1640 0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, 1641 SATURATE, ROUND, &dspctl ); }}, IntMultOp); 1642 } 1643 } 1644 } 1645 1646 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL) 1647 0x1: decode OP_HI { 1648 0x0: decode OP_LO { 1649 format DspIntOp { 1650 0x0: cmpu_eq_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1651 UNSIGNED, CMP_EQ, &dspctl ); }}); 1652 0x1: cmpu_lt_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1653 UNSIGNED, CMP_LT, &dspctl ); }}); 1654 0x2: cmpu_le_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1655 UNSIGNED, CMP_LE, &dspctl ); }}); 1656 0x3: pick_qb({{ Rd.uw = dspPick( Rs.uw, Rt.uw, 1657 SIMD_FMT_QB, &dspctl ); }}); 1658 0x4: cmpgu_eq_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1659 UNSIGNED, CMP_EQ ); }}); 1660 0x5: cmpgu_lt_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1661 UNSIGNED, CMP_LT ); }}); 1662 0x6: cmpgu_le_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1663 UNSIGNED, CMP_LE ); }}); 1664 } 1665 } 1666 0x1: decode OP_LO { 1667 format DspIntOp { 1668 0x0: cmp_eq_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1669 SIGNED, CMP_EQ, &dspctl ); }}); 1670 0x1: cmp_lt_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1671 SIGNED, CMP_LT, &dspctl ); }}); 1672 0x2: cmp_le_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1673 SIGNED, CMP_LE, &dspctl ); }}); 1674 0x3: pick_ph({{ Rd.uw = dspPick( Rs.uw, Rt.uw, 1675 SIMD_FMT_PH, &dspctl ); }}); 1676 0x4: precrq_qb_ph({{ Rd.uw = Rs.uw<31:24> << 24 | 1677 Rs.uw<15:8> << 16 | 1678 Rt.uw<31:24> << 8 | 1679 Rt.uw<15:8>; }}); 1680 0x5: precr_qb_ph({{ Rd.uw = Rs.uw<23:16> << 24 | 1681 Rs.uw<7:0> << 16 | 1682 Rt.uw<23:16> << 8 | 1683 Rt.uw<7:0>; }}); 1684 0x6: packrl_ph({{ Rd.uw = dspPack( Rs.uw, Rt.uw, 1685 SIMD_FMT_PH ); }}); 1686 0x7: precrqu_s_qb_ph({{ Rd.uw = dspPrecrqu( Rs.uw, Rt.uw, &dspctl ); }}); 1687 } 1688 } 1689 0x2: decode OP_LO { 1690 format DspIntOp { 1691 0x4: precrq_ph_w({{ Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; }}); 1692 0x5: precrq_rs_ph_w({{ Rd.uw = dspPrecrq( Rs.uw, Rt.uw, SIMD_FMT_W, &dspctl ); }}); 1693 } 1694 } 1695 0x3: decode OP_LO { 1696 format DspIntOp { 1697 0x0: cmpgdu_eq_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1698 UNSIGNED, CMP_EQ, &dspctl ); }}); 1699 0x1: cmpgdu_lt_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1700 UNSIGNED, CMP_LT, &dspctl ); }}); 1701 0x2: cmpgdu_le_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1702 UNSIGNED, CMP_LE, &dspctl ); }}); 1703 0x6: precr_sra_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, 1704 SIMD_FMT_W, NOROUND ); }}); 1705 0x7: precr_sra_r_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, 1706 SIMD_FMT_W, ROUND ); }}); 1707 } 1708 } 1709 } 1710 1711 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field (DSP ASE MANUAL) 1712 0x2: decode OP_HI { 1713 0x0: decode OP_LO { 1714 format DspIntOp { 1715 0x1: absq_s_qb({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_QB, &dspctl );}}); 1716 0x2: repl_qb({{ Rd.uw = RS_RT<7:0> << 24 | 1717 RS_RT<7:0> << 16 | 1718 RS_RT<7:0> << 8 | 1719 RS_RT<7:0>; }}); 1720 0x3: replv_qb({{ Rd.sw = Rt.uw<7:0> << 24 | 1721 Rt.uw<7:0> << 16 | 1722 Rt.uw<7:0> << 8 | 1723 Rt.uw<7:0>; }}); 1724 0x4: precequ_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1725 SIMD_FMT_PH, SIGNED, MODE_L ); }}); 1726 0x5: precequ_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1727 SIMD_FMT_PH, SIGNED, MODE_R ); }}); 1728 0x6: precequ_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1729 SIMD_FMT_PH, SIGNED, MODE_LA ); }}); 1730 0x7: precequ_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1731 SIMD_FMT_PH, SIGNED, MODE_RA ); }}); 1732 } 1733 } 1734 0x1: decode OP_LO { 1735 format DspIntOp { 1736 0x1: absq_s_ph({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_PH, &dspctl ); }}); 1737 0x2: repl_ph({{ Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | 1738 (sext<10>(RS_RT))<15:0>; }}); 1739 0x3: replv_ph({{ Rd.uw = Rt.uw<15:0> << 16 | 1740 Rt.uw<15:0>; }}); 1741 0x4: preceq_w_phl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, 1742 SIMD_FMT_W, SIGNED, MODE_L ); }}); 1743 0x5: preceq_w_phr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, 1744 SIMD_FMT_W, SIGNED, MODE_R ); }}); 1745 } 1746 } 1747 0x2: decode OP_LO { 1748 format DspIntOp { 1749 0x1: absq_s_w({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_W, &dspctl ); }}); 1750 } 1751 } 1752 0x3: decode OP_LO { 1753 0x3: IntOp::bitrev({{ Rd.uw = bitrev( Rt.uw<15:0> ); }}); 1754 format DspIntOp { 1755 0x4: preceu_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1756 SIMD_FMT_PH, UNSIGNED, MODE_L ); }}); 1757 0x5: preceu_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1758 SIMD_FMT_PH, UNSIGNED, MODE_R ); }}); 1759 0x6: preceu_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1760 SIMD_FMT_PH, UNSIGNED, MODE_LA ); }}); 1761 0x7: preceu_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1762 SIMD_FMT_PH, UNSIGNED, MODE_RA ); }}); 1763 } 1764 } 1765 } 1766 1767 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field (DSP ASE MANUAL) 1768 0x3: decode OP_HI { 1769 0x0: decode OP_LO { 1770 format DspIntOp { 1771 0x0: shll_qb({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_QB, 1772 NOSATURATE, UNSIGNED, &dspctl ); }}); 1773 0x1: shrl_qb({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_QB, 1774 UNSIGNED ); }}); 1775 0x2: shllv_qb({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_QB, 1776 NOSATURATE, UNSIGNED, &dspctl ); }}); 1777 0x3: shrlv_qb({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_QB, 1778 UNSIGNED ); }}); 1779 0x4: shra_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, 1780 NOROUND, SIGNED, &dspctl ); }}); 1781 0x5: shra_r_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, 1782 ROUND, SIGNED, &dspctl ); }}); 1783 0x6: shrav_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, 1784 NOROUND, SIGNED, &dspctl ); }}); 1785 0x7: shrav_r_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, 1786 ROUND, SIGNED, &dspctl ); }}); 1787 } 1788 } 1789 0x1: decode OP_LO { 1790 format DspIntOp { 1791 0x0: shll_ph({{ Rd.uw = dspShll( Rt.uw, RS, SIMD_FMT_PH, 1792 NOSATURATE, SIGNED, &dspctl ); }}); 1793 0x1: shra_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, 1794 NOROUND, SIGNED, &dspctl ); }}); 1795 0x2: shllv_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, 1796 NOSATURATE, SIGNED, &dspctl ); }}); 1797 0x3: shrav_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, 1798 NOROUND, SIGNED, &dspctl ); }}); 1799 0x4: shll_s_ph({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_PH, 1800 SATURATE, SIGNED, &dspctl ); }}); 1801 0x5: shra_r_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, 1802 ROUND, SIGNED, &dspctl ); }}); 1803 0x6: shllv_s_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, 1804 SATURATE, SIGNED, &dspctl ); }}); 1805 0x7: shrav_r_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, 1806 ROUND, SIGNED, &dspctl ); }}); 1807 } 1808 } 1809 0x2: decode OP_LO { 1810 format DspIntOp { 1811 0x4: shll_s_w({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_W, 1812 SATURATE, SIGNED, &dspctl ); }}); 1813 0x5: shra_r_w({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_W, 1814 ROUND, SIGNED, &dspctl ); }}); 1815 0x6: shllv_s_w({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_W, 1816 SATURATE, SIGNED, &dspctl ); }}); 1817 0x7: shrav_r_w({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_W, 1818 ROUND, SIGNED, &dspctl ); }}); 1819 } 1820 } 1821 0x3: decode OP_LO { 1822 format DspIntOp { 1823 0x1: shrl_ph({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_PH, 1824 UNSIGNED ); }}); 1825 0x3: shrlv_ph({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_PH, 1826 UNSIGNED ); }}); 1827 } 1828 } 1829 } 1830 } 1831 1832 0x3: decode FUNCTION_LO { 1833 1834 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field (DSP ASE Rev2 Manual) 1835 0x0: decode OP_HI { 1836 0x0: decode OP_LO { 1837 format DspIntOp { 1838 0x0: adduh_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1839 NOROUND, UNSIGNED ); }}); 1840 0x1: subuh_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1841 NOROUND, UNSIGNED ); }}); 1842 0x2: adduh_r_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1843 ROUND, UNSIGNED ); }}); 1844 0x3: subuh_r_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1845 ROUND, UNSIGNED ); }}); 1846 } 1847 } 1848 0x1: decode OP_LO { 1849 format DspIntOp { 1850 0x0: addqh_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1851 NOROUND, SIGNED ); }}); 1852 0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1853 NOROUND, SIGNED ); }}); 1854 0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1855 ROUND, SIGNED ); }}); 1856 0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1857 ROUND, SIGNED ); }}); 1858 0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, 1859 NOSATURATE, &dspctl ); }}, IntMultOp); 1860 0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, 1861 SATURATE, &dspctl ); }}, IntMultOp); 1862 1863 } 1864 } 1865 0x2: decode OP_LO { 1866 format DspIntOp { 1867 0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, 1868 NOROUND, SIGNED ); }}); 1869 0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, 1870 NOROUND, SIGNED ); }}); 1871 0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, 1872 ROUND, SIGNED ); }}); 1873 0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, 1874 ROUND, SIGNED ); }}); 1875 0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, 1876 SATURATE, NOROUND, &dspctl ); }}, IntMultOp); 1877 0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, 1878 SATURATE, ROUND, &dspctl ); }}, IntMultOp); 1879 } 1880 } 1881 } 1882 } 1883 1884 //Table A-10 MIPS32 BSHFL Encoding of sa Field 1885 0x4: decode SA { 1886 format BasicOp { 1887 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 | 1888 Rt.uw<31:24> << 16 | 1889 Rt.uw<7:0> << 8 | 1890 Rt.uw<15:8>; 1891 }}); 1892 0x10: seb({{ Rd.sw = Rt.sb; }}); 1893 0x18: seh({{ Rd.sw = Rt.sh; }}); 1894 } 1895 } 1896 1897 0x6: decode FUNCTION_LO { 1898 1899 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL) 1900 0x0: decode OP_HI { 1901 0x0: decode OP_LO { 1902 format DspHiLoOp { 1903 0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1904 SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); 1905 0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1906 SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); 1907 0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw, 1908 ACDST, SIMD_FMT_PH ); }}, IntMultOp); 1909 0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1910 SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); 1911 0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1912 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1913 0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1914 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1915 0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw, 1916 ACDST, SIMD_FMT_PH, &dspctl ); }}, IntMultOp); 1917 0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1918 SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); 1919 } 1920 } 1921 0x1: decode OP_LO { 1922 format DspHiLoOp { 1923 0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1924 SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); 1925 0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1926 SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); 1927 0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1928 SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); 1929 0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, 1930 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1931 0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, 1932 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1933 0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1934 SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); 1935 } 1936 } 1937 0x2: decode OP_LO { 1938 format DspHiLoOp { 1939 0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1940 MODE_L, SATURATE, &dspctl ); }}, IntMultOp); 1941 0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1942 MODE_R, SATURATE, &dspctl ); }}, IntMultOp); 1943 0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1944 MODE_L, NOSATURATE, &dspctl ); }}, IntMultOp); 1945 0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1946 MODE_R, NOSATURATE, &dspctl ); }}, IntMultOp); 1947 } 1948 } 1949 0x3: decode OP_LO { 1950 format DspHiLoOp { 1951 0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1952 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); 1953 0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1954 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); 1955 0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1956 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); 1957 0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1958 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); 1959 } 1960 } 1961 } 1962 1963 //Table 3.3 MIPS32 APPEND Encoding of the op Field 1964 0x1: decode OP_HI { 1965 0x0: decode OP_LO { 1966 format IntOp { 1967 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }}); 1968 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw, RD - 1, 0) << (32 - RD)); }}); 1969 } 1970 } 1971 0x2: decode OP_LO { 1972 format IntOp { 1973 0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }}); 1974 } 1975 } 1976 } 1977 1978 } 1979 0x7: decode FUNCTION_LO { 1980 1981 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL) 1982 0x0: decode OP_HI { 1983 0x0: decode OP_LO { 1984 format DspHiLoOp { 1985 0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 1986 NOROUND, NOSATURATE, &dspctl ); }}); 1987 0x1: extrv_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 1988 NOROUND, NOSATURATE, &dspctl ); }}); 1989 0x2: extp({{ Rt.uw = dspExtp( dspac, RS, &dspctl ); }}); 1990 0x3: extpv({{ Rt.uw = dspExtp( dspac, Rs.uw, &dspctl ); }}); 1991 0x4: extr_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 1992 ROUND, NOSATURATE, &dspctl ); }}); 1993 0x5: extrv_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 1994 ROUND, NOSATURATE, &dspctl ); }}); 1995 0x6: extr_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 1996 ROUND, SATURATE, &dspctl ); }}); 1997 0x7: extrv_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 1998 ROUND, SATURATE, &dspctl ); }}); 1999 } 2000 } 2001 0x1: decode OP_LO { 2002 format DspHiLoOp { 2003 0x2: extpdp({{ Rt.uw = dspExtpd( dspac, RS, &dspctl ); }}); 2004 0x3: extpdpv({{ Rt.uw = dspExtpd( dspac, Rs.uw, &dspctl ); }}); 2005 0x6: extr_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, RS, 2006 NOROUND, SATURATE, &dspctl ); }}); 2007 0x7: extrv_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, Rs.uw, 2008 NOROUND, SATURATE, &dspctl ); }}); 2009 } 2010 } 2011 0x2: decode OP_LO { 2012 format DspIntOp { 2013 0x2: rddsp({{ Rd.uw = readDSPControl( &dspctl, RDDSPMASK ); }}); 2014 0x3: wrdsp({{ writeDSPControl( &dspctl, Rs.uw, WRDSPMASK ); }}); 2015 } 2016 } 2017 0x3: decode OP_LO { 2018 format DspHiLoOp { 2019 0x2: shilo({{ if( sext<6>(HILOSA) < 0 ) 2020 dspac = (uint64_t)dspac << -sext<6>(HILOSA); 2021 else 2022 dspac = (uint64_t)dspac >> sext<6>(HILOSA); }}); 2023 0x3: shilov({{ if( sext<6>(Rs.sw<5:0>) < 0 ) 2024 dspac = (uint64_t)dspac << -sext<6>(Rs.sw<5:0>); 2025 else 2026 dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }}); 2027 0x7: mthlip({{ dspac = dspac << 32; 2028 dspac |= Rs.uw; 2029 dspctl = insertBits( dspctl, 5, 0, 2030 dspctl<5:0>+32 ); }}); 2031 } 2032 } 2033 } 2034 0x3: decode OP_HI { 2035 0x2: decode OP_LO { 2036 0x3: FailUnimpl::rdhwr(); 2037 } 2038 } 2039 } 2040 } 2041 } 2042 2043 0x4: decode OPCODE_LO { 2044 format LoadMemory { 2045 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT); 2046 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 2047 0x3: lw({{ Rt.sw = Mem.sw; }}); 2048 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT); 2049 0x5: lhu({{ Rt.uw = Mem.uh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 2050 } 2051 2052 format LoadUnalignedMemory { 2053 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset); 2054 Rt.uw = mem_word << mem_shift | 2055 (Rt.uw & mask(mem_shift)); 2056 }}); 2057 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset; 2058 Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) | 2059 (mem_word >> mem_shift); 2060 }}); 2061 } 2062 } 2063 2064 0x5: decode OPCODE_LO { 2065 format StoreMemory { 2066 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT); 2067 0x1: sh({{ Mem.uh = Rt<15:0>; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 2068 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 2069 } 2070 2071 format StoreUnalignedMemory { 2072 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset); 2073 uint32_t mem_shift = 32 - reg_shift; 2074 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2075 (Rt.uw >> reg_shift); 2076 }}); 2077 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset; 2078 mem_word = Rt.uw << reg_shift | 2079 (mem_word & (mask(reg_shift))); 2080 }}); 2081 } 2082 format CP0Control { 2083 0x7: cache({{ 2084 //Addr CacheEA = Rs.uw + OFFSET; 2085 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2086 }}); 2087 } 2088 } 2089 2090 0x6: decode OPCODE_LO { 2091 format LoadMemory { 2092 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LLSC); 2093 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 2094 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 2095 } 2096 0x2: CP2Unimpl::lwc2(); 2097 0x6: CP2Unimpl::ldc2(); 2098 0x3: Prefetch::pref(); 2099 } 2100 2101 2102 0x7: decode OPCODE_LO { 2103 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, 2104 {{ uint64_t tmp = write_result; 2105 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; 2106 }}, mem_flags=LLSC, inst_flags = IsStoreConditional); 2107 2108 format StoreMemory { 2109 0x1: swc1({{ Mem.uw = Ft.uw;}}); 2110 0x5: sdc1({{ Mem.ud = Ft.ud;}}); 2111 } 2112 2113 0x2: CP2Unimpl::swc2(); 2114 0x6: CP2Unimpl::sdc2(); 2115 2116 } 2117} 2118 2119 2120