decoder.isa revision 5222:bb733a878f85
1// -*- mode:c++ -*- 2 3// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved 4 5// This software is part of the M5 simulator. 6 7// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 8// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 9// TO THESE TERMS AND CONDITIONS. 10 11// Permission is granted to use, copy, create derivative works and 12// distribute this software and such derivative works for any purpose, 13// so long as (1) the copyright notice above, this grant of permission, 14// and the disclaimer below appear in all copies and derivative works 15// made, (2) the copyright notice above is augmented as appropriate to 16// reflect the addition of any new copyrightable work in a derivative 17// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3) 18// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any 19// advertising or publicity pertaining to the use or distribution of 20// this software without specific, written prior authorization. 21 22// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND 23// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 24// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 26// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 27// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 28// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 29// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 30// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 31// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 32// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 33// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 34 35//Authors: Korey L. Sewell 36// Brett Miller 37// Jaidev Patwardhan 38 39//////////////////////////////////////////////////////////////////// 40// 41// The actual MIPS32 ISA decoder 42// ----------------------------- 43// The following instructions are specified in the MIPS32 ISA 44// Specification. Decoding closely follows the style specified 45// in the MIPS32 ISA specification document starting with Table 46// A-2 (document available @ http://www.mips.com) 47// 48decode OPCODE_HI default Unknown::unknown() { 49 //Table A-2 50 0x0: decode OPCODE_LO { 51 0x0: decode FUNCTION_HI { 52 0x0: decode FUNCTION_LO { 53 0x1: decode MOVCI { 54 format BasicOp { 55 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }}); 56 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }}); 57 } 58 } 59 60 format BasicOp { 61 //Table A-3 Note: "Specific encodings of the rd, rs, and 62 //rt fields are used to distinguish SLL, SSNOP, and EHB 63 //functions 64 0x0: decode RS { 65 0x0: decode RT_RD { 66 0x0: decode SA default Nop::nop() { 67 0x1: ssnop({{;}}); 68 0x3: ehb({{;}}); 69 } 70 default: sll({{ Rd = Rt.uw << SA; }}); 71 } 72 } 73 74 0x2: decode RS_SRL { 75 0x0:decode SRL { 76 0: srl({{ Rd = Rt.uw >> SA; }}); 77 78 //Hardcoded assuming 32-bit ISA, probably need parameter here 79 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 80 } 81 } 82 83 0x3: decode RS { 84 0x0: sra({{ 85 uint32_t temp = Rt >> SA; 86 if ( (Rt & 0x80000000) > 0 ) { 87 uint32_t mask = 0x80000000; 88 for(int i=0; i < SA; i++) { 89 temp |= mask; 90 mask = mask >> 1; 91 } 92 } 93 Rd = temp; 94 }}); 95 } 96 97 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 98 99 0x6: decode SRLV { 100 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 101 102 //Hardcoded assuming 32-bit ISA, probably need parameter here 103 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 104 } 105 106 0x7: srav({{ 107 int shift_amt = Rs<4:0>; 108 109 uint32_t temp = Rt >> shift_amt; 110 111 if ( (Rt & 0x80000000) > 0 ) { 112 uint32_t mask = 0x80000000; 113 for(int i=0; i < shift_amt; i++) { 114 temp |= mask; 115 mask = mask >> 1; 116 } 117 } 118 119 Rd = temp; 120 }}); 121 } 122 } 123 124 0x1: decode FUNCTION_LO { 125 //Table A-3 Note: "Specific encodings of the hint field are 126 //used to distinguish JR from JR.HB and JALR from JALR.HB" 127 format Jump { 128 0x0: decode HINT { 129 0x1: jr_hb({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");}; }}, IsReturn, ClearHazards); 130 default: jr({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");};}}, IsReturn); 131 } 132 133 0x1: decode HINT { 134 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall 135 , ClearHazards); 136 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall); 137 } 138 } 139 140 format BasicOp { 141 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 142 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 143#if FULL_SYSTEM 144 0x4: syscall({{ 145 fault = new SystemCallFault(); 146 }}); 147#else 148 0x4: syscall({{ xc->syscall(R2); }}, 149 IsSerializing, IsNonSpeculative); 150#endif 151 0x7: sync({{ ; }}, IsMemBarrier); 152 0x5: break({{fault = new BreakpointFault();}}); 153 } 154 155 } 156 157 0x2: decode FUNCTION_LO { 158 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess); 159 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); 160 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess); 161 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 162 } 163 164 0x3: decode FUNCTION_LO { 165 format HiLoRdSelValOp { 166 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp); 167 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp); 168 } 169 170 format HiLoOp { 171 0x2: div({{ if (Rt.sd != 0) { 172 HI0 = Rs.sd % Rt.sd; 173 LO0 = Rs.sd / Rt.sd; 174 } 175 }}, IntDivOp); 176 177 0x3: divu({{ if (Rt.ud != 0) { 178 HI0 = Rs.ud % Rt.ud; 179 LO0 = Rs.ud / Rt.ud; 180 } 181 }}, IntDivOp); 182 } 183 } 184 185 0x4: decode HINT { 186 0x0: decode FUNCTION_LO { 187 format IntOp { 188 0x0: add({{ /* More complicated since an ADD can cause an arithmetic overflow exception */ 189 int64_t Src1 = Rs.sw; 190 int64_t Src2 = Rt.sw; 191 int64_t temp_result; 192#if FULL_SYSTEM 193 if(((Src1 >> 31) & 1) == 1) 194 Src1 |= 0x100000000LL; 195#endif 196 temp_result = Src1 + Src2; 197#if FULL_SYSTEM 198 if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ 199#endif 200 Rd.sw = temp_result; 201#if FULL_SYSTEM 202 } else{ 203 fault = new ArithmeticFault(); 204 } 205#endif 206 207 }}); 208 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 209 0x2: sub({{ 210 /* More complicated since an SUB can cause an arithmetic overflow exception */ 211 int64_t Src1 = Rs.sw; 212 int64_t Src2 = Rt.sw; 213 int64_t temp_result = Src1 - Src2; 214#if FULL_SYSTEM 215 if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){ 216#endif 217 Rd.sw = temp_result; 218#if FULL_SYSTEM 219 } else{ 220 fault = new ArithmeticFault(); 221 } 222#endif 223 }}); 224 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 225 0x4: and({{ Rd = Rs & Rt;}}); 226 0x5: or({{ Rd = Rs | Rt;}}); 227 0x6: xor({{ Rd = Rs ^ Rt;}}); 228 0x7: nor({{ Rd = ~(Rs | Rt);}}); 229 } 230 } 231 } 232 233 0x5: decode HINT { 234 0x0: decode FUNCTION_LO { 235 format IntOp{ 236 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 237 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 238 } 239 } 240 } 241 242 0x6: decode FUNCTION_LO { 243 format Trap { 244 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 245 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 246 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 247 0x3: tltu({{ cond = (Rs.uw < Rt.uw); }}); 248 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 249 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 250 } 251 } 252 } 253 254 0x1: decode REGIMM_HI { 255 0x0: decode REGIMM_LO { 256 format Branch { 257 0x0: bltz({{ cond = (Rs.sw < 0); }}); 258 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 259 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely); 260 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely); 261 } 262 } 263 264 0x1: decode REGIMM_LO { 265 format TrapImm { 266 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }}); 267 0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }}); 268 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }}); 269 0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }}); 270 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}}); 271 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}}); 272 } 273 } 274 275 0x2: decode REGIMM_LO { 276 format Branch { 277 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link); 278 0x1: decode RS { 279 0x0: bal ({{ cond = 1; }}, IsCall, Link); 280 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link); 281 } 282 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely); 283 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely); 284 } 285 } 286 287 0x3: decode REGIMM_LO { 288 // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL) 289 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 290 format WarnUnimpl { 291 0x7: synci(); 292 } 293 } 294 } 295 296 format Jump { 297 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 298 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall, 299 Link); 300 } 301 302 format Branch { 303 0x4: decode RS_RT { 304 0x0: b({{ cond = 1; }}); 305 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 306 } 307 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 308 0x6: blez({{ cond = (Rs.sw <= 0); }}); 309 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 310 } 311 } 312 313 0x1: decode OPCODE_LO { 314 format IntImmOp { 315 0x0: addi({{ 316 int64_t Src1 = Rs.sw; 317 int64_t Src2 = imm; 318 int64_t temp_result; 319#if FULL_SYSTEM 320 if(((Src1 >> 31) & 1) == 1) 321 Src1 |= 0x100000000LL; 322#endif 323 temp_result = Src1 + Src2; 324#if FULL_SYSTEM 325 if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ 326#endif 327 Rt.sw = temp_result; 328#if FULL_SYSTEM 329 } else{ 330 fault = new ArithmeticFault(); 331 } 332#endif 333 }}); 334 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 335 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 336 337 //Edited to include MIPS AVP Pass/Fail instructions and 338 //default to the sltiu instruction 339 0x3: decode RS_RT_INTIMM { 340 0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }}); 341 0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }}); 342 default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 343 } 344 345 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 346 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 347 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 348 349 0x7: decode RS { 350 0x0: lui({{ Rt = imm << 16}}); 351 } 352 } 353 } 354 355 0x2: decode OPCODE_LO { 356 //Table A-11 MIPS32 COP0 Encoding of rs Field 357 0x0: decode RS_MSB { 358 0x0: decode RS { 359 format CP0Control { 360 0x0: mfc0({{ Rt = CP0_RD_SEL; 361 /* Hack for PageMask */ 362 if(RD == 5) // PageMask 363 if(Config3_SP == 0 || PageGrain_ESP == 0) 364 Rt &= 0xFFFFE7FF; 365 }}); 366 0x4: mtc0({{ CP0_RD_SEL = Rt; 367 368 if(RD == 11) // Compare{ 369 if(Cause_TI == 1){ 370 Cause_TI = 0; 371 MiscReg cause = xc->readMiscRegNoEffect(MipsISA::Cause); 372 int Offset = 10; // corresponding to Cause_IP0 373 Offset += ((IntCtl_IPTI) - 2); 374 replaceBits(cause,Offset,Offset,0); 375 xc->setMiscRegNoEffect(MipsISA::Cause,cause); 376 } 377 378 }}); 379 } 380 format CP0Unimpl { 381 0x1: dmfc0(); 382 0x5: dmtc0(); 383 default: unknown(); 384 } 385 format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions 386 0x8: decode MT_U { 387 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) + 388 Ctrl_Base_DepTag); 389 }}); 390 0x1: decode SEL { 391 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }}); 392 0x1: decode RT { 393 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }}); 394 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }}); 395 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }}); 396 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }}); 397 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }}); 398 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }}); 399 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }}); 400 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }}); 401 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }}); 402 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }}); 403 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }}); 404 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }}); 405 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }}); 406 default: CP0Unimpl::unknown(); 407 } 408 0x2: decode MT_H { 409 0x0: mftc1({{ data = xc->readRegOtherThread(RT + 410 FP_Base_DepTag); 411 }}); 412 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + 413 FP_Base_DepTag); 414 }}); 415 } 416 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR + 417 FP_Base_DepTag); 418 switch (RT) 419 { 420 case 0: 421 data = xc->readRegOtherThread(MipsISA::FIR + 422 Ctrl_Base_DepTag); 423 break; 424 case 25: 425 data = 0 | fcsr_val & 0xFE000000 >> 24 426 | fcsr_val & 0x00800000 >> 23; 427 break; 428 case 26: 429 data = 0 | fcsr_val & 0x0003F07C; 430 break; 431 case 28: 432 data = 0 | fcsr_val & 0x00000F80 433 | fcsr_val & 0x01000000 >> 21 434 | fcsr_val & 0x00000003; 435 break; 436 case 31: 437 data = fcsr_val; 438 break; 439 default: 440 fatal("FP Control Value (%d) Not Valid"); 441 } 442 }}); 443 default: CP0Unimpl::unknown(); 444 } 445 } 446 } 447 448 format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions 449 0xC: decode MT_U { 450 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, 451 Rt); 452 }}); 453 0x1: decode SEL { 454 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 455 0x1: decode RT { 456 0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt); 457 }}); 458 0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0, 459 Rt); 460 }}); 461 0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0, 462 Rt); 463 }}); 464 0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1, 465 Rt); 466 }}); 467 0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1, 468 Rt); 469 }}); 470 0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1, 471 Rt); 472 }}); 473 0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2, 474 Rt); 475 }}); 476 0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2, 477 Rt); 478 }}); 479 0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2, 480 Rt); 481 }}); 482 0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3, 483 Rt); 484 }}); 485 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3, 486 Rt); 487 }}); 488 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt); 489 }}); 490 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }}); 491 default: CP0Unimpl::unknown(); 492 493 } 494 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + 495 FP_Base_DepTag); 496 data = insertBits(data, top_bit, bottom_bit, Rt); 497 xc->setRegOtherThread(RD + FP_Base_DepTag, data); 498 }}); 499 0x3: cttc1({{ uint32_t data; 500 switch (RD) 501 { 502 case 25: 503 data = 0 | (Rt.uw<7:1> << 25) // move 31...25 504 | (FCSR & 0x01000000) // bit 24 505 | (FCSR & 0x004FFFFF);// bit 22...0 506 break; 507 508 case 26: 509 data = 0 | (FCSR & 0xFFFC0000) // move 31...18 510 | Rt.uw<17:12> << 12 // bit 17...12 511 | (FCSR & 0x00000F80) << 7// bit 11...7 512 | Rt.uw<6:2> << 2 // bit 6...2 513 | (FCSR & 0x00000002); // bit 1...0 514 break; 515 516 case 28: 517 data = 0 | (FCSR & 0xFE000000) // move 31...25 518 | Rt.uw<2:2> << 24 // bit 24 519 | (FCSR & 0x00FFF000) << 23// bit 23...12 520 | Rt.uw<11:7> << 7 // bit 24 521 | (FCSR & 0x000007E) 522 | Rt.uw<1:0>;// bit 22...0 523 break; 524 525 case 31: 526 data = Rt.uw; 527 break; 528 529 default: 530 panic("FP Control Value (%d) Not Available. Ignoring Access to" 531 "Floating Control Status Register", FS); 532 } 533 xc->setRegOtherThread(FCSR, data); 534 }}); 535 default: CP0Unimpl::unknown(); 536 } 537 } 538 } 539 540 541 0xB: decode RD { 542 format MT_Control { 543 0x0: decode POS { 544 0x0: decode SEL { 545 0x1: decode SC { 546 0x0: dvpe({{ Rt = MVPControl; 547 if (VPEConf0<VPEC0_MVP:> == 1) { 548 MVPControl = insertBits(MVPControl, MVPC_EVP, 0); 549 } 550 }}); 551 0x1: evpe({{ Rt = MVPControl; 552 if (VPEConf0<VPEC0_MVP:> == 1) { 553 MVPControl = insertBits(MVPControl, MVPC_EVP, 1); 554 } 555 }}); 556 default:CP0Unimpl::unknown(); 557 } 558 default:CP0Unimpl::unknown(); 559 } 560 default:CP0Unimpl::unknown(); 561 } 562 563 0x1: decode POS { 564 0xF: decode SEL { 565 0x1: decode SC { 566 0x0: dmt({{ Rt = VPEControl; 567 VPEControl = insertBits(VPEControl, VPEC_TE, 0); 568 }}); 569 0x1: emt({{ Rt = VPEControl; 570 VPEControl = insertBits(VPEControl, VPEC_TE, 1); 571 }}); 572 default:CP0Unimpl::unknown(); 573 } 574 default:CP0Unimpl::unknown(); 575 } 576 default:CP0Unimpl::unknown(); 577 } 578 } 579 0xC: decode POS { 580 0x0: decode SC { 581 0x0: CP0Control::di({{ 582 if(Config_AR >= 1) // Rev 2.0 or beyond? 583 { 584 Rt = Status; 585 Status_IE = 0; 586 } 587 else // Enable this else branch once we actually set values for Config on init 588 { 589 fault = new ReservedInstructionFault(); 590 } 591 }}); 592 0x1: CP0Control::ei({{ 593 if(Config_AR >= 1) 594 { 595 Rt = Status; 596 Status_IE = 1; 597 } 598 else 599 { 600 fault = new ReservedInstructionFault(); 601 } 602 }}); 603 default:CP0Unimpl::unknown(); 604 } 605 } 606 default: CP0Unimpl::unknown(); 607 } 608 format CP0Control { 609 0xA: rdpgpr({{ 610 if(Config_AR >= 1) 611 { // Rev 2 of the architecture 612 Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS); 613 } 614 else 615 { 616 fault = new ReservedInstructionFault(); 617 } 618 }}); 619 0xE: wrpgpr({{ 620 if(Config_AR >= 1) 621 { // Rev 2 of the architecture 622 xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt); 623 // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl); 624 } 625 else 626 { 627 fault = new ReservedInstructionFault(); 628 } 629 630 }}); 631 } 632 633 } 634 635 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 636 0x1: decode FUNCTION { 637 format CP0Control { 638 0x18: eret({{ 639 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 640 // Ugly hack to get the value of Status_EXL 641 if(Status_EXL == 1){ 642 DPRINTF(MipsPRA,"ERET EXL Hack\n"); 643 } 644 if(Status_ERL == 1){ 645 Status_ERL = 0; 646 NPC = ErrorEPC; 647 NNPC = ErrorEPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break 648 } 649 else { 650 NPC = EPC; 651 NNPC = EPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break 652 Status_EXL = 0; 653 if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){ 654 SRSCtl_CSS = SRSCtl_PSS; 655 xc->setShadowSet(SRSCtl_PSS); 656 } 657 } 658 LLFlag = 0; 659 }},IsReturn,IsSerializing,IsERET); 660 661 0x1F: deret({{ 662 // if(EJTagImplemented()) { 663 if(Debug_DM == 1){ 664 Debug_DM = 1; 665 Debug_IEXI = 0; 666 NPC = DEPC; 667 } 668 else 669 { 670 // Undefined; 671 } 672 //} // EJTag Implemented 673 //else { 674 // Reserved Instruction Exception 675 //} 676 }},IsReturn,IsSerializing,IsERET); 677 } 678 format CP0TLB { 679 0x01: tlbr({{ 680 MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF); 681 if(PTEntry == NULL) 682 { 683 fatal("Invalid PTE Entry received on a TLBR instruction\n"); 684 } 685 /* Setup PageMask */ 686 PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11 687 /* Setup EntryHi */ 688 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 689 /* Setup Entry Lo0 */ 690 EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G); 691 /* Setup Entry Lo1 */ 692 EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G); 693 }}); // Need to hook up to TLB 694 695 0x02: tlbwi({{ 696 //Create PTE 697 MipsISA::PTE NewEntry; 698 //Write PTE 699 NewEntry.Mask = (Addr)(PageMask >> 11); 700 NewEntry.VPN = (Addr)(EntryHi >> 11); 701 /* PageGrain _ ESP Config3 _ SP */ 702 if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) { 703 NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes 704 NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled 705 } 706 NewEntry.asid = (uint8_t)(EntryHi & 0xFF); 707 708 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); 709 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); 710 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 711 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 712 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 713 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 714 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 715 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 716 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 717 /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */ 718 /* Addr Shift Amount for 1KB or larger pages */ 719 // warn("PTE->Mask: %x\n",pte->Mask); 720 if((NewEntry.Mask & 0xFFFF) == 3){ 721 NewEntry.AddrShiftAmount = 12; 722 } else if((NewEntry.Mask & 0xFFFF) == 0x0000){ 723 NewEntry.AddrShiftAmount = 10; 724 } else if((NewEntry.Mask & 0xFFFC) == 0x000C){ 725 NewEntry.AddrShiftAmount = 14; 726 } else if((NewEntry.Mask & 0xFFF0) == 0x0030){ 727 NewEntry.AddrShiftAmount = 16; 728 } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){ 729 NewEntry.AddrShiftAmount = 18; 730 } else if((NewEntry.Mask & 0xFF00) == 0x0300){ 731 NewEntry.AddrShiftAmount = 20; 732 } else if((NewEntry.Mask & 0xFC00) == 0x0C00){ 733 NewEntry.AddrShiftAmount = 22; 734 } else if((NewEntry.Mask & 0xF000) == 0x3000){ 735 NewEntry.AddrShiftAmount = 24; 736 } else if((NewEntry.Mask & 0xC000) == 0xC000){ 737 NewEntry.AddrShiftAmount = 26; 738 } else if((NewEntry.Mask & 0x30000) == 0x30000){ 739 NewEntry.AddrShiftAmount = 28; 740 } else { 741 fatal("Invalid Mask Pattern Detected!\n"); 742 } 743 NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1); 744 745 MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr(); 746 MiscReg c3=xc->readMiscReg(MipsISA::Config3); 747 MiscReg pg=xc->readMiscReg(MipsISA::PageGrain); 748 int SP=0; 749 if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){ 750 SP=1; 751 } 752 Ptr->insertAt(NewEntry,Index & 0x7FFFFFFF,SP); 753 }}); 754 0x06: tlbwr({{ 755 //Create PTE 756 MipsISA::PTE NewEntry; 757 //Write PTE 758 NewEntry.Mask = (Addr)(PageMask >> 11); 759 NewEntry.VPN = (Addr)(EntryHi >> 11); 760 /* PageGrain _ ESP Config3 _ SP */ 761 if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) { 762 NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes 763 NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled 764 } 765 NewEntry.asid = (uint8_t)(EntryHi & 0xFF); 766 767 NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); 768 NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); 769 NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 770 NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 771 NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 772 NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 773 NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 774 NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 775 NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 776 /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */ 777 /* Addr Shift Amount for 1KB or larger pages */ 778 // warn("PTE->Mask: %x\n",pte->Mask); 779 if((NewEntry.Mask & 0xFFFF) == 3){ 780 NewEntry.AddrShiftAmount = 12; 781 } else if((NewEntry.Mask & 0xFFFF) == 0x0000){ 782 NewEntry.AddrShiftAmount = 10; 783 } else if((NewEntry.Mask & 0xFFFC) == 0x000C){ 784 NewEntry.AddrShiftAmount = 14; 785 } else if((NewEntry.Mask & 0xFFF0) == 0x0030){ 786 NewEntry.AddrShiftAmount = 16; 787 } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){ 788 NewEntry.AddrShiftAmount = 18; 789 } else if((NewEntry.Mask & 0xFF00) == 0x0300){ 790 NewEntry.AddrShiftAmount = 20; 791 } else if((NewEntry.Mask & 0xFC00) == 0x0C00){ 792 NewEntry.AddrShiftAmount = 22; 793 } else if((NewEntry.Mask & 0xF000) == 0x3000){ 794 NewEntry.AddrShiftAmount = 24; 795 } else if((NewEntry.Mask & 0xC000) == 0xC000){ 796 NewEntry.AddrShiftAmount = 26; 797 } else if((NewEntry.Mask & 0x30000) == 0x30000){ 798 NewEntry.AddrShiftAmount = 28; 799 } else { 800 fatal("Invalid Mask Pattern Detected!\n"); 801 } 802 NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1); 803 804 MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr(); 805 MiscReg c3=xc->readMiscReg(MipsISA::Config3); 806 MiscReg pg=xc->readMiscReg(MipsISA::PageGrain); 807 int SP=0; 808 if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){ 809 SP=1; 810 } 811 Ptr->insertAt(NewEntry,Random,SP); 812 }}); 813 814 0x08: tlbp({{ 815 int TLB_Index; 816 Addr VPN; 817 if(PageGrain_ESP == 1 && Config3_SP ==1){ 818 VPN = EntryHi >> 11; 819 } else { 820 VPN = ((EntryHi >> 11) & 0xFFFFFFFC); // Mask off lower 2 bits 821 } 822 TLB_Index = xc->tcBase()->getITBPtr()->probeEntry(VPN,EntryHi_ASID); 823 if(TLB_Index != -1){ // Check TLB for entry matching EntryHi 824 Index=TLB_Index; 825 // warn("\ntlbp: Match Found!\n"); 826 } else {// else, set Index = 1<<31 827 Index = (1<<31); 828 } 829 }}); 830 } 831 format CP0Unimpl { 832 0x20: wait(); 833 } 834 default: CP0Unimpl::unknown(); 835 836 } 837 } 838 839 //Table A-13 MIPS32 COP1 Encoding of rs Field 840 0x1: decode RS_MSB { 841 842 0x0: decode RS_HI { 843 0x0: decode RS_LO { 844 format CP1Control { 845 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 846 847 0x2: cfc1({{ 848 switch (FS) 849 { 850 case 0: 851 Rt = FIR; 852 break; 853 case 25: 854 Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23; 855 break; 856 case 26: 857 Rt = 0 | (FCSR & 0x0003F07C); 858 break; 859 case 28: 860 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003); 861 break; 862 case 31: 863 Rt = FCSR; 864 break; 865 default: 866 warn("FP Control Value (%d) Not Valid"); 867 } 868 // warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt); 869 }}); 870 871 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 872 873 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 874 875 0x6: ctc1({{ 876 switch (FS) 877 { 878 case 25: 879 FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25 880 | (FCSR & 0x01000000) // bit 24 881 | (FCSR & 0x004FFFFF);// bit 22...0 882 break; 883 884 case 26: 885 FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18 886 | Rt.uw<17:12> << 12 // bit 17...12 887 | (FCSR & 0x00000F80) << 7// bit 11...7 888 | Rt.uw<6:2> << 2 // bit 6...2 889 | (FCSR & 0x00000002); // bit 1...0 890 break; 891 892 case 28: 893 FCSR = 0 | (FCSR & 0xFE000000) // move 31...25 894 | Rt.uw<2:2> << 24 // bit 24 895 | (FCSR & 0x00FFF000) << 23// bit 23...12 896 | Rt.uw<11:7> << 7 // bit 24 897 | (FCSR & 0x000007E) 898 | Rt.uw<1:0>;// bit 22...0 899 break; 900 901 case 31: 902 FCSR = Rt.uw; 903 break; 904 905 default: 906 panic("FP Control Value (%d) Not Available. Ignoring Access to" 907 "Floating Control Status Register", FS); 908 } 909 }}); 910 911 0x7: mthc1({{ 912 uint64_t fs_hi = Rt.uw; 913 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 914 Fs.ud = (fs_hi << 32) | fs_lo; 915 }}); 916 917 } 918 format CP1Unimpl { 919 0x1: dmfc1(); 920 0x5: dmtc1(); 921 } 922 } 923 924 0x1: 925 decode RS_LO { 926 0x0: 927 decode ND { 928 format Branch { 929 0x0: decode TF { 930 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 931 }}); 932 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 933 }}); 934 } 935 0x1: decode TF { 936 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 937 }}, Likely); 938 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 939 }}, Likely); 940 } 941 } 942 } 943 format CP1Unimpl { 944 0x1: bc1any2(); 945 0x2: bc1any4(); 946 default: unknown(); 947 } 948 } 949 } 950 951 0x1: decode RS_HI { 952 0x2: decode RS_LO { 953 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 954 //(( single-precision floating point)) 955 0x0: decode FUNCTION_HI { 956 0x0: decode FUNCTION_LO { 957 format FloatOp { 958 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 959 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 960 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 961 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 962 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 963 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 964 0x7: neg_s({{ Fd.sf = -Fs.sf;}}); 965 } 966 967 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}}); 968 } 969 970 0x1: decode FUNCTION_LO { 971 format FloatConvertOp { 972 0x0: round_l_s({{ val = Fs.sf; }}, ToLong, 973 Round); 974 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong, 975 Trunc); 976 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong, 977 Ceil); 978 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong, 979 Floor); 980 0x4: round_w_s({{ val = Fs.sf; }}, ToWord, 981 Round); 982 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord, 983 Trunc); 984 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord, 985 Ceil); 986 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord, 987 Floor); 988 } 989 } 990 991 0x2: decode FUNCTION_LO { 992 0x1: decode MOVCF { 993 format BasicOp { 994 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }}); 995 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }}); 996 } 997 } 998 999 format BasicOp { 1000 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1001 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1002 } 1003 1004 format FloatOp { 1005 0x5: recip_s({{ Fd = 1 / Fs; }}); 1006 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); 1007 } 1008 format CP1Unimpl { 1009 default: unknown(); 1010 } 1011 } 1012 0x3: CP1Unimpl::unknown(); 1013 1014 0x4: decode FUNCTION_LO { 1015 format FloatConvertOp { 1016 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 1017 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 1018 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 1019 } 1020 1021 0x6: FloatOp::cvt_ps_s({{ 1022 Fd.ud = (uint64_t) Fs.uw << 32 | 1023 (uint64_t) Ft.uw; 1024 }}); 1025 format CP1Unimpl { 1026 default: unknown(); 1027 } 1028 } 1029 0x5: CP1Unimpl::unknown(); 1030 1031 0x6: decode FUNCTION_LO { 1032 format FloatCompareOp { 1033 0x0: c_f_s({{ cond = 0; }}, SinglePrecision, 1034 UnorderedFalse); 1035 0x1: c_un_s({{ cond = 0; }}, SinglePrecision, 1036 UnorderedTrue); 1037 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 1038 UnorderedFalse); 1039 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 1040 UnorderedTrue); 1041 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 1042 UnorderedFalse); 1043 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 1044 UnorderedTrue); 1045 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }}, 1046 UnorderedFalse); 1047 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }}, 1048 UnorderedTrue); 1049 } 1050 } 1051 1052 0x7: decode FUNCTION_LO { 1053 format FloatCompareOp { 1054 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1055 UnorderedFalse, QnanException); 1056 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1057 UnorderedTrue, QnanException); 1058 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}}, 1059 UnorderedFalse, QnanException); 1060 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 1061 UnorderedTrue, QnanException); 1062 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 1063 UnorderedFalse, QnanException); 1064 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 1065 UnorderedTrue, QnanException); 1066 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 1067 UnorderedFalse, QnanException); 1068 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 1069 UnorderedTrue, QnanException); 1070 } 1071 } 1072 } 1073 1074 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 1075 0x1: decode FUNCTION_HI { 1076 0x0: decode FUNCTION_LO { 1077 format FloatOp { 1078 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 1079 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 1080 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 1081 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); 1082 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 1083 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 1084 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); 1085 } 1086 1087 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); 1088 } 1089 1090 0x1: decode FUNCTION_LO { 1091 format FloatConvertOp { 1092 0x0: round_l_d({{ val = Fs.df; }}, ToLong, 1093 Round); 1094 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong, 1095 Trunc); 1096 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong, 1097 Ceil); 1098 0x3: floor_l_d({{ val = Fs.df; }}, ToLong, 1099 Floor); 1100 0x4: round_w_d({{ val = Fs.df; }}, ToWord, 1101 Round); 1102 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord, 1103 Trunc); 1104 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord, 1105 Ceil); 1106 0x7: floor_w_d({{ val = Fs.df; }}, ToWord, 1107 Floor); 1108 } 1109 } 1110 1111 0x2: decode FUNCTION_LO { 1112 0x1: decode MOVCF { 1113 format BasicOp { 1114 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ? 1115 Fs.df : Fd.df; 1116 }}); 1117 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ? 1118 Fs.df : Fd.df; 1119 }}); 1120 } 1121 } 1122 1123 format BasicOp { 1124 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }}); 1125 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }}); 1126 } 1127 1128 format FloatOp { 1129 0x5: recip_d({{ Fd.df = 1 / Fs.df }}); 1130 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }}); 1131 } 1132 format CP1Unimpl { 1133 default: unknown(); 1134 } 1135 1136 } 1137 0x4: decode FUNCTION_LO { 1138 format FloatConvertOp { 1139 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 1140 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 1141 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 1142 } 1143 default: CP1Unimpl::unknown(); 1144 } 1145 1146 0x6: decode FUNCTION_LO { 1147 format FloatCompareOp { 1148 0x0: c_f_d({{ cond = 0; }}, DoublePrecision, 1149 UnorderedFalse); 1150 0x1: c_un_d({{ cond = 0; }}, DoublePrecision, 1151 UnorderedTrue); 1152 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 1153 UnorderedFalse); 1154 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 1155 UnorderedTrue); 1156 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 1157 UnorderedFalse); 1158 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 1159 UnorderedTrue); 1160 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }}, 1161 UnorderedFalse); 1162 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }}, 1163 UnorderedTrue); 1164 } 1165 } 1166 1167 0x7: decode FUNCTION_LO { 1168 format FloatCompareOp { 1169 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1170 UnorderedFalse, QnanException); 1171 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1172 UnorderedTrue, QnanException); 1173 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }}, 1174 UnorderedFalse, QnanException); 1175 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }}, 1176 UnorderedTrue, QnanException); 1177 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }}, 1178 UnorderedFalse, QnanException); 1179 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 1180 UnorderedTrue, QnanException); 1181 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 1182 UnorderedFalse, QnanException); 1183 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 1184 UnorderedTrue, QnanException); 1185 } 1186 } 1187 default: CP1Unimpl::unknown(); 1188 } 1189 0x2: CP1Unimpl::unknown(); 1190 0x3: CP1Unimpl::unknown(); 1191 0x7: CP1Unimpl::unknown(); 1192 1193 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 1194 0x4: decode FUNCTION { 1195 format FloatConvertOp { 1196 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 1197 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 1198 0x26: CP1Unimpl::cvt_ps_w(); 1199 } 1200 default: CP1Unimpl::unknown(); 1201 } 1202 1203 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 1204 //Note: "1. Format type L is legal only if 64-bit floating point operations 1205 //are enabled." 1206 0x5: decode FUNCTION_HI { 1207 format FloatConvertOp { 1208 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 1209 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 1210 0x26: CP1Unimpl::cvt_ps_l(); 1211 } 1212 default: CP1Unimpl::unknown(); 1213 } 1214 1215 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 1216 //Note: "1. Format type PS is legal only if 64-bit floating point operations 1217 //are enabled. " 1218 0x6: decode FUNCTION_HI { 1219 0x0: decode FUNCTION_LO { 1220 format Float64Op { 1221 0x0: add_ps({{ 1222 Fd1.sf = Fs1.sf + Ft2.sf; 1223 Fd2.sf = Fs2.sf + Ft2.sf; 1224 }}); 1225 0x1: sub_ps({{ 1226 Fd1.sf = Fs1.sf - Ft2.sf; 1227 Fd2.sf = Fs2.sf - Ft2.sf; 1228 }}); 1229 0x2: mul_ps({{ 1230 Fd1.sf = Fs1.sf * Ft2.sf; 1231 Fd2.sf = Fs2.sf * Ft2.sf; 1232 }}); 1233 0x5: abs_ps({{ 1234 Fd1.sf = fabs(Fs1.sf); 1235 Fd2.sf = fabs(Fs2.sf); 1236 }}); 1237 0x6: mov_ps({{ 1238 Fd1.sf = Fs1.sf; 1239 Fd2.sf = Fs2.sf; 1240 }}); 1241 0x7: neg_ps({{ 1242 Fd1.sf = -(Fs1.sf); 1243 Fd2.sf = -(Fs2.sf); 1244 }}); 1245 default: CP1Unimpl::unknown(); 1246 } 1247 } 1248 0x1: CP1Unimpl::unknown(); 1249 0x2: decode FUNCTION_LO { 1250 0x1: decode MOVCF { 1251 format Float64Op { 1252 0x0: movf_ps({{ 1253 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1254 Fs1 : Fd1; 1255 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1256 Fs2 : Fd2; 1257 }}); 1258 0x1: movt_ps({{ 1259 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1260 Fs1 : Fd1; 1261 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1262 Fs2 : Fd2; 1263 }}); 1264 } 1265 } 1266 1267 format Float64Op { 1268 0x2: movz_ps({{ 1269 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1270 Fs1 : Fd1; 1271 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1272 Fs2 : Fd2; 1273 }}); 1274 0x3: movn_ps({{ 1275 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1276 Fs1 : Fd1; 1277 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1278 Fs2 : Fd2; 1279 }}); 1280 } 1281 default: CP1Unimpl::unknown(); 1282 1283 } 1284 0x3: CP1Unimpl::unknown(); 1285 0x4: decode FUNCTION_LO { 1286 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 1287 default: CP1Unimpl::unknown(); 1288 } 1289 1290 0x5: decode FUNCTION_LO { 1291 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); 1292 1293 format Float64Op { 1294 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 1295 Ft1.uw; 1296 }}); 1297 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 1298 Ft2.uw; 1299 }}); 1300 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 1301 Ft1.uw; 1302 }}); 1303 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 1304 Ft2.uw; 1305 }}); 1306 } 1307 default: CP1Unimpl::unknown(); 1308 } 1309 1310 0x6: decode FUNCTION_LO { 1311 format FloatPSCompareOp { 1312 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1313 UnorderedFalse); 1314 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1315 UnorderedTrue); 1316 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1317 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1318 UnorderedFalse); 1319 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1320 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1321 UnorderedTrue); 1322 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1323 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1324 UnorderedFalse); 1325 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }}, 1326 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1327 UnorderedTrue); 1328 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }}, 1329 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1330 UnorderedFalse); 1331 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1332 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1333 UnorderedTrue); 1334 } 1335 } 1336 1337 0x7: decode FUNCTION_LO { 1338 format FloatPSCompareOp { 1339 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1340 UnorderedFalse, QnanException); 1341 0x1: c_ngle_ps({{ cond1 = 0; }}, 1342 {{ cond2 = 0; }}, 1343 UnorderedTrue, QnanException); 1344 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1345 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1346 UnorderedFalse, QnanException); 1347 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 1348 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 1349 UnorderedTrue, QnanException); 1350 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1351 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1352 UnorderedFalse, QnanException); 1353 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 1354 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 1355 UnorderedTrue, QnanException); 1356 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1357 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1358 UnorderedFalse, QnanException); 1359 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 1360 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 1361 UnorderedTrue, QnanException); 1362 } 1363 } 1364 } 1365 } 1366 default: CP1Unimpl::unknown(); 1367 } 1368 } 1369 1370 //Table A-19 MIPS32 COP2 Encoding of rs Field 1371 0x2: decode RS_MSB { 1372 format CP2Unimpl { 1373 0x0: decode RS_HI { 1374 0x0: decode RS_LO { 1375 0x0: mfc2(); 1376 0x2: cfc2(); 1377 0x3: mfhc2(); 1378 0x4: mtc2(); 1379 0x6: ctc2(); 1380 0x7: mftc2(); 1381 default: unknown(); 1382 } 1383 1384 0x1: decode ND { 1385 0x0: decode TF { 1386 0x0: bc2f(); 1387 0x1: bc2t(); 1388 default: unknown(); 1389 } 1390 1391 0x1: decode TF { 1392 0x0: bc2fl(); 1393 0x1: bc2tl(); 1394 default: unknown(); 1395 } 1396 default: unknown(); 1397 1398 } 1399 default: unknown(); 1400 1401 } 1402 default: unknown(); 1403 } 1404 } 1405 1406 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1407 //Note: "COP1X instructions are legal only if 64-bit floating point 1408 //operations are enabled." 1409 0x3: decode FUNCTION_HI { 1410 0x0: decode FUNCTION_LO { 1411 format LoadIndexedMemory { 1412 0x0: lwxc1({{ Fd.uw = Mem.uw;}}); 1413 0x1: ldxc1({{ Fd.ud = Mem.ud;}}); 1414 0x5: luxc1({{ Fd.ud = Mem.ud;}}, 1415 {{ EA = (Rs + Rt) & ~7; }}); 1416 } 1417 } 1418 1419 0x1: decode FUNCTION_LO { 1420 format StoreIndexedMemory { 1421 0x0: swxc1({{ Mem.uw = Fs.uw;}}); 1422 0x1: sdxc1({{ Mem.ud = Fs.ud;}}); 1423 0x5: suxc1({{ Mem.ud = Fs.ud;}}, 1424 {{ EA = (Rs + Rt) & ~7; }}); 1425 } 1426 1427 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1428 } 1429 1430 0x3: decode FUNCTION_LO { 1431 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) { 1432 Fd.ud = Fs.ud; 1433 } else if (Rs<2:0> == 4) { 1434 #if BYTE_ORDER == BIG_ENDIAN 1435 Fd.ud = Fs.ud<31:0> << 32 | 1436 Ft.ud<63:32>; 1437 #elif BYTE_ORDER == LITTLE_ENDIAN 1438 Fd.ud = Ft.ud<31:0> << 32 | 1439 Fs.ud<63:32>; 1440 #endif 1441 } else { 1442 Fd.ud = Fd.ud; 1443 } 1444 }}); 1445 } 1446 1447 format FloatAccOp { 1448 0x4: decode FUNCTION_LO { 1449 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 1450 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 1451 0x6: madd_ps({{ 1452 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; 1453 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; 1454 }}); 1455 } 1456 1457 0x5: decode FUNCTION_LO { 1458 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); 1459 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 1460 0x6: msub_ps({{ 1461 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; 1462 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; 1463 }}); 1464 } 1465 1466 0x6: decode FUNCTION_LO { 1467 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1468 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 1469 0x6: nmadd_ps({{ 1470 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df); 1471 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df); 1472 }}); 1473 } 1474 1475 0x7: decode FUNCTION_LO { 1476 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 1477 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 1478 0x6: nmsub_ps({{ 1479 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 1480 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 1481 }}); 1482 } 1483 1484 } 1485 } 1486 1487 format Branch { 1488 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 1489 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 1490 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 1491 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 1492 } 1493 } 1494 1495 0x3: decode OPCODE_LO { 1496 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1497 0x4: decode FUNCTION_HI { 1498 0x0: decode FUNCTION_LO { 1499 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd; 1500 Rd.sw = temp1<31:0>; 1501 }}, IntMultOp); 1502 1503 format HiLoRdSelValOp { 1504 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}, IntMultOp); 1505 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}, IntMultOp); 1506 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}, IntMultOp); 1507 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}, IntMultOp); 1508 } 1509 } 1510 1511 0x4: decode FUNCTION_LO { 1512 format BasicOp { 1513 0x0: clz({{ int cnt = 32; 1514 for (int idx = 31; idx >= 0; idx--) { 1515 if( Rs<idx:idx> == 1) { 1516 cnt = 31 - idx; 1517 break; 1518 } 1519 } 1520 Rd.uw = cnt; 1521 }}); 1522 0x1: clo({{ int cnt = 32; 1523 for (int idx = 31; idx >= 0; idx--) { 1524 if( Rs<idx:idx> == 0) { 1525 cnt = 31 - idx; 1526 break; 1527 } 1528 } 1529 Rd.uw = cnt; 1530 }}); 1531 } 1532 } 1533 1534 0x7: decode FUNCTION_LO { 1535 0x7: FailUnimpl::sdbbp(); 1536 } 1537 } 1538 1539 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1540 //of the Architecture 1541 0x7: decode FUNCTION_HI { 1542 0x0: decode FUNCTION_LO { 1543 format BasicOp { 1544 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); 1545 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 1546 bits(Rs.uw, MSB-LSB, 0) << LSB | 1547 bits(Rt.uw, LSB-1, 0); 1548 }}); 1549 } 1550 } 1551 1552 0x1: decode FUNCTION_LO { 1553 format MT_Control { 1554 0x0: fork({{ forkThread(xc->tcBase(), fault, RD, Rs, Rt); }}, 1555 UserMode); 1556 0x1: yield({{ Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, YQMask); }}, 1557 UserMode); 1558 } 1559 1560 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1561 0x2: decode OP_HI { 1562 0x0: decode OP_LO { 1563 format LoadIndexedMemory { 1564 0x0: lwx({{ Rd.sw = Mem.sw; }}); 1565 0x4: lhx({{ Rd.sw = Mem.sh; }}); 1566 0x6: lbux({{ Rd.uw = Mem.ub; }}); 1567 } 1568 } 1569 } 1570 0x4: DspIntOp::insv({{ int pos = dspctl<5:0>; 1571 int size = dspctl<12:7>-1; 1572 Rt.uw = insertBits( Rt.uw, pos+size, pos, Rs.uw<size:0> ); }}); 1573 } 1574 1575 0x2: decode FUNCTION_LO { 1576 1577 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field (DSP ASE MANUAL) 1578 0x0: decode OP_HI { 1579 0x0: decode OP_LO { 1580 format DspIntOp { 1581 0x0: addu_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1582 NOSATURATE, UNSIGNED, &dspctl ); }}); 1583 0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, 1584 NOSATURATE, UNSIGNED, &dspctl ); }}); 1585 0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1586 SATURATE, UNSIGNED, &dspctl ); }}); 1587 0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, 1588 SATURATE, UNSIGNED, &dspctl ); }}); 1589 0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, 1590 MODE_L, &dspctl ); }}, IntMultOp); 1591 0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, 1592 MODE_R, &dspctl ); }}, IntMultOp); 1593 } 1594 } 1595 0x1: decode OP_LO { 1596 format DspIntOp { 1597 0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1598 NOSATURATE, UNSIGNED, &dspctl ); }}); 1599 0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1600 NOSATURATE, UNSIGNED, &dspctl ); }}); 1601 0x2: addq_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1602 NOSATURATE, SIGNED, &dspctl ); }}); 1603 0x3: subq_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1604 NOSATURATE, SIGNED, &dspctl ); }}); 1605 0x4: addu_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1606 SATURATE, UNSIGNED, &dspctl ); }}); 1607 0x5: subu_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1608 SATURATE, UNSIGNED, &dspctl ); }}); 1609 0x6: addq_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 1610 SATURATE, SIGNED, &dspctl ); }}); 1611 0x7: subq_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 1612 SATURATE, SIGNED, &dspctl ); }}); 1613 } 1614 } 1615 0x2: decode OP_LO { 1616 format DspIntOp { 1617 0x0: addsc({{ int64_t dresult; 1618 dresult = Rs.ud + Rt.ud; 1619 Rd.sw = dresult<31:0>; 1620 dspctl = insertBits( dspctl, 13, 13, 1621 dresult<32:32> ); }}); 1622 0x1: addwc({{ int64_t dresult; 1623 dresult = Rs.sd + Rt.sd + dspctl<13:13>; 1624 Rd.sw = dresult<31:0>; 1625 if( dresult<32:32> != dresult<31:31> ) 1626 dspctl = insertBits( dspctl, 20, 20, 1 ); }}); 1627 0x2: modsub({{ Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : Rs.sw - Rt.sw<7:0>; }}); 1628 0x4: raddu_w_qb({{ Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + 1629 Rs.uw<15:8> + Rs.uw<7:0>; }}); 1630 0x6: addq_s_w({{ Rd.sw = dspAdd( Rs.sw, Rt.sw, SIMD_FMT_W, 1631 SATURATE, SIGNED, &dspctl ); }}); 1632 0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W, 1633 SATURATE, SIGNED, &dspctl ); }}); 1634 } 1635 } 1636 0x3: decode OP_LO { 1637 format DspIntOp { 1638 0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, 1639 MODE_L, &dspctl ); }}, IntMultOp); 1640 0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, 1641 MODE_R, &dspctl ); }}, IntMultOp); 1642 0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, 1643 SATURATE, NOROUND, &dspctl ); }}, IntMultOp); 1644 0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, 1645 SATURATE, ROUND, &dspctl ); }}, IntMultOp); 1646 } 1647 } 1648 } 1649 1650 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL) 1651 0x1: decode OP_HI { 1652 0x0: decode OP_LO { 1653 format DspIntOp { 1654 0x0: cmpu_eq_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1655 UNSIGNED, CMP_EQ, &dspctl ); }}); 1656 0x1: cmpu_lt_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1657 UNSIGNED, CMP_LT, &dspctl ); }}); 1658 0x2: cmpu_le_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 1659 UNSIGNED, CMP_LE, &dspctl ); }}); 1660 0x3: pick_qb({{ Rd.uw = dspPick( Rs.uw, Rt.uw, 1661 SIMD_FMT_QB, &dspctl ); }}); 1662 0x4: cmpgu_eq_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1663 UNSIGNED, CMP_EQ ); }}); 1664 0x5: cmpgu_lt_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1665 UNSIGNED, CMP_LT ); }}); 1666 0x6: cmpgu_le_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 1667 UNSIGNED, CMP_LE ); }}); 1668 } 1669 } 1670 0x1: decode OP_LO { 1671 format DspIntOp { 1672 0x0: cmp_eq_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1673 SIGNED, CMP_EQ, &dspctl ); }}); 1674 0x1: cmp_lt_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1675 SIGNED, CMP_LT, &dspctl ); }}); 1676 0x2: cmp_le_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 1677 SIGNED, CMP_LE, &dspctl ); }}); 1678 0x3: pick_ph({{ Rd.uw = dspPick( Rs.uw, Rt.uw, 1679 SIMD_FMT_PH, &dspctl ); }}); 1680 0x4: precrq_qb_ph({{ Rd.uw = Rs.uw<31:24> << 24 | 1681 Rs.uw<15:8> << 16 | 1682 Rt.uw<31:24> << 8 | 1683 Rt.uw<15:8>; }}); 1684 0x5: precr_qb_ph({{ Rd.uw = Rs.uw<23:16> << 24 | 1685 Rs.uw<7:0> << 16 | 1686 Rt.uw<23:16> << 8 | 1687 Rt.uw<7:0>; }}); 1688 0x6: packrl_ph({{ Rd.uw = dspPack( Rs.uw, Rt.uw, 1689 SIMD_FMT_PH ); }}); 1690 0x7: precrqu_s_qb_ph({{ Rd.uw = dspPrecrqu( Rs.uw, Rt.uw, &dspctl ); }}); 1691 } 1692 } 1693 0x2: decode OP_LO { 1694 format DspIntOp { 1695 0x4: precrq_ph_w({{ Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; }}); 1696 0x5: precrq_rs_ph_w({{ Rd.uw = dspPrecrq( Rs.uw, Rt.uw, SIMD_FMT_W, &dspctl ); }}); 1697 } 1698 } 1699 0x3: decode OP_LO { 1700 format DspIntOp { 1701 0x0: cmpgdu_eq_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1702 UNSIGNED, CMP_EQ, &dspctl ); }}); 1703 0x1: cmpgdu_lt_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1704 UNSIGNED, CMP_LT, &dspctl ); }}); 1705 0x2: cmpgdu_le_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 1706 UNSIGNED, CMP_LE, &dspctl ); }}); 1707 0x6: precr_sra_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, 1708 SIMD_FMT_W, NOROUND ); }}); 1709 0x7: precr_sra_r_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, 1710 SIMD_FMT_W, ROUND ); }}); 1711 } 1712 } 1713 } 1714 1715 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field (DSP ASE MANUAL) 1716 0x2: decode OP_HI { 1717 0x0: decode OP_LO { 1718 format DspIntOp { 1719 0x1: absq_s_qb({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_QB, &dspctl );}}); 1720 0x2: repl_qb({{ Rd.uw = RS_RT<7:0> << 24 | 1721 RS_RT<7:0> << 16 | 1722 RS_RT<7:0> << 8 | 1723 RS_RT<7:0>; }}); 1724 0x3: replv_qb({{ Rd.sw = Rt.uw<7:0> << 24 | 1725 Rt.uw<7:0> << 16 | 1726 Rt.uw<7:0> << 8 | 1727 Rt.uw<7:0>; }}); 1728 0x4: precequ_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1729 SIMD_FMT_PH, SIGNED, MODE_L ); }}); 1730 0x5: precequ_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1731 SIMD_FMT_PH, SIGNED, MODE_R ); }}); 1732 0x6: precequ_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1733 SIMD_FMT_PH, SIGNED, MODE_LA ); }}); 1734 0x7: precequ_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1735 SIMD_FMT_PH, SIGNED, MODE_RA ); }}); 1736 } 1737 } 1738 0x1: decode OP_LO { 1739 format DspIntOp { 1740 0x1: absq_s_ph({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_PH, &dspctl ); }}); 1741 0x2: repl_ph({{ Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | 1742 (sext<10>(RS_RT))<15:0>; }}); 1743 0x3: replv_ph({{ Rd.uw = Rt.uw<15:0> << 16 | 1744 Rt.uw<15:0>; }}); 1745 0x4: preceq_w_phl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, 1746 SIMD_FMT_W, SIGNED, MODE_L ); }}); 1747 0x5: preceq_w_phr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, 1748 SIMD_FMT_W, SIGNED, MODE_R ); }}); 1749 } 1750 } 1751 0x2: decode OP_LO { 1752 format DspIntOp { 1753 0x1: absq_s_w({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_W, &dspctl ); }}); 1754 } 1755 } 1756 0x3: decode OP_LO { 1757 0x3: IntOp::bitrev({{ Rd.uw = bitrev( Rt.uw<15:0> ); }}); 1758 format DspIntOp { 1759 0x4: preceu_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1760 SIMD_FMT_PH, UNSIGNED, MODE_L ); }}); 1761 0x5: preceu_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1762 SIMD_FMT_PH, UNSIGNED, MODE_R ); }}); 1763 0x6: preceu_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1764 SIMD_FMT_PH, UNSIGNED, MODE_LA ); }}); 1765 0x7: preceu_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 1766 SIMD_FMT_PH, UNSIGNED, MODE_RA ); }}); 1767 } 1768 } 1769 } 1770 1771 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field (DSP ASE MANUAL) 1772 0x3: decode OP_HI { 1773 0x0: decode OP_LO { 1774 format DspIntOp { 1775 0x0: shll_qb({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_QB, 1776 NOSATURATE, UNSIGNED, &dspctl ); }}); 1777 0x1: shrl_qb({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_QB, 1778 UNSIGNED ); }}); 1779 0x2: shllv_qb({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_QB, 1780 NOSATURATE, UNSIGNED, &dspctl ); }}); 1781 0x3: shrlv_qb({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_QB, 1782 UNSIGNED ); }}); 1783 0x4: shra_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, 1784 NOROUND, SIGNED, &dspctl ); }}); 1785 0x5: shra_r_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, 1786 ROUND, SIGNED, &dspctl ); }}); 1787 0x6: shrav_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, 1788 NOROUND, SIGNED, &dspctl ); }}); 1789 0x7: shrav_r_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, 1790 ROUND, SIGNED, &dspctl ); }}); 1791 } 1792 } 1793 0x1: decode OP_LO { 1794 format DspIntOp { 1795 0x0: shll_ph({{ Rd.uw = dspShll( Rt.uw, RS, SIMD_FMT_PH, 1796 NOSATURATE, SIGNED, &dspctl ); }}); 1797 0x1: shra_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, 1798 NOROUND, SIGNED, &dspctl ); }}); 1799 0x2: shllv_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, 1800 NOSATURATE, SIGNED, &dspctl ); }}); 1801 0x3: shrav_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, 1802 NOROUND, SIGNED, &dspctl ); }}); 1803 0x4: shll_s_ph({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_PH, 1804 SATURATE, SIGNED, &dspctl ); }}); 1805 0x5: shra_r_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, 1806 ROUND, SIGNED, &dspctl ); }}); 1807 0x6: shllv_s_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, 1808 SATURATE, SIGNED, &dspctl ); }}); 1809 0x7: shrav_r_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, 1810 ROUND, SIGNED, &dspctl ); }}); 1811 } 1812 } 1813 0x2: decode OP_LO { 1814 format DspIntOp { 1815 0x4: shll_s_w({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_W, 1816 SATURATE, SIGNED, &dspctl ); }}); 1817 0x5: shra_r_w({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_W, 1818 ROUND, SIGNED, &dspctl ); }}); 1819 0x6: shllv_s_w({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_W, 1820 SATURATE, SIGNED, &dspctl ); }}); 1821 0x7: shrav_r_w({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_W, 1822 ROUND, SIGNED, &dspctl ); }}); 1823 } 1824 } 1825 0x3: decode OP_LO { 1826 format DspIntOp { 1827 0x1: shrl_ph({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_PH, 1828 UNSIGNED ); }}); 1829 0x3: shrlv_ph({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_PH, 1830 UNSIGNED ); }}); 1831 } 1832 } 1833 } 1834 } 1835 1836 0x3: decode FUNCTION_LO { 1837 1838 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field (DSP ASE Rev2 Manual) 1839 0x0: decode OP_HI { 1840 0x0: decode OP_LO { 1841 format DspIntOp { 1842 0x0: adduh_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1843 NOROUND, UNSIGNED ); }}); 1844 0x1: subuh_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1845 NOROUND, UNSIGNED ); }}); 1846 0x2: adduh_r_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1847 ROUND, UNSIGNED ); }}); 1848 0x3: subuh_r_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, 1849 ROUND, UNSIGNED ); }}); 1850 } 1851 } 1852 0x1: decode OP_LO { 1853 format DspIntOp { 1854 0x0: addqh_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1855 NOROUND, SIGNED ); }}); 1856 0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1857 NOROUND, SIGNED ); }}); 1858 0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1859 ROUND, SIGNED ); }}); 1860 0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, 1861 ROUND, SIGNED ); }}); 1862 0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, 1863 NOSATURATE, &dspctl ); }}, IntMultOp); 1864 0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, 1865 SATURATE, &dspctl ); }}, IntMultOp); 1866 1867 } 1868 } 1869 0x2: decode OP_LO { 1870 format DspIntOp { 1871 0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, 1872 NOROUND, SIGNED ); }}); 1873 0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, 1874 NOROUND, SIGNED ); }}); 1875 0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, 1876 ROUND, SIGNED ); }}); 1877 0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, 1878 ROUND, SIGNED ); }}); 1879 0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, 1880 SATURATE, NOROUND, &dspctl ); }}, IntMultOp); 1881 0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, 1882 SATURATE, ROUND, &dspctl ); }}, IntMultOp); 1883 } 1884 } 1885 } 1886 } 1887 1888 //Table A-10 MIPS32 BSHFL Encoding of sa Field 1889 0x4: decode SA { 1890 format BasicOp { 1891 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 | 1892 Rt.uw<31:24> << 16 | 1893 Rt.uw<7:0> << 8 | 1894 Rt.uw<15:8>; 1895 }}); 1896 0x10: seb({{ Rd.sw = Rt.sb; }}); 1897 0x18: seh({{ Rd.sw = Rt.sh; }}); 1898 } 1899 } 1900 1901 0x6: decode FUNCTION_LO { 1902 1903 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL) 1904 0x0: decode OP_HI { 1905 0x0: decode OP_LO { 1906 format DspHiLoOp { 1907 0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1908 SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); 1909 0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1910 SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); 1911 0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw, 1912 ACDST, SIMD_FMT_PH ); }}, IntMultOp); 1913 0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1914 SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); 1915 0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1916 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1917 0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1918 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1919 0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw, 1920 ACDST, SIMD_FMT_PH, &dspctl ); }}, IntMultOp); 1921 0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1922 SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); 1923 } 1924 } 1925 0x1: decode OP_LO { 1926 format DspHiLoOp { 1927 0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 1928 SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); 1929 0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1930 SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); 1931 0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1932 SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); 1933 0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, 1934 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1935 0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, 1936 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); 1937 0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 1938 SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); 1939 } 1940 } 1941 0x2: decode OP_LO { 1942 format DspHiLoOp { 1943 0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1944 MODE_L, SATURATE, &dspctl ); }}, IntMultOp); 1945 0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1946 MODE_R, SATURATE, &dspctl ); }}, IntMultOp); 1947 0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1948 MODE_L, NOSATURATE, &dspctl ); }}, IntMultOp); 1949 0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 1950 MODE_R, NOSATURATE, &dspctl ); }}, IntMultOp); 1951 } 1952 } 1953 0x3: decode OP_LO { 1954 format DspHiLoOp { 1955 0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1956 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); 1957 0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1958 SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); 1959 0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1960 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); 1961 0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 1962 SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); 1963 } 1964 } 1965 } 1966 1967 //Table 3.3 MIPS32 APPEND Encoding of the op Field 1968 0x1: decode OP_HI { 1969 0x0: decode OP_LO { 1970 format IntOp { 1971 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }}); 1972 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }}); 1973 } 1974 } 1975 0x2: decode OP_LO { 1976 format IntOp { 1977 0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }}); 1978 } 1979 } 1980 } 1981 1982 } 1983 0x7: decode FUNCTION_LO { 1984 1985 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL) 1986 0x0: decode OP_HI { 1987 0x0: decode OP_LO { 1988 format DspHiLoOp { 1989 0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 1990 NOROUND, NOSATURATE, &dspctl ); }}); 1991 0x1: extrv_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 1992 NOROUND, NOSATURATE, &dspctl ); }}); 1993 0x2: extp({{ Rt.uw = dspExtp( dspac, RS, &dspctl ); }}); 1994 0x3: extpv({{ Rt.uw = dspExtp( dspac, Rs.uw, &dspctl ); }}); 1995 0x4: extr_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 1996 ROUND, NOSATURATE, &dspctl ); }}); 1997 0x5: extrv_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 1998 ROUND, NOSATURATE, &dspctl ); }}); 1999 0x6: extr_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 2000 ROUND, SATURATE, &dspctl ); }}); 2001 0x7: extrv_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 2002 ROUND, SATURATE, &dspctl ); }}); 2003 } 2004 } 2005 0x1: decode OP_LO { 2006 format DspHiLoOp { 2007 0x2: extpdp({{ Rt.uw = dspExtpd( dspac, RS, &dspctl ); }}); 2008 0x3: extpdpv({{ Rt.uw = dspExtpd( dspac, Rs.uw, &dspctl ); }}); 2009 0x6: extr_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, RS, 2010 NOROUND, SATURATE, &dspctl ); }}); 2011 0x7: extrv_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, Rs.uw, 2012 NOROUND, SATURATE, &dspctl ); }}); 2013 } 2014 } 2015 0x2: decode OP_LO { 2016 format DspIntOp { 2017 0x2: rddsp({{ Rd.uw = readDSPControl( &dspctl, RDDSPMASK ); }}); 2018 0x3: wrdsp({{ writeDSPControl( &dspctl, Rs.uw, WRDSPMASK ); }}); 2019 } 2020 } 2021 0x3: decode OP_LO { 2022 format DspHiLoOp { 2023 0x2: shilo({{ if( sext<6>(HILOSA) < 0 ) 2024 dspac = (uint64_t)dspac << -sext<6>(HILOSA); 2025 else 2026 dspac = (uint64_t)dspac >> sext<6>(HILOSA); }}); 2027 0x3: shilov({{ if( sext<6>(Rs.sw<5:0>) < 0 ) 2028 dspac = (uint64_t)dspac << -sext<6>(Rs.sw<5:0>); 2029 else 2030 dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }}); 2031 0x7: mthlip({{ dspac = dspac << 32; 2032 dspac |= Rs.uw; 2033 dspctl = insertBits( dspctl, 5, 0, 2034 dspctl<5:0>+32 ); }}); 2035 } 2036 } 2037 } 2038 0x3: decode OP_HI { 2039 0x2: decode OP_LO { 2040 0x3: FailUnimpl::rdhwr(); 2041 } 2042 } 2043 } 2044 } 2045 } 2046 2047 0x4: decode OPCODE_LO { 2048 format LoadMemory { 2049 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT); 2050 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 2051 0x3: lw({{ Rt.sw = Mem.sw; }}); 2052 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT); 2053 0x5: lhu({{ Rt.uw = Mem.uh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 2054 } 2055 2056 format LoadUnalignedMemory { 2057 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset); 2058 Rt.uw = mem_word << mem_shift | 2059 Rt.uw & mask(mem_shift); 2060 }}); 2061 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset; 2062 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) | 2063 mem_word >> mem_shift; 2064 }}); 2065 } 2066 } 2067 2068 0x5: decode OPCODE_LO { 2069 format StoreMemory { 2070 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT); 2071 0x1: sh({{ Mem.uh = Rt<15:0>; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 2072 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 2073 } 2074 2075 format StoreUnalignedMemory { 2076 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset); 2077 uint32_t mem_shift = 32 - reg_shift; 2078 mem_word = mem_word & (mask(reg_shift) << mem_shift) | 2079 Rt.uw >> reg_shift; 2080 }}); 2081 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset; 2082 mem_word = Rt.uw << reg_shift | 2083 mem_word & (mask(reg_shift)); 2084 }}); 2085 } 2086 format CP0Control { 2087 0x7: cache({{ 2088 Addr CacheEA = Rs.uw + OFFSET; 2089 fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2090 }}); 2091 } 2092 } 2093 2094 0x6: decode OPCODE_LO { 2095 format LoadMemory { 2096 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED); 2097 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 2098 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 2099 } 2100 0x2: CP2Unimpl::lwc2(); 2101 0x6: CP2Unimpl::ldc2(); 2102 0x3: Prefetch::pref(); 2103 } 2104 2105 2106 0x7: decode OPCODE_LO { 2107 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, 2108 {{ uint64_t tmp = write_result; 2109 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; 2110 }}, mem_flags=LOCKED, inst_flags = IsStoreConditional); 2111 2112 format StoreMemory { 2113 0x1: swc1({{ Mem.uw = Ft.uw;}}); 2114 0x5: sdc1({{ Mem.ud = Ft.ud;}}); 2115 } 2116 2117 0x2: CP2Unimpl::swc2(); 2118 0x6: CP2Unimpl::sdc2(); 2119 2120 } 2121} 2122 2123 2124