decoder.isa revision 4675:598d4c33c38d 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
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24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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28//
29// Authors: Korey Sewell
30//          Brett Miller
31
32////////////////////////////////////////////////////////////////////
33//
34// The actual MIPS32 ISA decoder
35// -----------------------------
36// The following instructions are specified in the MIPS32 ISA
37// Specification. Decoding closely follows the style specified
38// in the MIPS32 ISA specification document starting with Table
39// A-2 (document available @ http://www.mips.com)
40//
41decode OPCODE_HI default Unknown::unknown() {
42    //Table A-2
43    0x0: decode OPCODE_LO {
44        0x0: decode FUNCTION_HI {
45            0x0: decode FUNCTION_LO {
46                0x1: decode MOVCI {
47                    format BasicOp {
48                        0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }});
49                        1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }});
50                    }
51                }
52
53                format BasicOp {
54                    //Table A-3 Note: "Specific encodings of the rd, rs, and
55                    //rt fields are used to distinguish SLL, SSNOP, and EHB
56                    //functions
57                    0x0: decode RS  {
58                        0x0: decode RT_RD {
59                            0x0: decode SA default Nop::nop() {
60                                0x1: WarnUnimpl::ssnop();
61                                0x3: WarnUnimpl::ehb();
62                            }
63                            default: sll({{ Rd = Rt.uw << SA; }});
64                        }
65                    }
66
67                    0x2: decode RS_SRL {
68                        0x0:decode SRL {
69                            0: srl({{ Rd = Rt.uw >> SA; }});
70
71                            //Hardcoded assuming 32-bit ISA, probably need parameter here
72                            1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
73                        }
74                    }
75
76                    0x3: decode RS {
77                        0x0: sra({{
78                            uint32_t temp = Rt >> SA;
79                            if ( (Rt & 0x80000000) > 0 ) {
80                                uint32_t mask = 0x80000000;
81                                for(int i=0; i < SA; i++) {
82                                    temp |= mask;
83                                    mask = mask >> 1;
84                                }
85                            }
86                            Rd = temp;
87                        }});
88                    }
89
90                    0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
91
92                    0x6: decode SRLV {
93                        0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
94
95                        //Hardcoded assuming 32-bit ISA, probably need parameter here
96                        1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
97                    }
98
99                    0x7: srav({{
100                        int shift_amt = Rs<4:0>;
101
102                        uint32_t temp = Rt >> shift_amt;
103
104                        if ( (Rt & 0x80000000) > 0 ) {
105                                uint32_t mask = 0x80000000;
106                                for(int i=0; i < shift_amt; i++) {
107                                    temp |= mask;
108                                    mask = mask >> 1;
109                                }
110                            }
111
112                        Rd = temp;
113                    }});
114                }
115            }
116
117            0x1: decode FUNCTION_LO {
118                //Table A-3 Note: "Specific encodings of the hint field are
119                //used to distinguish JR from JR.HB and JALR from JALR.HB"
120                format Jump {
121                    0x0: decode HINT {
122                        0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
123                        default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
124                    }
125
126                    0x1: decode HINT {
127                        0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall
128                                     , ClearHazards);
129                        default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall);
130                    }
131                }
132
133                format BasicOp {
134                    0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
135                    0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
136                    0x4: syscall({{ xc->syscall(R2); }},
137                                 IsSerializeAfter, IsNonSpeculative);
138                    0x7: sync({{ ; }}, IsMemBarrier);
139                }
140
141                format FailUnimpl {
142                    0x5: break();
143                }
144            }
145
146            0x2: decode FUNCTION_LO {
147                0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }});
148                0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
149                0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }});
150                0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
151            }
152
153            0x3: decode FUNCTION_LO {
154                format HiLoRdSelValOp {
155                    0x0: mult({{ val = Rs.sd * Rt.sd; }});
156                    0x1: multu({{ val = Rs.ud * Rt.ud; }});
157                }
158
159                format HiLoOp {
160                    0x2: div({{ if (Rt.sd != 0) {
161                        HI0 = Rs.sd % Rt.sd;
162                        LO0 = Rs.sd / Rt.sd;
163                    }
164                    }});
165                    0x3: divu({{ if (Rt.ud != 0) {
166                        HI0 = Rs.ud % Rt.ud;
167                        LO0 = Rs.ud / Rt.ud;
168                    }
169                    }});
170                }
171            }
172
173            0x4: decode HINT {
174                0x0: decode FUNCTION_LO {
175                    format IntOp {
176                        0x0: add({{  Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
177                        0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
178                        0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;  /*Trap on Overflow*/}});
179                        0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
180                        0x4: and({{ Rd = Rs & Rt;}});
181                        0x5: or({{ Rd = Rs | Rt;}});
182                        0x6: xor({{ Rd = Rs ^ Rt;}});
183                        0x7: nor({{ Rd = ~(Rs | Rt);}});
184                    }
185                }
186            }
187
188            0x5: decode HINT {
189                0x0: decode FUNCTION_LO {
190                    format IntOp{
191                        0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
192                        0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
193                    }
194                }
195            }
196
197            0x6: decode FUNCTION_LO {
198                format Trap {
199                    0x0: tge({{  cond = (Rs.sw >= Rt.sw); }});
200                    0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
201                    0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
202                    0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
203                    0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
204                    0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
205                }
206            }
207        }
208
209        0x1: decode REGIMM_HI {
210            0x0: decode REGIMM_LO {
211                format Branch {
212                    0x0: bltz({{ cond = (Rs.sw < 0); }});
213                    0x1: bgez({{ cond = (Rs.sw >= 0); }});
214                    0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely);
215                    0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely);
216                }
217            }
218
219            0x1: decode REGIMM_LO {
220                format Trap {
221                    0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
222                    0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
223                    0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
224                    0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
225                    0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
226                    0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
227                }
228            }
229
230            0x2: decode REGIMM_LO {
231                format Branch {
232                    0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link);
233                    0x1: decode RS {
234                        0x0: bal ({{ cond = 1; }}, IsCall, Link);
235                        default: bgezal({{ cond = (Rs.sw >= 0); }}, Link);
236                    }
237                    0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely);
238                    0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely);
239                }
240            }
241
242            0x3: decode REGIMM_LO {
243                // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL)
244                0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }});
245                format WarnUnimpl {
246                    0x7: synci();
247                }
248            }
249        }
250
251        format Jump {
252            0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
253            0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall,
254                     Link);
255        }
256
257        format Branch {
258            0x4: decode RS_RT  {
259                0x0: b({{ cond = 1; }});
260                default: beq({{ cond = (Rs.sw == Rt.sw); }});
261            }
262            0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
263            0x6: blez({{ cond = (Rs.sw <= 0); }});
264            0x7: bgtz({{ cond = (Rs.sw > 0); }});
265        }
266    }
267
268    0x1: decode OPCODE_LO {
269        format IntImmOp {
270            0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
271            0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
272            0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
273
274            //Edited to include MIPS AVP Pass/Fail instructions and
275            //default to the sltiu instruction
276            0x3: decode RS_RT_INTIMM {
277                0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }});
278                0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }});
279              default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
280            }
281
282            0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
283            0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
284            0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
285
286            0x7: decode RS {
287                0x0: lui({{ Rt = imm << 16}});
288            }
289        }
290    }
291
292    0x2: decode OPCODE_LO {
293        //Table A-11 MIPS32 COP0 Encoding of rs Field
294        0x0: decode RS_MSB {
295            0x0: decode RS {
296                format CP0Control {
297                    0x0: mfc0({{  Rt = CP0_RD_SEL; }});
298                    0x4: mtc0({{  CP0_RD_SEL = Rt; }});
299                }
300
301
302                format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
303                    0x8: decode MT_U {
304                        0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
305                                                                    Ctrl_Base_DepTag);
306                                   }});
307                        0x1: decode SEL {
308                            0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
309                            0x1: decode RT {
310                                0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }});
311                                0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }});
312                                0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }});
313                                0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }});
314                                0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }});
315                                0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }});
316                                0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }});
317                                0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }});
318                                0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }});
319                                0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }});
320                                0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
321                                0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
322                                0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
323                            }
324                            0x2: decode MT_H {
325                                0x0: mftc1({{ data = xc->readRegOtherThread(RT +
326                                                                            FP_Base_DepTag);
327                                           }});
328                                0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
329                                                                             FP_Base_DepTag);
330                                           }});
331                            }
332                            0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR +
333                                                                            FP_Base_DepTag);
334                                          switch (RT)
335                                          {
336                                               case 0:
337                                                 data = xc->readRegOtherThread(MipsISA::FIR +
338                                                                               Ctrl_Base_DepTag);
339                                                 break;
340                                               case 25:
341                                                 data = 0 | fcsr_val & 0xFE000000 >> 24
342                                                          | fcsr_val & 0x00800000 >> 23;
343                                                 break;
344                                               case 26:
345                                                 data = 0 | fcsr_val & 0x0003F07C;
346                                                 break;
347                                               case 28:
348                                                 data = 0 | fcsr_val & 0x00000F80
349                                                          | fcsr_val & 0x01000000 >> 21
350                                                          | fcsr_val & 0x00000003;
351                                                 break;
352                                               case 31:
353                                                 data = fcsr_val;
354                                                 break;
355                                               default:
356                                                 fatal("FP Control Value (%d) Not Valid");
357                                          }
358                                        }});
359                        }
360                    }
361                }
362
363                format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions
364                    0xC: decode MT_U {
365                        0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
366                                                            Rt);
367                                   }});
368                        0x1: decode SEL {
369                            0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
370                            0x1: decode RT {
371                                0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt);
372                                                }});
373                                0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0,
374                                                                         Rt);
375                                                }});
376                                0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0,
377                                                                          Rt);
378                                                 }});
379                                0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1,
380                                                                         Rt);
381                                                }});
382                                0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1,
383                                                                         Rt);
384                                                }});
385                                0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1,
386                                                                          Rt);
387                                                 }});
388                                0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2,
389                                                                         Rt);
390                                                }});
391                                0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2,
392                                                                         Rt);
393                                                }});
394                                0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2,
395                                                                           Rt);
396                                                  }});
397                                0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3,
398                                                                          Rt);
399                                                 }});
400                                0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3,
401                                                                          Rt);
402                                                 }});
403                                0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
404                                                  }});
405                                0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
406                            }
407                            0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
408                                                                                FP_Base_DepTag);
409                                          data = insertBits(data, top_bit, bottom_bit, Rt);
410                                          xc->setRegOtherThread(RD + FP_Base_DepTag, data);
411                                       }});
412                            0x3: cttc1({{ uint32_t data;
413                                          switch (RD)
414                                          {
415                                            case 25:
416                                              data = 0 | (Rt.uw<7:1> << 25) // move 31...25
417                                                  | (FCSR & 0x01000000) // bit 24
418                                                  | (FCSR & 0x004FFFFF);// bit 22...0
419                                              break;
420
421                                            case 26:
422                                              data = 0 | (FCSR & 0xFFFC0000) // move 31...18
423                                                  | Rt.uw<17:12> << 12           // bit 17...12
424                                                  | (FCSR & 0x00000F80) << 7// bit 11...7
425                                                  | Rt.uw<6:2> << 2              // bit 6...2
426                                                  | (FCSR & 0x00000002);     // bit 1...0
427                                              break;
428
429                                            case 28:
430                                              data = 0 | (FCSR & 0xFE000000) // move 31...25
431                                                  | Rt.uw<2:2> << 24       // bit 24
432                                                  | (FCSR & 0x00FFF000) << 23// bit 23...12
433                                                  | Rt.uw<11:7> << 7       // bit 24
434                                                  | (FCSR & 0x000007E)
435                                                  | Rt.uw<1:0>;// bit 22...0
436                                              break;
437
438                                            case 31:
439                                              data  = Rt.uw;
440                                              break;
441
442                                            default:
443                                              panic("FP Control Value (%d) Not Available. Ignoring Access to"
444                                                    "Floating Control Status Register", FS);
445                                          }
446                                          xc->setRegOtherThread(FCSR, data);
447                                       }});
448                        }
449                    }
450                }
451
452
453                0xB: decode RD {
454                    format MT_Control {
455                        0x0: decode POS {
456                            0x0: decode SEL {
457                                0x1: decode SC {
458                                    0x0: dvpe({{ Rt = MVPControl;
459                                                 if (VPEConf0<VPEC0_MVP:> == 1) {
460                                                     MVPControl = insertBits(MVPControl, MVPC_EVP, 0);
461                                                 }
462                                              }});
463                                    0x1: evpe({{ Rt = MVPControl;
464                                                 if (VPEConf0<VPEC0_MVP:> == 1) {
465                                                     MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
466                                                 }
467                                              }});
468                                }
469                            }
470                        }
471
472                        0x1: decode POS {
473                            0xF: decode SEL {
474                                0x1: decode SC {
475                                    0x0: dmt({{ Rt = VPEControl;
476                                                VPEControl = insertBits(VPEControl, VPEC_TE, 0);
477                                         }});
478                                    0x1: emt({{ Rt = VPEControl;
479                                                VPEControl = insertBits(VPEControl, VPEC_TE, 1);
480                                         }});
481
482                                }
483                            }
484                        }
485                    }
486                    0xC: decode POS {
487                      0x0: decode SC {
488                        0x0: CP0Control::di({{
489                            if(Config_AR >= 1) // Rev 2.0 or beyond?
490                                {
491                                  Rt = Status;
492                                  Status_IE = 0;
493                                }
494                            else // Enable this else branch once we actually set values for Config on init
495                              {
496                                fault = new ReservedInstructionFault();
497                              }
498                          }});
499                        0x1: CP0Control::ei({{
500                            if(Config_AR >= 1)
501                              {
502                                Rt = Status;
503                                Status_IE = 1;
504                              }
505                            else
506                              {
507                                fault = new ReservedInstructionFault();
508                              }
509                          }});
510                      }
511                    }
512                }
513
514                format CP0Control {
515                    0xA: rdpgpr({{
516                      if(Config_AR >= 1)
517                        { // Rev 2 of the architecture
518                          Rd = xc->tcBase()->readIntReg(Rt + NumIntRegs * SRSCtl_PSS);
519                        }
520                      else
521                        {
522                          fault = new ReservedInstructionFault();
523                        }
524                         }});
525                    0xE: wrpgpr({{
526                      if(Config_AR >= 1)
527                        { // Rev 2 of the architecture
528                          xc->tcBase()->setIntReg(Rd + NumIntRegs * SRSCtl_PSS,Rt);
529                        }
530                      else
531                        {
532                          fault = new ReservedInstructionFault();
533                        }
534
535                         }});
536
537                }
538
539            }
540
541            //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
542            0x1: decode FUNCTION {
543              format CP0Control {
544                0x18: eret({{
545                  if(Status_ERL == 1){
546                    Status_ERL = 0;
547                    NPC = ErrorEPC;
548                  }
549                  else{
550                    NPC = EPC;
551                    Status_EXL = 0;
552                    if(Config_AR >= 1 && SRSCtl_HSS > 0 && Status_BEV == 0){
553                      SRSCtl_CSS = SRSCtl_PSS;
554                    }
555                  }
556                  //		  LLFlag = 0;
557                  // ClearHazards(); ?
558                }});
559
560                0x1F: deret({{
561                    //if(Debug_DM == 1){
562                    //Debug_DM = 1;
563                    //Debug_IEXI = 0;
564                    //NPC = DEPC;
565                    //}
566                    panic("deret not implemented");
567                }});
568              }
569
570              format FailUnimpl {
571                  0x01: tlbr(); // Need to hook up to TLB
572                  0x02: tlbwi(); // Need to hook up to TLB
573                    0x06: tlbwr();// Need to hook up to TLB
574                    0x08: tlbp();// Need to hook up to TLB
575
576                    0x20: wait();
577                }
578
579            }
580        }
581
582        //Table A-13 MIPS32 COP1 Encoding of rs Field
583        0x1: decode RS_MSB {
584
585            0x0: decode RS_HI {
586                0x0: decode RS_LO {
587                    format CP1Control {
588                        0x0: mfc1 ({{ Rt.uw = Fs.uw; }});
589
590                        0x2: cfc1({{
591                            switch (FS)
592                            {
593                              case 0:
594                                Rt = FIR;
595                                break;
596                              case 25:
597                                Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23;
598                                break;
599                              case 26:
600                                Rt = 0 | (FCSR & 0x0003F07C);
601                                break;
602                              case 28:
603                                Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003);
604                                break;
605                              case 31:
606                                Rt = FCSR;
607                                break;
608                              default:
609                                panic("FP Control Value (%d) Not Valid");
610                            }
611                        }});
612
613                        0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
614
615                        0x4: mtc1 ({{ Fs.uw = Rt.uw;       }});
616
617                        0x6: ctc1({{
618                            switch (FS)
619                            {
620                              case 25:
621                                FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25
622                                    | (FCSR & 0x01000000) // bit 24
623                                    | (FCSR & 0x004FFFFF);// bit 22...0
624                                break;
625
626                              case 26:
627                                FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18
628                                    | Rt.uw<17:12> << 12           // bit 17...12
629                                    | (FCSR & 0x00000F80) << 7// bit 11...7
630                                    | Rt.uw<6:2> << 2              // bit 6...2
631                                    | (FCSR & 0x00000002);     // bit 1...0
632                                break;
633
634                              case 28:
635                                FCSR = 0 | (FCSR & 0xFE000000) // move 31...25
636                                    | Rt.uw<2:2> << 24       // bit 24
637                                    | (FCSR & 0x00FFF000) << 23// bit 23...12
638                                    | Rt.uw<11:7> << 7       // bit 24
639                                    | (FCSR & 0x000007E)
640                                    | Rt.uw<1:0>;// bit 22...0
641                                break;
642
643                              case 31:
644                                FCSR  = Rt.uw;
645                                break;
646
647                              default:
648                                panic("FP Control Value (%d) Not Available. Ignoring Access to"
649                                      "Floating Control Status Register", FS);
650                            }
651                        }});
652
653                        0x7: mthc1({{
654                             uint64_t fs_hi = Rt.uw;
655                             uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF;
656                             Fs.ud = (fs_hi << 32) | fs_lo;
657                        }});
658
659                    }
660                }
661
662                0x1: decode ND {
663                    format Branch {
664                        0x0: decode TF {
665                            0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
666                                      }});
667                            0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
668                                      }});
669                        }
670                        0x1: decode TF {
671                            0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
672                                       }}, Likely);
673                            0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
674                                       }}, Likely);
675                        }
676                    }
677                }
678            }
679
680            0x1: decode RS_HI {
681                0x2: decode RS_LO {
682                    //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
683                    //(( single-precision floating point))
684                    0x0: decode FUNCTION_HI {
685                        0x0: decode FUNCTION_LO {
686                            format FloatOp {
687                                0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}});
688                                0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}});
689                                0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}});
690                                0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}});
691                                0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}});
692                                0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}});
693                                0x7: neg_s({{ Fd.sf = -Fs.sf;}});
694                            }
695
696                            0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}});
697                        }
698
699                        0x1: decode FUNCTION_LO {
700                            format FloatConvertOp {
701                                0x0: round_l_s({{ val = Fs.sf; }}, ToLong,
702                                               Round);
703                                0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong,
704                                               Trunc);
705                                0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong,
706                                               Ceil);
707                                0x3: floor_l_s({{ val = Fs.sf; }}, ToLong,
708                                               Floor);
709                                0x4: round_w_s({{ val = Fs.sf; }}, ToWord,
710                                               Round);
711                                0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord,
712                                               Trunc);
713                                0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord,
714                                               Ceil);
715                                0x7: floor_w_s({{ val = Fs.sf; }}, ToWord,
716                                               Floor);
717                            }
718                        }
719
720                        0x2: decode FUNCTION_LO {
721                            0x1: decode MOVCF {
722                                format BasicOp {
723                                    0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }});
724                                    0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }});
725                                }
726                            }
727
728                            format BasicOp {
729                                0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
730                                0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
731                            }
732
733                            format FloatOp {
734                                0x5: recip_s({{ Fd = 1 / Fs; }});
735                                0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
736                            }
737                        }
738
739                        0x4: decode FUNCTION_LO {
740                            format FloatConvertOp {
741                                0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble);
742                                0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord);
743                                0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong);
744                            }
745
746                            0x6: FloatOp::cvt_ps_s({{
747                                    Fd.ud = (uint64_t) Fs.uw << 32 |
748                                            (uint64_t) Ft.uw;
749                                }});
750                        }
751
752                        0x6: decode FUNCTION_LO {
753                            format FloatCompareOp {
754                                0x0: c_f_s({{ cond = 0; }}, SinglePrecision,
755                                           UnorderedFalse);
756                                0x1: c_un_s({{ cond = 0; }}, SinglePrecision,
757                                            UnorderedTrue);
758                                0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }},
759                                            UnorderedFalse);
760                                0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }},
761                                             UnorderedTrue);
762                                0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf);	}},
763                                             UnorderedFalse);
764                                0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }},
765                                             UnorderedTrue);
766                                0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }},
767                                             UnorderedFalse);
768                                0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }},
769                                             UnorderedTrue);
770                            }
771                        }
772
773                        0x7: decode FUNCTION_LO {
774                            format FloatCompareOp {
775                                0x0: c_sf_s({{ cond = 0; }}, SinglePrecision,
776                                            UnorderedFalse, QnanException);
777                                0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision,
778                                              UnorderedTrue, QnanException);
779                                0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}},
780                                             UnorderedFalse, QnanException);
781                                0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }},
782                                             UnorderedTrue, QnanException);
783                                0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }},
784                                            UnorderedFalse, QnanException);
785                                0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }},
786                                             UnorderedTrue, QnanException);
787                                0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }},
788                                            UnorderedFalse, QnanException);
789                                0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }},
790                                             UnorderedTrue, QnanException);
791                            }
792                        }
793                    }
794
795                    //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
796                    0x1: decode FUNCTION_HI {
797                        0x0: decode FUNCTION_LO {
798                            format FloatOp {
799                                0x0: add_d({{ Fd.df = Fs.df + Ft.df; }});
800                                0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }});
801                                0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }});
802                                0x3: div_d({{ Fd.df = Fs.df / Ft.df; }});
803                                0x4: sqrt_d({{ Fd.df = sqrt(Fs.df);  }});
804                                0x5: abs_d({{ Fd.df = fabs(Fs.df);   }});
805                                0x7: neg_d({{ Fd.df = -1 * Fs.df;    }});
806                            }
807
808                            0x6: BasicOp::mov_d({{ Fd.df = Fs.df;    }});
809                        }
810
811                        0x1: decode FUNCTION_LO {
812                            format FloatConvertOp {
813                                0x0: round_l_d({{ val = Fs.df; }}, ToLong,
814                                               Round);
815                                0x1: trunc_l_d({{ val = Fs.df; }}, ToLong,
816                                               Trunc);
817                                0x2: ceil_l_d({{ val = Fs.df; }}, ToLong,
818                                               Ceil);
819                                0x3: floor_l_d({{ val = Fs.df; }}, ToLong,
820                                               Floor);
821                                0x4: round_w_d({{ val = Fs.df; }}, ToWord,
822                                               Round);
823                                0x5: trunc_w_d({{ val = Fs.df; }}, ToWord,
824                                               Trunc);
825                                0x6: ceil_w_d({{ val = Fs.df; }}, ToWord,
826                                               Ceil);
827                                0x7: floor_w_d({{ val = Fs.df; }}, ToWord,
828                                               Floor);
829                            }
830                        }
831
832                        0x2: decode FUNCTION_LO {
833                            0x1: decode MOVCF {
834                                format BasicOp {
835                                    0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ?
836                                                       Fs.df : Fd.df;
837                                                }});
838                                    0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ?
839                                                       Fs.df : Fd.df;
840                                                }});
841                                }
842                            }
843
844                            format BasicOp {
845                                0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }});
846                                0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }});
847                            }
848
849                            format FloatOp {
850                                0x5: recip_d({{ Fd.df = 1 / Fs.df }});
851                                0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
852                            }
853                        }
854
855                        0x4: decode FUNCTION_LO {
856                            format FloatConvertOp {
857                                0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
858                                0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
859                                0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
860                            }
861                        }
862
863                        0x6: decode FUNCTION_LO {
864                            format FloatCompareOp {
865                                0x0: c_f_d({{ cond = 0; }}, DoublePrecision,
866                                           UnorderedFalse);
867                                0x1: c_un_d({{ cond = 0; }}, DoublePrecision,
868                                            UnorderedTrue);
869                                0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }},
870                                            UnorderedFalse);
871                                0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }},
872                                             UnorderedTrue);
873                                0x4: c_olt_d({{ cond = (Fs.df < Ft.df);	}},
874                                             UnorderedFalse);
875                                0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }},
876                                             UnorderedTrue);
877                                0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }},
878                                             UnorderedFalse);
879                                0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }},
880                                             UnorderedTrue);
881                            }
882                        }
883
884                        0x7: decode FUNCTION_LO {
885                            format FloatCompareOp {
886                                0x0: c_sf_d({{ cond = 0; }}, DoublePrecision,
887                                            UnorderedFalse, QnanException);
888                                0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision,
889                                              UnorderedTrue, QnanException);
890                                0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }},
891                                             UnorderedFalse, QnanException);
892                                0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }},
893                                             UnorderedTrue, QnanException);
894                                0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }},
895                                            UnorderedFalse, QnanException);
896                                0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }},
897                                             UnorderedTrue, QnanException);
898                                0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }},
899                                            UnorderedFalse, QnanException);
900                                0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }},
901                                             UnorderedTrue, QnanException);
902                            }
903                        }
904                    }
905
906                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
907                    0x4: decode FUNCTION {
908                        format FloatConvertOp {
909                            0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
910                            0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
911                            0x26: FailUnimpl::cvt_ps_w();
912                        }
913                    }
914
915                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
916                    //Note: "1. Format type L is legal only if 64-bit floating point operations
917                    //are enabled."
918                    0x5: decode FUNCTION_HI {
919                        format FloatConvertOp {
920                            0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
921                            0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
922                            0x26: FailUnimpl::cvt_ps_l();
923                        }
924                    }
925
926                    //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
927                    //Note: "1. Format type PS is legal only if 64-bit floating point operations
928                    //are enabled. "
929                    0x6: decode FUNCTION_HI {
930                        0x0: decode FUNCTION_LO {
931                            format Float64Op {
932                                0x0: add_ps({{
933                                    Fd1.sf = Fs1.sf + Ft2.sf;
934                                    Fd2.sf = Fs2.sf + Ft2.sf;
935                                }});
936                                0x1: sub_ps({{
937                                    Fd1.sf = Fs1.sf - Ft2.sf;
938                                    Fd2.sf = Fs2.sf - Ft2.sf;
939                                }});
940                                0x2: mul_ps({{
941                                    Fd1.sf = Fs1.sf * Ft2.sf;
942                                    Fd2.sf = Fs2.sf * Ft2.sf;
943                                }});
944                                0x5: abs_ps({{
945                                    Fd1.sf = fabs(Fs1.sf);
946                                    Fd2.sf = fabs(Fs2.sf);
947                                }});
948                                0x6: mov_ps({{
949                                    Fd1.sf = Fs1.sf;
950                                    Fd2.sf = Fs2.sf;
951                                }});
952                                0x7: neg_ps({{
953                                    Fd1.sf = -(Fs1.sf);
954                                    Fd2.sf = -(Fs2.sf);
955                                }});
956                            }
957                        }
958
959                        0x2: decode FUNCTION_LO {
960                            0x1: decode MOVCF {
961                                format Float64Op {
962                                    0x0: movf_ps({{
963                                        Fd1 = (getCondCode(FCSR, CC) == 0) ?
964                                            Fs1 : Fd1;
965                                        Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
966                                            Fs2 : Fd2;
967                                    }});
968                                    0x1: movt_ps({{
969                                        Fd2 = (getCondCode(FCSR, CC) == 1) ?
970                                            Fs1 : Fd1;
971                                        Fd2 = (getCondCode(FCSR, CC+1) == 1) ?
972                                            Fs2 : Fd2;
973                                    }});
974                                }
975                            }
976
977                            format Float64Op {
978                                0x2: movz_ps({{
979                                    Fd1 = (getCondCode(FCSR, CC) == 0) ?
980                                        Fs1 : Fd1;
981                                    Fd2 = (getCondCode(FCSR, CC) == 0) ?
982                                        Fs2 : Fd2;
983                                }});
984                                0x3: movn_ps({{
985                                    Fd1 = (getCondCode(FCSR, CC) == 1) ?
986                                        Fs1 : Fd1;
987                                    Fd2 = (getCondCode(FCSR, CC) == 1) ?
988                                        Fs2 : Fd2;
989                                }});
990                            }
991
992                        }
993
994                        0x4: decode FUNCTION_LO {
995                            0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
996                        }
997
998                        0x5: decode FUNCTION_LO {
999                            0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }});
1000
1001                            format Float64Op {
1002                                0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1003                                                    Ft1.uw;
1004                                         }});
1005                                0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1006                                                    Ft2.uw;
1007                                         }});
1008                                0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1009                                                    Ft1.uw;
1010                                         }});
1011                                0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1012                                                    Ft2.uw;
1013                                         }});
1014                            }
1015                        }
1016
1017                        0x6: decode FUNCTION_LO {
1018                            format FloatPSCompareOp {
1019                                0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1020                                            UnorderedFalse);
1021                                0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1022                                             UnorderedTrue);
1023                                0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1024                                             {{ cond2 = (Fs2.sf == Ft2.sf); }},
1025                                             UnorderedFalse);
1026                                0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1027                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
1028                                              UnorderedTrue);
1029                                0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
1030                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
1031                                              UnorderedFalse);
1032                                0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }},
1033                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
1034                                              UnorderedTrue);
1035                                0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }},
1036                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1037                                              UnorderedFalse);
1038                                0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1039                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1040                                              UnorderedTrue);
1041                            }
1042                        }
1043
1044                        0x7: decode FUNCTION_LO {
1045                            format FloatPSCompareOp {
1046                                0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1047                                             UnorderedFalse, QnanException);
1048                                0x1: c_ngle_ps({{ cond1 = 0; }},
1049                                               {{ cond2 = 0; }},
1050                                               UnorderedTrue, QnanException);
1051                                0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1052                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
1053                                              UnorderedFalse, QnanException);
1054                                0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1055                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
1056                                              UnorderedTrue, QnanException);
1057                                0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
1058                                             {{ cond2 = (Fs2.sf < Ft2.sf); }},
1059                                             UnorderedFalse, QnanException);
1060                                0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
1061                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
1062                                              UnorderedTrue, QnanException);
1063                                0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1064                                             {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1065                                             UnorderedFalse, QnanException);
1066                                0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1067                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1068                                              UnorderedTrue, QnanException);
1069                            }
1070                        }
1071                    }
1072                }
1073            }
1074        }
1075
1076        //Table A-19 MIPS32 COP2 Encoding of rs Field
1077        0x2: decode RS_MSB {
1078            format FailUnimpl {
1079                0x0: decode RS_HI {
1080                    0x0: decode RS_LO {
1081                        0x0: mfc2();
1082                        0x2: cfc2();
1083                        0x3: mfhc2();
1084                        0x4: mtc2();
1085                        0x6: ctc2();
1086                        0x7: mftc2();
1087                    }
1088
1089                    0x1: decode ND {
1090                        0x0: decode TF {
1091                            0x0: bc2f();
1092                            0x1: bc2t();
1093                        }
1094
1095                        0x1: decode TF {
1096                            0x0: bc2fl();
1097                            0x1: bc2tl();
1098                        }
1099                    }
1100                }
1101            }
1102        }
1103
1104        //Table A-20 MIPS64 COP1X Encoding of Function Field 1
1105        //Note: "COP1X instructions are legal only if 64-bit floating point
1106        //operations are enabled."
1107        0x3: decode FUNCTION_HI {
1108            0x0: decode FUNCTION_LO {
1109                format LoadIndexedMemory {
1110                    0x0: lwxc1({{ Fd.uw = Mem.uw;}});
1111                    0x1: ldxc1({{ Fd.ud = Mem.ud;}});
1112                    0x5: luxc1({{ Fd.ud = Mem.ud;}},
1113                               {{ EA = (Rs + Rt) & ~7; }});
1114                }
1115            }
1116
1117            0x1: decode FUNCTION_LO {
1118                format StoreIndexedMemory {
1119                    0x0: swxc1({{ Mem.uw = Fs.uw;}});
1120                    0x1: sdxc1({{ Mem.ud = Fs.ud;}});
1121                    0x5: suxc1({{ Mem.ud = Fs.ud;}},
1122                               {{ EA = (Rs + Rt) & ~7; }});
1123                }
1124
1125                0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
1126            }
1127
1128            0x3: decode FUNCTION_LO {
1129                0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) {
1130                                               Fd.ud = Fs.ud;
1131                                           } else if (Rs<2:0> == 4) {
1132                                             #if BYTE_ORDER == BIG_ENDIAN
1133                                               Fd.ud = Fs.ud<31:0> << 32 |
1134                                                       Ft.ud<63:32>;
1135                                             #elif BYTE_ORDER == LITTLE_ENDIAN
1136                                               Fd.ud = Ft.ud<31:0> << 32 |
1137                                                       Fs.ud<63:32>;
1138                                             #endif
1139                                           } else {
1140                                               Fd.ud = Fd.ud;
1141                                           }
1142                                        }});
1143            }
1144
1145            format FloatAccOp {
1146                0x4: decode FUNCTION_LO {
1147                    0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }});
1148                    0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }});
1149                    0x6: madd_ps({{
1150                        Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df;
1151                        Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df;
1152                    }});
1153                }
1154
1155                0x5: decode FUNCTION_LO {
1156                    0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }});
1157                    0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }});
1158                    0x6: msub_ps({{
1159                        Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df;
1160                        Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df;
1161                    }});
1162                }
1163
1164                0x6: decode FUNCTION_LO {
1165                    0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
1166                    0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }});
1167                    0x6: nmadd_ps({{
1168                        Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df);
1169                        Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df);
1170                    }});
1171                }
1172
1173                0x7: decode FUNCTION_LO {
1174                    0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
1175                    0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }});
1176                    0x6: nmsub_ps({{
1177                        Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df);
1178                        Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df);
1179                    }});
1180                }
1181
1182            }
1183        }
1184
1185        format Branch {
1186            0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely);
1187            0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely);
1188            0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely);
1189            0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely);
1190        }
1191    }
1192
1193    0x3: decode OPCODE_LO {
1194        //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1195        0x4: decode FUNCTION_HI {
1196            0x0: decode FUNCTION_LO {
1197                0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
1198                                   Rd.sw = temp1<31:0>;
1199                                }});
1200
1201                format HiLoRdSelValOp {
1202                    0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }});
1203                    0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }});
1204                    0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }});
1205                    0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }});
1206                }
1207            }
1208
1209            0x4: decode FUNCTION_LO {
1210                format BasicOp {
1211                    0x0: clz({{ int cnt = 32;
1212                          for (int idx = 31; idx >= 0; idx--) {
1213                              if( Rs<idx:idx> == 1) {
1214                                  cnt = 31 - idx;
1215                                  break;
1216                              }
1217                          }
1218                          Rd.uw = cnt;
1219                       }});
1220                    0x1: clo({{ int cnt = 32;
1221                          for (int idx = 31; idx >= 0; idx--) {
1222                              if( Rs<idx:idx> == 0) {
1223                                  cnt = 31 - idx;
1224                                  break;
1225                              }
1226                          }
1227                          Rd.uw = cnt;
1228                        }});
1229                }
1230            }
1231
1232            0x7: decode FUNCTION_LO {
1233                0x7: FailUnimpl::sdbbp();
1234            }
1235        }
1236
1237        //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2
1238        //of the Architecture
1239        0x7: decode FUNCTION_HI {
1240            0x0: decode FUNCTION_LO {
1241                format BasicOp {
1242                    0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }});
1243                    0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) |
1244                                        bits(Rs.uw, MSB-LSB, 0) << LSB |
1245                                        bits(Rt.uw, LSB-1, 0);
1246                             }});
1247                }
1248            }
1249
1250            0x1: decode FUNCTION_LO {
1251                format MT_Control {
1252                    0x0: fork({{ forkThread(xc->tcBase(), fault, RD, Rs, Rt); }},
1253                              UserMode);
1254                    0x1: yield({{ Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, YQMask); }},
1255                               UserMode);
1256                }
1257
1258                //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL)
1259                0x2: decode OP_HI {
1260                    0x0: decode OP_LO {
1261                        format LoadIndexedMemory {
1262                            0x0: lwx({{ Rd.sw = Mem.sw; }});
1263                            0x4: lhx({{ Rd.sw = Mem.sh; }});
1264                            0x6: lbux({{ Rd.uw = Mem.ub; }});
1265                        }
1266                    }
1267                }
1268                0x4: DspIntOp::insv({{ int pos = dspctl<5:0>;
1269                                       int size = dspctl<12:7>-1;
1270                                       Rt.uw = insertBits( Rt.uw, pos+size, pos, Rs.uw<size:0> ); }});
1271            }
1272
1273            0x2: decode FUNCTION_LO {
1274
1275                //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field (DSP ASE MANUAL)
1276                0x0: decode OP_HI {
1277                    0x0: decode OP_LO {
1278                        format DspIntOp {
1279                            0x0: addu_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1280                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1281                            0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1282                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1283                            0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1284                                                              SATURATE, UNSIGNED, &dspctl ); }});
1285                            0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1286                                                              SATURATE, UNSIGNED, &dspctl ); }});
1287                            0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1288                                                                     MODE_L, &dspctl ); }});
1289                            0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1290                                                                     MODE_R, &dspctl ); }});
1291                        }
1292                    }
1293                    0x1: decode OP_LO {
1294                        format DspIntOp {
1295                            0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1296                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1297                            0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1298                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1299                            0x2: addq_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1300                                                            NOSATURATE, SIGNED, &dspctl ); }});
1301                            0x3: subq_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1302                                                            NOSATURATE, SIGNED, &dspctl ); }});
1303                            0x4: addu_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1304                                                              SATURATE, UNSIGNED, &dspctl ); }});
1305                            0x5: subu_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1306                                                              SATURATE, UNSIGNED, &dspctl ); }});
1307                            0x6: addq_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1308                                                              SATURATE, SIGNED, &dspctl ); }});
1309                            0x7: subq_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1310                                                              SATURATE, SIGNED, &dspctl ); }});
1311                        }
1312                    }
1313                    0x2: decode OP_LO {
1314                        format DspIntOp {
1315                            0x0: addsc({{ int64_t dresult;
1316                                          dresult = Rs.ud + Rt.ud;
1317                                          Rd.sw = dresult<31:0>;
1318                                          dspctl = insertBits( dspctl, 13, 13,
1319                                                               dresult<32:32> ); }});
1320                            0x1: addwc({{ int64_t dresult;
1321                                          dresult = Rs.sd + Rt.sd + dspctl<13:13>;
1322                                          Rd.sw = dresult<31:0>;
1323                                          if( dresult<32:32> != dresult<31:31> )
1324                                              dspctl = insertBits( dspctl, 20, 20, 1 ); }});
1325                            0x2: modsub({{ Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : Rs.sw - Rt.sw<7:0>; }});
1326                            0x4: raddu_w_qb({{ Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> +
1327                                                   Rs.uw<15:8> + Rs.uw<7:0>; }});
1328                            0x6: addq_s_w({{ Rd.sw = dspAdd( Rs.sw, Rt.sw, SIMD_FMT_W,
1329                                                             SATURATE, SIGNED, &dspctl ); }});
1330                            0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W,
1331                                                             SATURATE, SIGNED, &dspctl ); }});
1332                        }
1333                    }
1334                    0x3: decode OP_LO {
1335                        format DspIntOp {
1336                            0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1337                                                                    MODE_L, &dspctl ); }});
1338                            0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1339                                                                    MODE_R, &dspctl ); }});
1340                            0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1341                                                               SATURATE, NOROUND, &dspctl ); }});
1342                            0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1343                                                                SATURATE, ROUND, &dspctl ); }});
1344                        }
1345                    }
1346                }
1347
1348                //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL)
1349                0x1: decode OP_HI {
1350                    0x0: decode OP_LO {
1351                        format DspIntOp {
1352                            0x0: cmpu_eq_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1353                                                       UNSIGNED, CMP_EQ, &dspctl ); }});
1354                            0x1: cmpu_lt_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1355                                                       UNSIGNED, CMP_LT, &dspctl ); }});
1356                            0x2: cmpu_le_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1357                                                       UNSIGNED, CMP_LE, &dspctl ); }});
1358                            0x3: pick_qb({{ Rd.uw = dspPick( Rs.uw, Rt.uw,
1359                                                             SIMD_FMT_QB, &dspctl ); }});
1360                            0x4: cmpgu_eq_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1361                                                                 UNSIGNED, CMP_EQ ); }});
1362                            0x5: cmpgu_lt_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1363                                                                 UNSIGNED, CMP_LT ); }});
1364                            0x6: cmpgu_le_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1365                                                                 UNSIGNED, CMP_LE ); }});
1366                        }
1367                    }
1368                    0x1: decode OP_LO {
1369                        format DspIntOp {
1370                            0x0: cmp_eq_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1371                                                      SIGNED, CMP_EQ, &dspctl ); }});
1372                            0x1: cmp_lt_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1373                                                      SIGNED, CMP_LT, &dspctl ); }});
1374                            0x2: cmp_le_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1375                                                      SIGNED, CMP_LE, &dspctl ); }});
1376                            0x3: pick_ph({{ Rd.uw = dspPick( Rs.uw, Rt.uw,
1377                                                             SIMD_FMT_PH, &dspctl ); }});
1378                            0x4: precrq_qb_ph({{ Rd.uw = Rs.uw<31:24> << 24 |
1379                                                         Rs.uw<15:8> << 16 |
1380                                                         Rt.uw<31:24> << 8 |
1381                                                         Rt.uw<15:8>; }});
1382                            0x5: precr_qb_ph({{ Rd.uw = Rs.uw<23:16> << 24 |
1383                                                         Rs.uw<7:0> << 16 |
1384                                                         Rt.uw<23:16> << 8 |
1385                                                         Rt.uw<7:0>; }});
1386                            0x6: packrl_ph({{ Rd.uw = dspPack( Rs.uw, Rt.uw,
1387                                                               SIMD_FMT_PH ); }});
1388                            0x7: precrqu_s_qb_ph({{ Rd.uw = dspPrecrqu( Rs.uw, Rt.uw, &dspctl ); }});
1389                        }
1390                    }
1391                    0x2: decode OP_LO {
1392                        format DspIntOp {
1393                            0x4: precrq_ph_w({{ Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; }});
1394                            0x5: precrq_rs_ph_w({{ Rd.uw = dspPrecrq( Rs.uw, Rt.uw, SIMD_FMT_W, &dspctl ); }});
1395                        }
1396                    }
1397                    0x3: decode OP_LO {
1398                        format DspIntOp {
1399                            0x0: cmpgdu_eq_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1400                                                                   UNSIGNED, CMP_EQ, &dspctl ); }});
1401                            0x1: cmpgdu_lt_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1402                                                                   UNSIGNED, CMP_LT, &dspctl  ); }});
1403                            0x2: cmpgdu_le_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1404                                                                   UNSIGNED, CMP_LE, &dspctl ); }});
1405                            0x6: precr_sra_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD,
1406                                                                        SIMD_FMT_W, NOROUND ); }});
1407                            0x7: precr_sra_r_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD,
1408                                                                        SIMD_FMT_W, ROUND ); }});
1409                        }
1410                    }
1411                }
1412
1413                //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field (DSP ASE MANUAL)
1414                0x2: decode OP_HI {
1415                    0x0: decode OP_LO {
1416                        format DspIntOp {
1417                            0x1: absq_s_qb({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_QB, &dspctl );}});
1418                            0x2: repl_qb({{ Rd.uw = RS_RT<7:0> << 24 |
1419                                                    RS_RT<7:0> << 16 |
1420                                                    RS_RT<7:0> << 8 |
1421                                                    RS_RT<7:0>; }});
1422                            0x3: replv_qb({{ Rd.sw = Rt.uw<7:0> << 24 |
1423                                                     Rt.uw<7:0> << 16 |
1424                                                     Rt.uw<7:0> << 8 |
1425                                                     Rt.uw<7:0>; }});
1426                            0x4: precequ_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1427                                                                     SIMD_FMT_PH, SIGNED, MODE_L ); }});
1428                            0x5: precequ_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1429                                                                     SIMD_FMT_PH, SIGNED, MODE_R ); }});
1430                            0x6: precequ_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1431                                                                      SIMD_FMT_PH, SIGNED, MODE_LA ); }});
1432                            0x7: precequ_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1433                                                                      SIMD_FMT_PH, SIGNED, MODE_RA ); }});
1434                        }
1435                    }
1436                    0x1: decode OP_LO {
1437                        format DspIntOp {
1438                            0x1: absq_s_ph({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_PH, &dspctl ); }});
1439                            0x2: repl_ph({{ Rd.uw = (sext<10>(RS_RT))<15:0> << 16 |
1440                                                    (sext<10>(RS_RT))<15:0>; }});
1441                            0x3: replv_ph({{ Rd.uw = Rt.uw<15:0> << 16 |
1442                                                     Rt.uw<15:0>; }});
1443                            0x4: preceq_w_phl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED,
1444                                                                   SIMD_FMT_W, SIGNED, MODE_L ); }});
1445                            0x5: preceq_w_phr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED,
1446                                                                   SIMD_FMT_W, SIGNED, MODE_R ); }});
1447                        }
1448                    }
1449                    0x2: decode OP_LO {
1450                        format DspIntOp {
1451                            0x1: absq_s_w({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_W, &dspctl ); }});
1452                        }
1453                    }
1454                    0x3: decode OP_LO {
1455                        0x3: IntOp::bitrev({{ Rd.uw = bitrev( Rt.uw<15:0> ); }});
1456                        format DspIntOp {
1457                            0x4: preceu_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1458                                                                    SIMD_FMT_PH, UNSIGNED, MODE_L ); }});
1459                            0x5: preceu_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1460                                                                    SIMD_FMT_PH, UNSIGNED, MODE_R ); }});
1461                            0x6: preceu_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1462                                                                     SIMD_FMT_PH, UNSIGNED, MODE_LA ); }});
1463                            0x7: preceu_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1464                                                                     SIMD_FMT_PH, UNSIGNED, MODE_RA ); }});
1465                        }
1466                    }
1467                }
1468
1469                //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field (DSP ASE MANUAL)
1470                0x3: decode OP_HI {
1471                    0x0: decode OP_LO {
1472                        format DspIntOp {
1473                            0x0: shll_qb({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_QB,
1474                                                             NOSATURATE, UNSIGNED, &dspctl ); }});
1475                            0x1: shrl_qb({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_QB,
1476                                                             UNSIGNED ); }});
1477                            0x2: shllv_qb({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_QB,
1478                                                              NOSATURATE, UNSIGNED, &dspctl ); }});
1479                            0x3: shrlv_qb({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_QB,
1480                                                              UNSIGNED ); }});
1481                            0x4: shra_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB,
1482                                                             NOROUND, SIGNED, &dspctl ); }});
1483                            0x5: shra_r_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB,
1484                                                               ROUND, SIGNED, &dspctl ); }});
1485                            0x6: shrav_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB,
1486                                                              NOROUND, SIGNED, &dspctl ); }});
1487                            0x7: shrav_r_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB,
1488                                                                ROUND, SIGNED, &dspctl ); }});
1489                        }
1490                    }
1491                    0x1: decode OP_LO {
1492                        format DspIntOp {
1493                            0x0: shll_ph({{ Rd.uw = dspShll( Rt.uw, RS, SIMD_FMT_PH,
1494                                                             NOSATURATE, SIGNED, &dspctl ); }});
1495                            0x1: shra_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH,
1496                                                             NOROUND, SIGNED, &dspctl ); }});
1497                            0x2: shllv_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH,
1498                                                              NOSATURATE, SIGNED, &dspctl ); }});
1499                            0x3: shrav_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH,
1500                                                              NOROUND, SIGNED, &dspctl ); }});
1501                            0x4: shll_s_ph({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_PH,
1502                                                               SATURATE, SIGNED, &dspctl ); }});
1503                            0x5: shra_r_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH,
1504                                                               ROUND, SIGNED, &dspctl ); }});
1505                            0x6: shllv_s_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH,
1506                                                                SATURATE, SIGNED, &dspctl ); }});
1507                            0x7: shrav_r_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH,
1508                                                                ROUND, SIGNED, &dspctl ); }});
1509                        }
1510                    }
1511                    0x2: decode OP_LO {
1512                        format DspIntOp {
1513                            0x4: shll_s_w({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_W,
1514                                                              SATURATE, SIGNED, &dspctl ); }});
1515                            0x5: shra_r_w({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_W,
1516                                                              ROUND, SIGNED, &dspctl ); }});
1517                            0x6: shllv_s_w({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_W,
1518                                                               SATURATE, SIGNED, &dspctl ); }});
1519                            0x7: shrav_r_w({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_W,
1520                                                               ROUND, SIGNED, &dspctl ); }});
1521                        }
1522                    }
1523                    0x3: decode OP_LO {
1524                        format DspIntOp {
1525                            0x1: shrl_ph({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_PH,
1526                                                             UNSIGNED ); }});
1527                            0x3: shrlv_ph({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_PH,
1528                                                              UNSIGNED ); }});
1529                        }
1530                    }
1531                }
1532            }
1533
1534            0x3: decode FUNCTION_LO {
1535
1536                //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field (DSP ASE Rev2 Manual)
1537                0x0: decode OP_HI {
1538                    0x0: decode OP_LO {
1539                        format DspIntOp {
1540                            0x0: adduh_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1541                                                              NOROUND, UNSIGNED ); }});
1542                            0x1: subuh_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1543                                                              NOROUND, UNSIGNED ); }});
1544                            0x2: adduh_r_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1545                                                                ROUND, UNSIGNED ); }});
1546                            0x3: subuh_r_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1547                                                                ROUND, UNSIGNED ); }});
1548                        }
1549                    }
1550                    0x1: decode OP_LO {
1551                        format DspIntOp {
1552                            0x0: addqh_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1553                                                              NOROUND, SIGNED ); }});
1554                            0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1555                                                              NOROUND, SIGNED ); }});
1556                            0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1557                                                                ROUND, SIGNED ); }});
1558                            0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1559                                                                ROUND, SIGNED ); }});
1560                            0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1561                                                           NOSATURATE, &dspctl ); }});
1562                            0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1563                                                             SATURATE, &dspctl ); }});
1564                        }
1565                    }
1566                    0x2: decode OP_LO {
1567                        format DspIntOp {
1568                            0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1569                                                             NOROUND, SIGNED ); }});
1570                            0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1571                                                             NOROUND, SIGNED ); }});
1572                            0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1573                                                               ROUND, SIGNED ); }});
1574                            0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1575                                                               ROUND, SIGNED ); }});
1576                            0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1577                                                              SATURATE, NOROUND, &dspctl ); }});
1578                            0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1579                                                               SATURATE, ROUND, &dspctl ); }});
1580                        }
1581                    }
1582                }
1583            }
1584
1585            //Table A-10 MIPS32 BSHFL Encoding of sa Field
1586            0x4: decode SA {
1587                format BasicOp {
1588                    0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 |
1589                                      Rt.uw<31:24> << 16 |
1590                                      Rt.uw<7:0>   << 8  |
1591                                      Rt.uw<15:8>;
1592                    }});
1593                    0x10: seb({{ Rd.sw = Rt.sb; }});
1594                    0x18: seh({{ Rd.sw = Rt.sh; }});
1595                }
1596            }
1597
1598            0x6: decode FUNCTION_LO {
1599
1600                //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL)
1601                0x0: decode OP_HI {
1602                    0x0: decode OP_LO {
1603                        format DspHiLoOp {
1604                            0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1605                                                             SIMD_FMT_PH, SIGNED, MODE_L ); }});
1606                            0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1607                                                             SIMD_FMT_PH, SIGNED, MODE_L ); }});
1608                            0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw,
1609                                                                 ACDST, SIMD_FMT_PH ); }});
1610                            0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1611                                                               SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1612                            0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1613                                                                 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1614                            0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1615                                                                 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1616                            0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw,
1617                                                                     ACDST, SIMD_FMT_PH, &dspctl ); }});
1618                            0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1619                                                               SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1620                        }
1621                    }
1622                    0x1: decode OP_LO {
1623                        format DspHiLoOp {
1624                            0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1625                                                              SIMD_FMT_PH, SIGNED, MODE_X ); }});
1626                            0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1627                                                              SIMD_FMT_PH, SIGNED, MODE_X ); }});
1628                            0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1629                                                               SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1630                            0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1631                                                                 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1632                            0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1633                                                                 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1634                            0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1635                                                               SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1636                        }
1637                    }
1638                    0x2: decode OP_LO {
1639                        format DspHiLoOp {
1640                            0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1641                                                                 MODE_L, SATURATE, &dspctl ); }});
1642                            0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1643                                                                 MODE_R, SATURATE, &dspctl ); }});
1644                            0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1645                                                                 MODE_L, NOSATURATE, &dspctl ); }});
1646                            0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1647                                                                 MODE_R, NOSATURATE, &dspctl ); }});
1648                        }
1649                    }
1650                    0x3: decode OP_LO {
1651                        format DspHiLoOp {
1652                            0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1653                                                                  SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1654                            0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1655                                                                  SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1656                            0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1657                                                                   SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1658                            0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1659                                                                   SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1660                        }
1661                    }
1662                }
1663
1664                //Table 3.3 MIPS32 APPEND Encoding of the op Field
1665                0x1: decode OP_HI {
1666                    0x0: decode OP_LO {
1667                        format IntOp {
1668                            0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }});
1669                            0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }});
1670                        }
1671                    }
1672                    0x2: decode OP_LO {
1673                        format IntOp {
1674                            0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }});
1675                        }
1676                    }
1677                }
1678
1679                0x7: FailUnimpl::rdhwr();
1680            }
1681
1682            0x7: decode FUNCTION_LO {
1683
1684                //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL)
1685                0x0: decode OP_HI {
1686                    0x0: decode OP_LO {
1687                        format DspHiLoOp {
1688                            0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1689                                                            NOROUND, NOSATURATE, &dspctl ); }});
1690                            0x1: extrv_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1691                                                             NOROUND, NOSATURATE, &dspctl ); }});
1692                            0x2: extp({{ Rt.uw = dspExtp( dspac, RS, &dspctl ); }});
1693                            0x3: extpv({{ Rt.uw = dspExtp( dspac, Rs.uw, &dspctl ); }});
1694                            0x4: extr_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1695                                                              ROUND, NOSATURATE, &dspctl ); }});
1696                            0x5: extrv_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1697                                                               ROUND, NOSATURATE, &dspctl ); }});
1698                            0x6: extr_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1699                                                               ROUND, SATURATE, &dspctl ); }});
1700                            0x7: extrv_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1701                                                                ROUND, SATURATE, &dspctl ); }});
1702                        }
1703                    }
1704                    0x1: decode OP_LO {
1705                        format DspHiLoOp {
1706                            0x2: extpdp({{ Rt.uw = dspExtpd( dspac, RS, &dspctl ); }});
1707                            0x3: extpdpv({{ Rt.uw = dspExtpd( dspac, Rs.uw, &dspctl ); }});
1708                            0x6: extr_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, RS,
1709                                                              NOROUND, SATURATE, &dspctl ); }});
1710                            0x7: extrv_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, Rs.uw,
1711                                                               NOROUND, SATURATE, &dspctl ); }});
1712                        }
1713                    }
1714                    0x2: decode OP_LO {
1715                        format DspIntOp {
1716                            0x2: rddsp({{ Rd.uw = readDSPControl( &dspctl, RDDSPMASK ); }});
1717                            0x3: wrdsp({{ writeDSPControl( &dspctl, Rs.uw, WRDSPMASK ); }});
1718                        }
1719                    }
1720                    0x3: decode OP_LO {
1721                        format DspHiLoOp {
1722                            0x2: shilo({{ if( sext<6>(HILOSA) < 0 )
1723                                              dspac = (uint64_t)dspac << -sext<6>(HILOSA);
1724                                          else
1725                                              dspac = (uint64_t)dspac >> sext<6>(HILOSA); }});
1726                            0x3: shilov({{ if( sext<6>(Rs.sw<5:0>) < 0 )
1727                                              dspac = (uint64_t)dspac << -sext<6>(Rs.sw<5:0>);
1728                                           else
1729                                              dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }});
1730                            0x7: mthlip({{ dspac = dspac << 32;
1731                                           dspac |= Rs.uw;
1732                                           dspctl = insertBits( dspctl, 5, 0,
1733                                                                dspctl<5:0>+32 ); }});
1734                        }
1735                    }
1736                }
1737            }
1738        }
1739    }
1740
1741    0x4: decode OPCODE_LO {
1742        format LoadMemory {
1743            0x0: lb({{ Rt.sw = Mem.sb; }});
1744            0x1: lh({{ Rt.sw = Mem.sh; }});
1745            0x3: lw({{ Rt.sw = Mem.sw; }});
1746            0x4: lbu({{ Rt.uw = Mem.ub; }});
1747            0x5: lhu({{ Rt.uw = Mem.uh; }});
1748        }
1749
1750        format LoadUnalignedMemory {
1751            0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
1752                        Rt.uw = mem_word << mem_shift |
1753                            Rt.uw & mask(mem_shift);
1754                     }});
1755            0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
1756                        Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
1757                            mem_word >> mem_shift;
1758                     }});
1759      }
1760    }
1761
1762    0x5: decode OPCODE_LO {
1763        format StoreMemory {
1764            0x0: sb({{ Mem.ub = Rt<7:0>; }});
1765            0x1: sh({{ Mem.uh = Rt<15:0>; }});
1766            0x3: sw({{ Mem.uw = Rt<31:0>; }});
1767        }
1768
1769        format StoreUnalignedMemory {
1770            0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
1771                        uint32_t mem_shift = 32 - reg_shift;
1772                        mem_word = mem_word & (mask(reg_shift) << mem_shift) |
1773                                   Rt.uw >> reg_shift;
1774                     }});
1775            0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
1776                        mem_word = Rt.uw << reg_shift |
1777                                   mem_word & (mask(reg_shift));
1778                     }});
1779        }
1780
1781        0x7: FailUnimpl::cache();
1782    }
1783
1784    0x6: decode OPCODE_LO {
1785        format LoadMemory {
1786            0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
1787            0x1: lwc1({{ Ft.uw = Mem.uw; }});
1788            0x5: ldc1({{ Ft.ud = Mem.ud; }});
1789        }
1790
1791        0x3: Prefetch::pref();
1792    }
1793
1794
1795    0x7: decode OPCODE_LO {
1796        0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
1797                           {{ uint64_t tmp = write_result;
1798                              Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
1799                           }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
1800
1801        format StoreMemory {
1802            0x1: swc1({{ Mem.uw = Ft.uw; }});
1803            0x5: sdc1({{ Mem.ud = Ft.ud; }});
1804        }
1805    }
1806}
1807
1808
1809