decoder.isa revision 4661:44458219add1 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
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28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual MIPS32 ISA decoder
34// -----------------------------
35// The following instructions are specified in the MIPS32 ISA
36// Specification. Decoding closely follows the style specified
37// in the MIPS32 ISA specification document starting with Table
38// A-2 (document available @ http://www.mips.com)
39//
40decode OPCODE_HI default Unknown::unknown() {
41    //Table A-2
42    0x0: decode OPCODE_LO {
43        0x0: decode FUNCTION_HI {
44            0x0: decode FUNCTION_LO {
45                0x1: decode MOVCI {
46                    format BasicOp {
47                        0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }});
48                        1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }});
49                    }
50                }
51
52                format BasicOp {
53                    //Table A-3 Note: "Specific encodings of the rd, rs, and
54                    //rt fields are used to distinguish SLL, SSNOP, and EHB
55                    //functions
56                    0x0: decode RS  {
57                        0x0: decode RT_RD {
58                            0x0: decode SA default Nop::nop() {
59                                0x1: WarnUnimpl::ssnop();
60                                0x3: WarnUnimpl::ehb();
61                            }
62                            default: sll({{ Rd = Rt.uw << SA; }});
63                        }
64                    }
65
66                    0x2: decode RS_SRL {
67                        0x0:decode SRL {
68                            0: srl({{ Rd = Rt.uw >> SA; }});
69
70                            //Hardcoded assuming 32-bit ISA, probably need parameter here
71                            1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
72                        }
73                    }
74
75                    0x3: decode RS {
76                        0x0: sra({{
77                            uint32_t temp = Rt >> SA;
78                            if ( (Rt & 0x80000000) > 0 ) {
79                                uint32_t mask = 0x80000000;
80                                for(int i=0; i < SA; i++) {
81                                    temp |= mask;
82                                    mask = mask >> 1;
83                                }
84                            }
85                            Rd = temp;
86                        }});
87                    }
88
89                    0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
90
91                    0x6: decode SRLV {
92                        0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
93
94                        //Hardcoded assuming 32-bit ISA, probably need parameter here
95                        1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
96                    }
97
98                    0x7: srav({{
99                        int shift_amt = Rs<4:0>;
100
101                        uint32_t temp = Rt >> shift_amt;
102
103                        if ( (Rt & 0x80000000) > 0 ) {
104                                uint32_t mask = 0x80000000;
105                                for(int i=0; i < shift_amt; i++) {
106                                    temp |= mask;
107                                    mask = mask >> 1;
108                                }
109                            }
110
111                        Rd = temp;
112                    }});
113                }
114            }
115
116            0x1: decode FUNCTION_LO {
117                //Table A-3 Note: "Specific encodings of the hint field are
118                //used to distinguish JR from JR.HB and JALR from JALR.HB"
119                format Jump {
120                    0x0: decode HINT {
121                        0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
122                        default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
123                    }
124
125                    0x1: decode HINT {
126                        0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall
127                                     , ClearHazards);
128                        default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall);
129                    }
130                }
131
132                format BasicOp {
133                    0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
134                    0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
135                    0x4: syscall({{ xc->syscall(R2); }},
136                                 IsSerializeAfter, IsNonSpeculative);
137                    0x7: sync({{ ; }}, IsMemBarrier);
138                }
139
140                format FailUnimpl {
141                    0x5: break();
142                }
143            }
144
145            0x2: decode FUNCTION_LO {
146                0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }});
147                0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
148                0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }});
149                0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
150            }
151
152            0x3: decode FUNCTION_LO {
153                format HiLoRdSelValOp {
154                    0x0: mult({{ val = Rs.sd * Rt.sd; }});
155                    0x1: multu({{ val = Rs.ud * Rt.ud; }});
156                }
157
158                format HiLoOp {
159                    0x2: div({{ if (Rt.sd != 0) {
160                        HI0 = Rs.sd % Rt.sd;
161                        LO0 = Rs.sd / Rt.sd;
162                    }
163                    }});
164                    0x3: divu({{ if (Rt.ud != 0) {
165                        HI0 = Rs.ud % Rt.ud;
166                        LO0 = Rs.ud / Rt.ud;
167                    }
168                    }});
169                }
170            }
171
172            0x4: decode HINT {
173                0x0: decode FUNCTION_LO {
174                    format IntOp {
175                        0x0: add({{  Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
176                        0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
177                        0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;  /*Trap on Overflow*/}});
178                        0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
179                        0x4: and({{ Rd = Rs & Rt;}});
180                        0x5: or({{ Rd = Rs | Rt;}});
181                        0x6: xor({{ Rd = Rs ^ Rt;}});
182                        0x7: nor({{ Rd = ~(Rs | Rt);}});
183                    }
184                }
185            }
186
187            0x5: decode HINT {
188                0x0: decode FUNCTION_LO {
189                    format IntOp{
190                        0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
191                        0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
192                    }
193                }
194            }
195
196            0x6: decode FUNCTION_LO {
197                format Trap {
198                    0x0: tge({{  cond = (Rs.sw >= Rt.sw); }});
199                    0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
200                    0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
201                    0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
202                    0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
203                    0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
204                }
205            }
206        }
207
208        0x1: decode REGIMM_HI {
209            0x0: decode REGIMM_LO {
210                format Branch {
211                    0x0: bltz({{ cond = (Rs.sw < 0); }});
212                    0x1: bgez({{ cond = (Rs.sw >= 0); }});
213                    0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely);
214                    0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely);
215                }
216            }
217
218            0x1: decode REGIMM_LO {
219                format Trap {
220                    0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
221                    0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
222                    0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
223                    0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
224                    0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
225                    0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
226                }
227            }
228
229            0x2: decode REGIMM_LO {
230                format Branch {
231                    0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link);
232                    0x1: decode RS {
233                        0x0: bal ({{ cond = 1; }}, IsCall, Link);
234                        default: bgezal({{ cond = (Rs.sw >= 0); }}, Link);
235                    }
236                    0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely);
237                    0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely);
238                }
239            }
240
241            0x3: decode REGIMM_LO {
242                // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL)
243                0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }});
244                format WarnUnimpl {
245                    0x7: synci();
246                }
247            }
248        }
249
250        format Jump {
251            0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
252            0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall,
253                     Link);
254        }
255
256        format Branch {
257            0x4: decode RS_RT  {
258                0x0: b({{ cond = 1; }});
259                default: beq({{ cond = (Rs.sw == Rt.sw); }});
260            }
261            0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
262            0x6: blez({{ cond = (Rs.sw <= 0); }});
263            0x7: bgtz({{ cond = (Rs.sw > 0); }});
264        }
265    }
266
267    0x1: decode OPCODE_LO {
268        format IntImmOp {
269            0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
270            0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
271            0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
272
273            //Edited to include MIPS AVP Pass/Fail instructions and
274            //default to the sltiu instruction
275            0x3: decode RS_RT_INTIMM {
276                0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }});
277                0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }});
278              default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
279            }
280
281            0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
282            0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
283            0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
284
285            0x7: decode RS {
286                0x0: lui({{ Rt = imm << 16}});
287            }
288        }
289    }
290
291    0x2: decode OPCODE_LO {
292        //Table A-11 MIPS32 COP0 Encoding of rs Field
293        0x0: decode RS_MSB {
294            0x0: decode RS {
295                format CP0Control {
296                    0x0: mfc0({{  Rt = CP0_RD_SEL; }});
297                    0x4: mtc0({{  CP0_RD_SEL = Rt; }});
298                }
299
300
301                format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
302                    0x8: decode MT_U {
303                        0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
304                                                                    Ctrl_Base_DepTag);
305                                   }});
306                        0x1: decode SEL {
307                            0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
308                            0x1: decode RT {
309                                0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }});
310                                0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }});
311                                0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }});
312                                0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }});
313                                0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }});
314                                0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }});
315                                0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }});
316                                0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }});
317                                0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }});
318                                0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }});
319                                0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
320                                0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
321                                0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
322                            }
323                            0x2: decode MT_H {
324                                0x0: mftc1({{ data = xc->readRegOtherThread(RT +
325                                                                            FP_Base_DepTag);
326                                           }});
327                                0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
328                                                                             FP_Base_DepTag);
329                                           }});
330                            }
331                            0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR +
332                                                                            FP_Base_DepTag);
333                                          switch (RT)
334                                          {
335                                               case 0:
336                                                 data = xc->readRegOtherThread(MipsISA::FIR +
337                                                                               Ctrl_Base_DepTag);
338                                                 break;
339                                               case 25:
340                                                 data = 0 | fcsr_val & 0xFE000000 >> 24
341                                                          | fcsr_val & 0x00800000 >> 23;
342                                                 break;
343                                               case 26:
344                                                 data = 0 | fcsr_val & 0x0003F07C;
345                                                 break;
346                                               case 28:
347                                                 data = 0 | fcsr_val & 0x00000F80
348                                                          | fcsr_val & 0x01000000 >> 21
349                                                          | fcsr_val & 0x00000003;
350                                                 break;
351                                               case 31:
352                                                 data = fcsr_val;
353                                                 break;
354                                               default:
355                                                 fatal("FP Control Value (%d) Not Valid");
356                                          }
357                                        }});
358                        }
359                    }
360                }
361
362                format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions
363                    0xC: decode MT_U {
364                        0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
365                                                            Rt);
366                                   }});
367                        0x1: decode SEL {
368                            0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
369                            0x1: decode RT {
370                                0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt);
371                                                }});
372                                0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0,
373                                                                         Rt);
374                                                }});
375                                0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0,
376                                                                          Rt);
377                                                 }});
378                                0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1,
379                                                                         Rt);
380                                                }});
381                                0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1,
382                                                                         Rt);
383                                                }});
384                                0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1,
385                                                                          Rt);
386                                                 }});
387                                0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2,
388                                                                         Rt);
389                                                }});
390                                0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2,
391                                                                         Rt);
392                                                }});
393                                0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2,
394                                                                           Rt);
395                                                  }});
396                                0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3,
397                                                                          Rt);
398                                                 }});
399                                0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3,
400                                                                          Rt);
401                                                 }});
402                                0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
403                                                  }});
404                                0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
405                            }
406                            0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
407                                                                                FP_Base_DepTag);
408                                          data = insertBits(data, top_bit, bottom_bit, Rt);
409                                          xc->setRegOtherThread(RD + FP_Base_DepTag, data);
410                                       }});
411                            0x3: cttc1({{ uint32_t data;
412                                          switch (RD)
413                                          {
414                                            case 25:
415                                              data = 0 | (Rt.uw<7:1> << 25) // move 31...25
416                                                  | (FCSR & 0x01000000) // bit 24
417                                                  | (FCSR & 0x004FFFFF);// bit 22...0
418                                              break;
419
420                                            case 26:
421                                              data = 0 | (FCSR & 0xFFFC0000) // move 31...18
422                                                  | Rt.uw<17:12> << 12           // bit 17...12
423                                                  | (FCSR & 0x00000F80) << 7// bit 11...7
424                                                  | Rt.uw<6:2> << 2              // bit 6...2
425                                                  | (FCSR & 0x00000002);     // bit 1...0
426                                              break;
427
428                                            case 28:
429                                              data = 0 | (FCSR & 0xFE000000) // move 31...25
430                                                  | Rt.uw<2:2> << 24       // bit 24
431                                                  | (FCSR & 0x00FFF000) << 23// bit 23...12
432                                                  | Rt.uw<11:7> << 7       // bit 24
433                                                  | (FCSR & 0x000007E)
434                                                  | Rt.uw<1:0>;// bit 22...0
435                                              break;
436
437                                            case 31:
438                                              data  = Rt.uw;
439                                              break;
440
441                                            default:
442                                              panic("FP Control Value (%d) Not Available. Ignoring Access to"
443                                                    "Floating Control Status Register", FS);
444                                          }
445                                          xc->setRegOtherThread(FCSR, data);
446                                       }});
447                        }
448                    }
449                }
450
451
452                0xB: decode RD {
453                    format MT_Control {
454                        0x0: decode POS {
455                            0x0: decode SEL {
456                                0x1: decode SC {
457                                    0x0: dvpe({{ Rt = MVPControl;
458                                                 if (VPEConf0<VPEC0_MVP:> == 1) {
459                                                     MVPControl = insertBits(MVPControl, MVPC_EVP, 0);
460                                                 }
461                                              }});
462                                    0x1: evpe({{ Rt = MVPControl;
463                                                 if (VPEConf0<VPEC0_MVP:> == 1) {
464                                                     MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
465                                                 }
466                                              }});
467                                }
468                            }
469                        }
470
471                        0x1: decode POS {
472                            0xF: decode SEL {
473                                0x1: decode SC {
474                                    0x0: dmt({{ Rt = VPEControl;
475                                                VPEControl = insertBits(VPEControl, VPEC_TE, 0);
476                                         }});
477                                    0x1: emt({{ Rt = VPEControl;
478                                                VPEControl = insertBits(VPEControl, VPEC_TE, 1);
479                                         }});
480
481                                }
482                            }
483                        }
484                    }
485                    0xC: decode POS {
486                      0x0: decode SC {
487                        0x0: CP0Control::di({{
488                            if(Config_AR >= 1) // Rev 2.0 or beyond?
489                                {
490                                  Rt = Status;
491                                  Status_IE = 0;
492                                }
493                            else // Enable this else branch once we actually set values for Config on init
494                              {
495                                fault = new ReservedInstructionFault();
496                              }
497                          }});
498                        0x1: CP0Control::ei({{
499                            if(Config_AR >= 1)
500                              {
501                                Rt = Status;
502                                Status_IE = 1;
503                              }
504                            else
505                              {
506                                fault = new ReservedInstructionFault();
507                              }
508                          }});
509                      }
510                    }
511                }
512
513                format CP0Control {
514                    0xA: rdpgpr({{
515                      if(Config_AR >= 1)
516                        { // Rev 2 of the architecture
517                          Rd = xc->tcBase()->readIntReg(Rt + NumIntRegs * SRSCtl_PSS);
518                        }
519                      else
520                        {
521                          fault = new ReservedInstructionFault();
522                        }
523                         }});
524                    0xE: wrpgpr({{
525                      if(Config_AR >= 1)
526                        { // Rev 2 of the architecture
527                          xc->tcBase()->setIntReg(Rd + NumIntRegs * SRSCtl_PSS,Rt);
528                        }
529                      else
530                        {
531                          fault = new ReservedInstructionFault();
532                        }
533
534                         }});
535
536                }
537
538            }
539
540            //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
541            0x1: decode FUNCTION {
542              format CP0Control {
543                0x18: eret({{
544                  if(Status_ERL == 1){
545                    Status_ERL = 0;
546                    NPC = ErrorEPC;
547                  }
548                  else{
549                    NPC = EPC;
550                    Status_EXL = 0;
551                    if(Config_AR >= 1 && SRSCtl_HSS > 0 && Status_BEV == 0){
552                      SRSCtl_CSS = SRSCtl_PSS;
553                    }
554                  }
555                  //		  LLFlag = 0;
556                  // ClearHazards(); ?
557                }});
558
559                0x1F: deret({{
560                  // if(EJTagImplemented()) {
561                  if(Debug_DM == 1){
562                    Debug_DM = 1;
563                    Debug_IEXI = 0;
564                    NPC = DEPC;
565                  }
566                  else
567                    {
568                      // Undefined;
569                    }
570                  //} // EJTag Implemented
571                  //else {
572                  // Reserved Instruction Exception
573                  //}
574                }});
575              }
576
577              format FailUnimpl {
578                  0x01: tlbr(); // Need to hook up to TLB
579                  0x02: tlbwi(); // Need to hook up to TLB
580                    0x06: tlbwr();// Need to hook up to TLB
581                    0x08: tlbp();// Need to hook up to TLB
582
583                    0x20: wait();
584                }
585
586            }
587        }
588
589        //Table A-13 MIPS32 COP1 Encoding of rs Field
590        0x1: decode RS_MSB {
591
592            0x0: decode RS_HI {
593                0x0: decode RS_LO {
594                    format CP1Control {
595                        0x0: mfc1 ({{ Rt.uw = Fs.uw; }});
596
597                        0x2: cfc1({{
598                            switch (FS)
599                            {
600                              case 0:
601                                Rt = FIR;
602                                break;
603                              case 25:
604                                Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23;
605                                break;
606                              case 26:
607                                Rt = 0 | (FCSR & 0x0003F07C);
608                                break;
609                              case 28:
610                                Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003);
611                                break;
612                              case 31:
613                                Rt = FCSR;
614                                break;
615                              default:
616                                panic("FP Control Value (%d) Not Valid");
617                            }
618                        }});
619
620                        0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
621
622                        0x4: mtc1 ({{ Fs.uw = Rt.uw;       }});
623
624                        0x6: ctc1({{
625                            switch (FS)
626                            {
627                              case 25:
628                                FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25
629                                    | (FCSR & 0x01000000) // bit 24
630                                    | (FCSR & 0x004FFFFF);// bit 22...0
631                                break;
632
633                              case 26:
634                                FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18
635                                    | Rt.uw<17:12> << 12           // bit 17...12
636                                    | (FCSR & 0x00000F80) << 7// bit 11...7
637                                    | Rt.uw<6:2> << 2              // bit 6...2
638                                    | (FCSR & 0x00000002);     // bit 1...0
639                                break;
640
641                              case 28:
642                                FCSR = 0 | (FCSR & 0xFE000000) // move 31...25
643                                    | Rt.uw<2:2> << 24       // bit 24
644                                    | (FCSR & 0x00FFF000) << 23// bit 23...12
645                                    | Rt.uw<11:7> << 7       // bit 24
646                                    | (FCSR & 0x000007E)
647                                    | Rt.uw<1:0>;// bit 22...0
648                                break;
649
650                              case 31:
651                                FCSR  = Rt.uw;
652                                break;
653
654                              default:
655                                panic("FP Control Value (%d) Not Available. Ignoring Access to"
656                                      "Floating Control Status Register", FS);
657                            }
658                        }});
659
660                        0x7: mthc1({{
661                             uint64_t fs_hi = Rt.uw;
662                             uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF;
663                             Fs.ud = (fs_hi << 32) | fs_lo;
664                        }});
665
666                    }
667                }
668
669                0x1: decode ND {
670                    format Branch {
671                        0x0: decode TF {
672                            0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
673                                      }});
674                            0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
675                                      }});
676                        }
677                        0x1: decode TF {
678                            0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
679                                       }}, Likely);
680                            0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
681                                       }}, Likely);
682                        }
683                    }
684                }
685            }
686
687            0x1: decode RS_HI {
688                0x2: decode RS_LO {
689                    //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
690                    //(( single-precision floating point))
691                    0x0: decode FUNCTION_HI {
692                        0x0: decode FUNCTION_LO {
693                            format FloatOp {
694                                0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}});
695                                0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}});
696                                0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}});
697                                0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}});
698                                0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}});
699                                0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}});
700                                0x7: neg_s({{ Fd.sf = -Fs.sf;}});
701                            }
702
703                            0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}});
704                        }
705
706                        0x1: decode FUNCTION_LO {
707                            format FloatConvertOp {
708                                0x0: round_l_s({{ val = Fs.sf; }}, ToLong,
709                                               Round);
710                                0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong,
711                                               Trunc);
712                                0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong,
713                                               Ceil);
714                                0x3: floor_l_s({{ val = Fs.sf; }}, ToLong,
715                                               Floor);
716                                0x4: round_w_s({{ val = Fs.sf; }}, ToWord,
717                                               Round);
718                                0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord,
719                                               Trunc);
720                                0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord,
721                                               Ceil);
722                                0x7: floor_w_s({{ val = Fs.sf; }}, ToWord,
723                                               Floor);
724                            }
725                        }
726
727                        0x2: decode FUNCTION_LO {
728                            0x1: decode MOVCF {
729                                format BasicOp {
730                                    0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }});
731                                    0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }});
732                                }
733                            }
734
735                            format BasicOp {
736                                0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
737                                0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
738                            }
739
740                            format FloatOp {
741                                0x5: recip_s({{ Fd = 1 / Fs; }});
742                                0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
743                            }
744                        }
745
746                        0x4: decode FUNCTION_LO {
747                            format FloatConvertOp {
748                                0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble);
749                                0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord);
750                                0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong);
751                            }
752
753                            0x6: FloatOp::cvt_ps_s({{
754                                    Fd.ud = (uint64_t) Fs.uw << 32 |
755                                            (uint64_t) Ft.uw;
756                                }});
757                        }
758
759                        0x6: decode FUNCTION_LO {
760                            format FloatCompareOp {
761                                0x0: c_f_s({{ cond = 0; }}, SinglePrecision,
762                                           UnorderedFalse);
763                                0x1: c_un_s({{ cond = 0; }}, SinglePrecision,
764                                            UnorderedTrue);
765                                0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }},
766                                            UnorderedFalse);
767                                0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }},
768                                             UnorderedTrue);
769                                0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf);	}},
770                                             UnorderedFalse);
771                                0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }},
772                                             UnorderedTrue);
773                                0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }},
774                                             UnorderedFalse);
775                                0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }},
776                                             UnorderedTrue);
777                            }
778                        }
779
780                        0x7: decode FUNCTION_LO {
781                            format FloatCompareOp {
782                                0x0: c_sf_s({{ cond = 0; }}, SinglePrecision,
783                                            UnorderedFalse, QnanException);
784                                0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision,
785                                              UnorderedTrue, QnanException);
786                                0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}},
787                                             UnorderedFalse, QnanException);
788                                0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }},
789                                             UnorderedTrue, QnanException);
790                                0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }},
791                                            UnorderedFalse, QnanException);
792                                0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }},
793                                             UnorderedTrue, QnanException);
794                                0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }},
795                                            UnorderedFalse, QnanException);
796                                0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }},
797                                             UnorderedTrue, QnanException);
798                            }
799                        }
800                    }
801
802                    //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
803                    0x1: decode FUNCTION_HI {
804                        0x0: decode FUNCTION_LO {
805                            format FloatOp {
806                                0x0: add_d({{ Fd.df = Fs.df + Ft.df; }});
807                                0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }});
808                                0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }});
809                                0x3: div_d({{ Fd.df = Fs.df / Ft.df; }});
810                                0x4: sqrt_d({{ Fd.df = sqrt(Fs.df);  }});
811                                0x5: abs_d({{ Fd.df = fabs(Fs.df);   }});
812                                0x7: neg_d({{ Fd.df = -1 * Fs.df;    }});
813                            }
814
815                            0x6: BasicOp::mov_d({{ Fd.df = Fs.df;    }});
816                        }
817
818                        0x1: decode FUNCTION_LO {
819                            format FloatConvertOp {
820                                0x0: round_l_d({{ val = Fs.df; }}, ToLong,
821                                               Round);
822                                0x1: trunc_l_d({{ val = Fs.df; }}, ToLong,
823                                               Trunc);
824                                0x2: ceil_l_d({{ val = Fs.df; }}, ToLong,
825                                               Ceil);
826                                0x3: floor_l_d({{ val = Fs.df; }}, ToLong,
827                                               Floor);
828                                0x4: round_w_d({{ val = Fs.df; }}, ToWord,
829                                               Round);
830                                0x5: trunc_w_d({{ val = Fs.df; }}, ToWord,
831                                               Trunc);
832                                0x6: ceil_w_d({{ val = Fs.df; }}, ToWord,
833                                               Ceil);
834                                0x7: floor_w_d({{ val = Fs.df; }}, ToWord,
835                                               Floor);
836                            }
837                        }
838
839                        0x2: decode FUNCTION_LO {
840                            0x1: decode MOVCF {
841                                format BasicOp {
842                                    0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ?
843                                                       Fs.df : Fd.df;
844                                                }});
845                                    0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ?
846                                                       Fs.df : Fd.df;
847                                                }});
848                                }
849                            }
850
851                            format BasicOp {
852                                0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }});
853                                0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }});
854                            }
855
856                            format FloatOp {
857                                0x5: recip_d({{ Fd.df = 1 / Fs.df }});
858                                0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
859                            }
860                        }
861
862                        0x4: decode FUNCTION_LO {
863                            format FloatConvertOp {
864                                0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
865                                0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
866                                0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
867                            }
868                        }
869
870                        0x6: decode FUNCTION_LO {
871                            format FloatCompareOp {
872                                0x0: c_f_d({{ cond = 0; }}, DoublePrecision,
873                                           UnorderedFalse);
874                                0x1: c_un_d({{ cond = 0; }}, DoublePrecision,
875                                            UnorderedTrue);
876                                0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }},
877                                            UnorderedFalse);
878                                0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }},
879                                             UnorderedTrue);
880                                0x4: c_olt_d({{ cond = (Fs.df < Ft.df);	}},
881                                             UnorderedFalse);
882                                0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }},
883                                             UnorderedTrue);
884                                0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }},
885                                             UnorderedFalse);
886                                0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }},
887                                             UnorderedTrue);
888                            }
889                        }
890
891                        0x7: decode FUNCTION_LO {
892                            format FloatCompareOp {
893                                0x0: c_sf_d({{ cond = 0; }}, DoublePrecision,
894                                            UnorderedFalse, QnanException);
895                                0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision,
896                                              UnorderedTrue, QnanException);
897                                0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }},
898                                             UnorderedFalse, QnanException);
899                                0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }},
900                                             UnorderedTrue, QnanException);
901                                0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }},
902                                            UnorderedFalse, QnanException);
903                                0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }},
904                                             UnorderedTrue, QnanException);
905                                0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }},
906                                            UnorderedFalse, QnanException);
907                                0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }},
908                                             UnorderedTrue, QnanException);
909                            }
910                        }
911                    }
912
913                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
914                    0x4: decode FUNCTION {
915                        format FloatConvertOp {
916                            0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
917                            0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
918                            0x26: FailUnimpl::cvt_ps_w();
919                        }
920                    }
921
922                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
923                    //Note: "1. Format type L is legal only if 64-bit floating point operations
924                    //are enabled."
925                    0x5: decode FUNCTION_HI {
926                        format FloatConvertOp {
927                            0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
928                            0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
929                            0x26: FailUnimpl::cvt_ps_l();
930                        }
931                    }
932
933                    //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
934                    //Note: "1. Format type PS is legal only if 64-bit floating point operations
935                    //are enabled. "
936                    0x6: decode FUNCTION_HI {
937                        0x0: decode FUNCTION_LO {
938                            format Float64Op {
939                                0x0: add_ps({{
940                                    Fd1.sf = Fs1.sf + Ft2.sf;
941                                    Fd2.sf = Fs2.sf + Ft2.sf;
942                                }});
943                                0x1: sub_ps({{
944                                    Fd1.sf = Fs1.sf - Ft2.sf;
945                                    Fd2.sf = Fs2.sf - Ft2.sf;
946                                }});
947                                0x2: mul_ps({{
948                                    Fd1.sf = Fs1.sf * Ft2.sf;
949                                    Fd2.sf = Fs2.sf * Ft2.sf;
950                                }});
951                                0x5: abs_ps({{
952                                    Fd1.sf = fabs(Fs1.sf);
953                                    Fd2.sf = fabs(Fs2.sf);
954                                }});
955                                0x6: mov_ps({{
956                                    Fd1.sf = Fs1.sf;
957                                    Fd2.sf = Fs2.sf;
958                                }});
959                                0x7: neg_ps({{
960                                    Fd1.sf = -(Fs1.sf);
961                                    Fd2.sf = -(Fs2.sf);
962                                }});
963                            }
964                        }
965
966                        0x2: decode FUNCTION_LO {
967                            0x1: decode MOVCF {
968                                format Float64Op {
969                                    0x0: movf_ps({{
970                                        Fd1 = (getCondCode(FCSR, CC) == 0) ?
971                                            Fs1 : Fd1;
972                                        Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
973                                            Fs2 : Fd2;
974                                    }});
975                                    0x1: movt_ps({{
976                                        Fd2 = (getCondCode(FCSR, CC) == 1) ?
977                                            Fs1 : Fd1;
978                                        Fd2 = (getCondCode(FCSR, CC+1) == 1) ?
979                                            Fs2 : Fd2;
980                                    }});
981                                }
982                            }
983
984                            format Float64Op {
985                                0x2: movz_ps({{
986                                    Fd1 = (getCondCode(FCSR, CC) == 0) ?
987                                        Fs1 : Fd1;
988                                    Fd2 = (getCondCode(FCSR, CC) == 0) ?
989                                        Fs2 : Fd2;
990                                }});
991                                0x3: movn_ps({{
992                                    Fd1 = (getCondCode(FCSR, CC) == 1) ?
993                                        Fs1 : Fd1;
994                                    Fd2 = (getCondCode(FCSR, CC) == 1) ?
995                                        Fs2 : Fd2;
996                                }});
997                            }
998
999                        }
1000
1001                        0x4: decode FUNCTION_LO {
1002                            0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
1003                        }
1004
1005                        0x5: decode FUNCTION_LO {
1006                            0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }});
1007
1008                            format Float64Op {
1009                                0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1010                                                    Ft1.uw;
1011                                         }});
1012                                0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1013                                                    Ft2.uw;
1014                                         }});
1015                                0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1016                                                    Ft1.uw;
1017                                         }});
1018                                0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1019                                                    Ft2.uw;
1020                                         }});
1021                            }
1022                        }
1023
1024                        0x6: decode FUNCTION_LO {
1025                            format FloatPSCompareOp {
1026                                0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1027                                            UnorderedFalse);
1028                                0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1029                                             UnorderedTrue);
1030                                0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1031                                             {{ cond2 = (Fs2.sf == Ft2.sf); }},
1032                                             UnorderedFalse);
1033                                0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1034                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
1035                                              UnorderedTrue);
1036                                0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
1037                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
1038                                              UnorderedFalse);
1039                                0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }},
1040                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
1041                                              UnorderedTrue);
1042                                0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }},
1043                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1044                                              UnorderedFalse);
1045                                0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1046                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1047                                              UnorderedTrue);
1048                            }
1049                        }
1050
1051                        0x7: decode FUNCTION_LO {
1052                            format FloatPSCompareOp {
1053                                0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1054                                             UnorderedFalse, QnanException);
1055                                0x1: c_ngle_ps({{ cond1 = 0; }},
1056                                               {{ cond2 = 0; }},
1057                                               UnorderedTrue, QnanException);
1058                                0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1059                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
1060                                              UnorderedFalse, QnanException);
1061                                0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1062                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
1063                                              UnorderedTrue, QnanException);
1064                                0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
1065                                             {{ cond2 = (Fs2.sf < Ft2.sf); }},
1066                                             UnorderedFalse, QnanException);
1067                                0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
1068                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
1069                                              UnorderedTrue, QnanException);
1070                                0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1071                                             {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1072                                             UnorderedFalse, QnanException);
1073                                0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1074                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1075                                              UnorderedTrue, QnanException);
1076                            }
1077                        }
1078                    }
1079                }
1080            }
1081        }
1082
1083        //Table A-19 MIPS32 COP2 Encoding of rs Field
1084        0x2: decode RS_MSB {
1085            format FailUnimpl {
1086                0x0: decode RS_HI {
1087                    0x0: decode RS_LO {
1088                        0x0: mfc2();
1089                        0x2: cfc2();
1090                        0x3: mfhc2();
1091                        0x4: mtc2();
1092                        0x6: ctc2();
1093                        0x7: mftc2();
1094                    }
1095
1096                    0x1: decode ND {
1097                        0x0: decode TF {
1098                            0x0: bc2f();
1099                            0x1: bc2t();
1100                        }
1101
1102                        0x1: decode TF {
1103                            0x0: bc2fl();
1104                            0x1: bc2tl();
1105                        }
1106                    }
1107                }
1108            }
1109        }
1110
1111        //Table A-20 MIPS64 COP1X Encoding of Function Field 1
1112        //Note: "COP1X instructions are legal only if 64-bit floating point
1113        //operations are enabled."
1114        0x3: decode FUNCTION_HI {
1115            0x0: decode FUNCTION_LO {
1116                format LoadIndexedMemory {
1117                    0x0: lwxc1({{ Fd.uw = Mem.uw;}});
1118                    0x1: ldxc1({{ Fd.ud = Mem.ud;}});
1119                    0x5: luxc1({{ Fd.ud = Mem.ud;}},
1120                               {{ EA = (Rs + Rt) & ~7; }});
1121                }
1122            }
1123
1124            0x1: decode FUNCTION_LO {
1125                format StoreIndexedMemory {
1126                    0x0: swxc1({{ Mem.uw = Fs.uw;}});
1127                    0x1: sdxc1({{ Mem.ud = Fs.ud;}});
1128                    0x5: suxc1({{ Mem.ud = Fs.ud;}},
1129                               {{ EA = (Rs + Rt) & ~7; }});
1130                }
1131
1132                0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
1133            }
1134
1135            0x3: decode FUNCTION_LO {
1136                0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) {
1137                                               Fd.ud = Fs.ud;
1138                                           } else if (Rs<2:0> == 4) {
1139                                             #if BYTE_ORDER == BIG_ENDIAN
1140                                               Fd.ud = Fs.ud<31:0> << 32 |
1141                                                       Ft.ud<63:32>;
1142                                             #elif BYTE_ORDER == LITTLE_ENDIAN
1143                                               Fd.ud = Ft.ud<31:0> << 32 |
1144                                                       Fs.ud<63:32>;
1145                                             #endif
1146                                           } else {
1147                                               Fd.ud = Fd.ud;
1148                                           }
1149                                        }});
1150            }
1151
1152            format FloatAccOp {
1153                0x4: decode FUNCTION_LO {
1154                    0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }});
1155                    0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }});
1156                    0x6: madd_ps({{
1157                        Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df;
1158                        Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df;
1159                    }});
1160                }
1161
1162                0x5: decode FUNCTION_LO {
1163                    0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }});
1164                    0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }});
1165                    0x6: msub_ps({{
1166                        Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df;
1167                        Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df;
1168                    }});
1169                }
1170
1171                0x6: decode FUNCTION_LO {
1172                    0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
1173                    0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }});
1174                    0x6: nmadd_ps({{
1175                        Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df);
1176                        Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df);
1177                    }});
1178                }
1179
1180                0x7: decode FUNCTION_LO {
1181                    0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
1182                    0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }});
1183                    0x6: nmsub_ps({{
1184                        Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df);
1185                        Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df);
1186                    }});
1187                }
1188
1189            }
1190        }
1191
1192        format Branch {
1193            0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely);
1194            0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely);
1195            0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely);
1196            0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely);
1197        }
1198    }
1199
1200    0x3: decode OPCODE_LO {
1201        //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1202        0x4: decode FUNCTION_HI {
1203            0x0: decode FUNCTION_LO {
1204                0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
1205                                   Rd.sw = temp1<31:0>;
1206                                }});
1207
1208                format HiLoRdSelValOp {
1209                    0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }});
1210                    0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }});
1211                    0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }});
1212                    0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }});
1213                }
1214            }
1215
1216            0x4: decode FUNCTION_LO {
1217                format BasicOp {
1218                    0x0: clz({{ int cnt = 32;
1219                          for (int idx = 31; idx >= 0; idx--) {
1220                              if( Rs<idx:idx> == 1) {
1221                                  cnt = 31 - idx;
1222                                  break;
1223                              }
1224                          }
1225                          Rd.uw = cnt;
1226                       }});
1227                    0x1: clo({{ int cnt = 32;
1228                          for (int idx = 31; idx >= 0; idx--) {
1229                              if( Rs<idx:idx> == 0) {
1230                                  cnt = 31 - idx;
1231                                  break;
1232                              }
1233                          }
1234                          Rd.uw = cnt;
1235                        }});
1236                }
1237            }
1238
1239            0x7: decode FUNCTION_LO {
1240                0x7: FailUnimpl::sdbbp();
1241            }
1242        }
1243
1244        //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2
1245        //of the Architecture
1246        0x7: decode FUNCTION_HI {
1247            0x0: decode FUNCTION_LO {
1248                format BasicOp {
1249                    0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }});
1250                    0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) |
1251                                        bits(Rs.uw, MSB-LSB, 0) << LSB |
1252                                        bits(Rt.uw, LSB-1, 0);
1253                             }});
1254                }
1255            }
1256
1257            0x1: decode FUNCTION_LO {
1258                format MT_Control {
1259                    0x0: fork({{ forkThread(xc->tcBase(), fault, RD, Rs, Rt); }},
1260                              UserMode);
1261                    0x1: yield({{ Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, YQMask); }},
1262                               UserMode);
1263                }
1264
1265                //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL)
1266                0x2: decode OP_HI {
1267                    0x0: decode OP_LO {
1268                        format LoadIndexedMemory {
1269                            0x0: lwx({{ Rd.sw = Mem.sw; }});
1270                            0x4: lhx({{ Rd.sw = Mem.sh; }});
1271                            0x6: lbux({{ Rd.uw = Mem.ub; }});
1272                        }
1273                    }
1274                }
1275                0x4: DspIntOp::insv({{ int pos = dspctl<5:0>;
1276                                       int size = dspctl<12:7>-1;
1277                                       Rt.uw = insertBits( Rt.uw, pos+size, pos, Rs.uw<size:0> ); }});
1278            }
1279
1280            0x2: decode FUNCTION_LO {
1281
1282                //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field (DSP ASE MANUAL)
1283                0x0: decode OP_HI {
1284                    0x0: decode OP_LO {
1285                        format DspIntOp {
1286                            0x0: addu_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1287                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1288                            0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1289                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1290                            0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1291                                                              SATURATE, UNSIGNED, &dspctl ); }});
1292                            0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1293                                                              SATURATE, UNSIGNED, &dspctl ); }});
1294                            0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1295                                                                     MODE_L, &dspctl ); }});
1296                            0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1297                                                                     MODE_R, &dspctl ); }});
1298                        }
1299                    }
1300                    0x1: decode OP_LO {
1301                        format DspIntOp {
1302                            0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1303                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1304                            0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1305                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1306                            0x2: addq_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1307                                                            NOSATURATE, SIGNED, &dspctl ); }});
1308                            0x3: subq_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1309                                                            NOSATURATE, SIGNED, &dspctl ); }});
1310                            0x4: addu_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1311                                                              SATURATE, UNSIGNED, &dspctl ); }});
1312                            0x5: subu_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1313                                                              SATURATE, UNSIGNED, &dspctl ); }});
1314                            0x6: addq_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1315                                                              SATURATE, SIGNED, &dspctl ); }});
1316                            0x7: subq_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1317                                                              SATURATE, SIGNED, &dspctl ); }});
1318                        }
1319                    }
1320                    0x2: decode OP_LO {
1321                        format DspIntOp {
1322                            0x0: addsc({{ int64_t dresult;
1323                                          dresult = Rs.ud + Rt.ud;
1324                                          Rd.sw = dresult<31:0>;
1325                                          dspctl = insertBits( dspctl, 13, 13,
1326                                                               dresult<32:32> ); }});
1327                            0x1: addwc({{ int64_t dresult;
1328                                          dresult = Rs.sd + Rt.sd + dspctl<13:13>;
1329                                          Rd.sw = dresult<31:0>;
1330                                          if( dresult<32:32> != dresult<31:31> )
1331                                              dspctl = insertBits( dspctl, 20, 20, 1 ); }});
1332                            0x2: modsub({{ Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : Rs.sw - Rt.sw<7:0>; }});
1333                            0x4: raddu_w_qb({{ Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> +
1334                                                   Rs.uw<15:8> + Rs.uw<7:0>; }});
1335                            0x6: addq_s_w({{ Rd.sw = dspAdd( Rs.sw, Rt.sw, SIMD_FMT_W,
1336                                                             SATURATE, SIGNED, &dspctl ); }});
1337                            0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W,
1338                                                             SATURATE, SIGNED, &dspctl ); }});
1339                        }
1340                    }
1341                    0x3: decode OP_LO {
1342                        format DspIntOp {
1343                            0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1344                                                                    MODE_L, &dspctl ); }});
1345                            0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1346                                                                    MODE_R, &dspctl ); }});
1347                            0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1348                                                               SATURATE, NOROUND, &dspctl ); }});
1349                            0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1350                                                                SATURATE, ROUND, &dspctl ); }});
1351                        }
1352                    }
1353                }
1354
1355                //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL)
1356                0x1: decode OP_HI {
1357                    0x0: decode OP_LO {
1358                        format DspIntOp {
1359                            0x0: cmpu_eq_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1360                                                       UNSIGNED, CMP_EQ, &dspctl ); }});
1361                            0x1: cmpu_lt_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1362                                                       UNSIGNED, CMP_LT, &dspctl ); }});
1363                            0x2: cmpu_le_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1364                                                       UNSIGNED, CMP_LE, &dspctl ); }});
1365                            0x3: pick_qb({{ Rd.uw = dspPick( Rs.uw, Rt.uw,
1366                                                             SIMD_FMT_QB, &dspctl ); }});
1367                            0x4: cmpgu_eq_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1368                                                                 UNSIGNED, CMP_EQ ); }});
1369                            0x5: cmpgu_lt_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1370                                                                 UNSIGNED, CMP_LT ); }});
1371                            0x6: cmpgu_le_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1372                                                                 UNSIGNED, CMP_LE ); }});
1373                        }
1374                    }
1375                    0x1: decode OP_LO {
1376                        format DspIntOp {
1377                            0x0: cmp_eq_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1378                                                      SIGNED, CMP_EQ, &dspctl ); }});
1379                            0x1: cmp_lt_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1380                                                      SIGNED, CMP_LT, &dspctl ); }});
1381                            0x2: cmp_le_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1382                                                      SIGNED, CMP_LE, &dspctl ); }});
1383                            0x3: pick_ph({{ Rd.uw = dspPick( Rs.uw, Rt.uw,
1384                                                             SIMD_FMT_PH, &dspctl ); }});
1385                            0x4: precrq_qb_ph({{ Rd.uw = Rs.uw<31:24> << 24 |
1386                                                         Rs.uw<15:8> << 16 |
1387                                                         Rt.uw<31:24> << 8 |
1388                                                         Rt.uw<15:8>; }});
1389                            0x5: precr_qb_ph({{ Rd.uw = Rs.uw<23:16> << 24 |
1390                                                         Rs.uw<7:0> << 16 |
1391                                                         Rt.uw<23:16> << 8 |
1392                                                         Rt.uw<7:0>; }});
1393                            0x6: packrl_ph({{ Rd.uw = dspPack( Rs.uw, Rt.uw,
1394                                                               SIMD_FMT_PH ); }});
1395                            0x7: precrqu_s_qb_ph({{ Rd.uw = dspPrecrqu( Rs.uw, Rt.uw, &dspctl ); }});
1396                        }
1397                    }
1398                    0x2: decode OP_LO {
1399                        format DspIntOp {
1400                            0x4: precrq_ph_w({{ Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; }});
1401                            0x5: precrq_rs_ph_w({{ Rd.uw = dspPrecrq( Rs.uw, Rt.uw, SIMD_FMT_W, &dspctl ); }});
1402                        }
1403                    }
1404                    0x3: decode OP_LO {
1405                        format DspIntOp {
1406                            0x0: cmpgdu_eq_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1407                                                                   UNSIGNED, CMP_EQ, &dspctl ); }});
1408                            0x1: cmpgdu_lt_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1409                                                                   UNSIGNED, CMP_LT, &dspctl  ); }});
1410                            0x2: cmpgdu_le_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1411                                                                   UNSIGNED, CMP_LE, &dspctl ); }});
1412                            0x6: precr_sra_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD,
1413                                                                        SIMD_FMT_W, NOROUND ); }});
1414                            0x7: precr_sra_r_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD,
1415                                                                        SIMD_FMT_W, ROUND ); }});
1416                        }
1417                    }
1418                }
1419
1420                //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field (DSP ASE MANUAL)
1421                0x2: decode OP_HI {
1422                    0x0: decode OP_LO {
1423                        format DspIntOp {
1424                            0x1: absq_s_qb({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_QB, &dspctl );}});
1425                            0x2: repl_qb({{ Rd.uw = RS_RT<7:0> << 24 |
1426                                                    RS_RT<7:0> << 16 |
1427                                                    RS_RT<7:0> << 8 |
1428                                                    RS_RT<7:0>; }});
1429                            0x3: replv_qb({{ Rd.sw = Rt.uw<7:0> << 24 |
1430                                                     Rt.uw<7:0> << 16 |
1431                                                     Rt.uw<7:0> << 8 |
1432                                                     Rt.uw<7:0>; }});
1433                            0x4: precequ_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1434                                                                     SIMD_FMT_PH, SIGNED, MODE_L ); }});
1435                            0x5: precequ_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1436                                                                     SIMD_FMT_PH, SIGNED, MODE_R ); }});
1437                            0x6: precequ_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1438                                                                      SIMD_FMT_PH, SIGNED, MODE_LA ); }});
1439                            0x7: precequ_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1440                                                                      SIMD_FMT_PH, SIGNED, MODE_RA ); }});
1441                        }
1442                    }
1443                    0x1: decode OP_LO {
1444                        format DspIntOp {
1445                            0x1: absq_s_ph({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_PH, &dspctl ); }});
1446                            0x2: repl_ph({{ Rd.uw = (sext<10>(RS_RT))<15:0> << 16 |
1447                                                    (sext<10>(RS_RT))<15:0>; }});
1448                            0x3: replv_ph({{ Rd.uw = Rt.uw<15:0> << 16 |
1449                                                     Rt.uw<15:0>; }});
1450                            0x4: preceq_w_phl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED,
1451                                                                   SIMD_FMT_W, SIGNED, MODE_L ); }});
1452                            0x5: preceq_w_phr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED,
1453                                                                   SIMD_FMT_W, SIGNED, MODE_R ); }});
1454                        }
1455                    }
1456                    0x2: decode OP_LO {
1457                        format DspIntOp {
1458                            0x1: absq_s_w({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_W, &dspctl ); }});
1459                        }
1460                    }
1461                    0x3: decode OP_LO {
1462                        0x3: IntOp::bitrev({{ Rd.uw = bitrev( Rt.uw<15:0> ); }});
1463                        format DspIntOp {
1464                            0x4: preceu_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1465                                                                    SIMD_FMT_PH, UNSIGNED, MODE_L ); }});
1466                            0x5: preceu_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1467                                                                    SIMD_FMT_PH, UNSIGNED, MODE_R ); }});
1468                            0x6: preceu_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1469                                                                     SIMD_FMT_PH, UNSIGNED, MODE_LA ); }});
1470                            0x7: preceu_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1471                                                                     SIMD_FMT_PH, UNSIGNED, MODE_RA ); }});
1472                        }
1473                    }
1474                }
1475
1476                //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field (DSP ASE MANUAL)
1477                0x3: decode OP_HI {
1478                    0x0: decode OP_LO {
1479                        format DspIntOp {
1480                            0x0: shll_qb({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_QB,
1481                                                             NOSATURATE, UNSIGNED, &dspctl ); }});
1482                            0x1: shrl_qb({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_QB,
1483                                                             UNSIGNED ); }});
1484                            0x2: shllv_qb({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_QB,
1485                                                              NOSATURATE, UNSIGNED, &dspctl ); }});
1486                            0x3: shrlv_qb({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_QB,
1487                                                              UNSIGNED ); }});
1488                            0x4: shra_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB,
1489                                                             NOROUND, SIGNED, &dspctl ); }});
1490                            0x5: shra_r_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB,
1491                                                               ROUND, SIGNED, &dspctl ); }});
1492                            0x6: shrav_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB,
1493                                                              NOROUND, SIGNED, &dspctl ); }});
1494                            0x7: shrav_r_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB,
1495                                                                ROUND, SIGNED, &dspctl ); }});
1496                        }
1497                    }
1498                    0x1: decode OP_LO {
1499                        format DspIntOp {
1500                            0x0: shll_ph({{ Rd.uw = dspShll( Rt.uw, RS, SIMD_FMT_PH,
1501                                                             NOSATURATE, SIGNED, &dspctl ); }});
1502                            0x1: shra_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH,
1503                                                             NOROUND, SIGNED, &dspctl ); }});
1504                            0x2: shllv_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH,
1505                                                              NOSATURATE, SIGNED, &dspctl ); }});
1506                            0x3: shrav_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH,
1507                                                              NOROUND, SIGNED, &dspctl ); }});
1508                            0x4: shll_s_ph({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_PH,
1509                                                               SATURATE, SIGNED, &dspctl ); }});
1510                            0x5: shra_r_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH,
1511                                                               ROUND, SIGNED, &dspctl ); }});
1512                            0x6: shllv_s_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH,
1513                                                                SATURATE, SIGNED, &dspctl ); }});
1514                            0x7: shrav_r_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH,
1515                                                                ROUND, SIGNED, &dspctl ); }});
1516                        }
1517                    }
1518                    0x2: decode OP_LO {
1519                        format DspIntOp {
1520                            0x4: shll_s_w({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_W,
1521                                                              SATURATE, SIGNED, &dspctl ); }});
1522                            0x5: shra_r_w({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_W,
1523                                                              ROUND, SIGNED, &dspctl ); }});
1524                            0x6: shllv_s_w({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_W,
1525                                                               SATURATE, SIGNED, &dspctl ); }});
1526                            0x7: shrav_r_w({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_W,
1527                                                               ROUND, SIGNED, &dspctl ); }});
1528                        }
1529                    }
1530                    0x3: decode OP_LO {
1531                        format DspIntOp {
1532                            0x1: shrl_ph({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_PH,
1533                                                             UNSIGNED ); }});
1534                            0x3: shrlv_ph({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_PH,
1535                                                              UNSIGNED ); }});
1536                        }
1537                    }
1538                }
1539            }
1540
1541            0x3: decode FUNCTION_LO {
1542
1543                //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field (DSP ASE Rev2 Manual)
1544                0x0: decode OP_HI {
1545                    0x0: decode OP_LO {
1546                        format DspIntOp {
1547                            0x0: adduh_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1548                                                              NOROUND, UNSIGNED ); }});
1549                            0x1: subuh_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1550                                                              NOROUND, UNSIGNED ); }});
1551                            0x2: adduh_r_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1552                                                                ROUND, UNSIGNED ); }});
1553                            0x3: subuh_r_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1554                                                                ROUND, UNSIGNED ); }});
1555                        }
1556                    }
1557                    0x1: decode OP_LO {
1558                        format DspIntOp {
1559                            0x0: addqh_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1560                                                              NOROUND, SIGNED ); }});
1561                            0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1562                                                              NOROUND, SIGNED ); }});
1563                            0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1564                                                                ROUND, SIGNED ); }});
1565                            0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1566                                                                ROUND, SIGNED ); }});
1567                            0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1568                                                           NOSATURATE, &dspctl ); }});
1569                            0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1570                                                             SATURATE, &dspctl ); }});
1571                        }
1572                    }
1573                    0x2: decode OP_LO {
1574                        format DspIntOp {
1575                            0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1576                                                             NOROUND, SIGNED ); }});
1577                            0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1578                                                             NOROUND, SIGNED ); }});
1579                            0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1580                                                               ROUND, SIGNED ); }});
1581                            0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1582                                                               ROUND, SIGNED ); }});
1583                            0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1584                                                              SATURATE, NOROUND, &dspctl ); }});
1585                            0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1586                                                               SATURATE, ROUND, &dspctl ); }});
1587                        }
1588                    }
1589                }
1590            }
1591
1592            //Table A-10 MIPS32 BSHFL Encoding of sa Field
1593            0x4: decode SA {
1594                format BasicOp {
1595                    0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 |
1596                                      Rt.uw<31:24> << 16 |
1597                                      Rt.uw<7:0>   << 8  |
1598                                      Rt.uw<15:8>;
1599                    }});
1600                    0x10: seb({{ Rd.sw = Rt.sb; }});
1601                    0x18: seh({{ Rd.sw = Rt.sh; }});
1602                }
1603            }
1604
1605            0x6: decode FUNCTION_LO {
1606
1607                //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL)
1608                0x0: decode OP_HI {
1609                    0x0: decode OP_LO {
1610                        format DspHiLoOp {
1611                            0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1612                                                             SIMD_FMT_PH, SIGNED, MODE_L ); }});
1613                            0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1614                                                             SIMD_FMT_PH, SIGNED, MODE_L ); }});
1615                            0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw,
1616                                                                 ACDST, SIMD_FMT_PH ); }});
1617                            0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1618                                                               SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1619                            0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1620                                                                 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1621                            0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1622                                                                 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1623                            0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw,
1624                                                                     ACDST, SIMD_FMT_PH, &dspctl ); }});
1625                            0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1626                                                               SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1627                        }
1628                    }
1629                    0x1: decode OP_LO {
1630                        format DspHiLoOp {
1631                            0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1632                                                              SIMD_FMT_PH, SIGNED, MODE_X ); }});
1633                            0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1634                                                              SIMD_FMT_PH, SIGNED, MODE_X ); }});
1635                            0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1636                                                               SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1637                            0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1638                                                                 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1639                            0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1640                                                                 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1641                            0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1642                                                               SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1643                        }
1644                    }
1645                    0x2: decode OP_LO {
1646                        format DspHiLoOp {
1647                            0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1648                                                                 MODE_L, SATURATE, &dspctl ); }});
1649                            0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1650                                                                 MODE_R, SATURATE, &dspctl ); }});
1651                            0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1652                                                                 MODE_L, NOSATURATE, &dspctl ); }});
1653                            0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1654                                                                 MODE_R, NOSATURATE, &dspctl ); }});
1655                        }
1656                    }
1657                    0x3: decode OP_LO {
1658                        format DspHiLoOp {
1659                            0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1660                                                                  SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1661                            0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1662                                                                  SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1663                            0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1664                                                                   SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1665                            0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1666                                                                   SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1667                        }
1668                    }
1669                }
1670
1671                //Table 3.3 MIPS32 APPEND Encoding of the op Field
1672                0x1: decode OP_HI {
1673                    0x0: decode OP_LO {
1674                        format IntOp {
1675                            0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }});
1676                            0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }});
1677                        }
1678                    }
1679                    0x2: decode OP_LO {
1680                        format IntOp {
1681                            0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }});
1682                        }
1683                    }
1684                }
1685
1686                0x7: FailUnimpl::rdhwr();
1687            }
1688
1689            0x7: decode FUNCTION_LO {
1690
1691                //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL)
1692                0x0: decode OP_HI {
1693                    0x0: decode OP_LO {
1694                        format DspHiLoOp {
1695                            0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1696                                                            NOROUND, NOSATURATE, &dspctl ); }});
1697                            0x1: extrv_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1698                                                             NOROUND, NOSATURATE, &dspctl ); }});
1699                            0x2: extp({{ Rt.uw = dspExtp( dspac, RS, &dspctl ); }});
1700                            0x3: extpv({{ Rt.uw = dspExtp( dspac, Rs.uw, &dspctl ); }});
1701                            0x4: extr_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1702                                                              ROUND, NOSATURATE, &dspctl ); }});
1703                            0x5: extrv_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1704                                                               ROUND, NOSATURATE, &dspctl ); }});
1705                            0x6: extr_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1706                                                               ROUND, SATURATE, &dspctl ); }});
1707                            0x7: extrv_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1708                                                                ROUND, SATURATE, &dspctl ); }});
1709                        }
1710                    }
1711                    0x1: decode OP_LO {
1712                        format DspHiLoOp {
1713                            0x2: extpdp({{ Rt.uw = dspExtpd( dspac, RS, &dspctl ); }});
1714                            0x3: extpdpv({{ Rt.uw = dspExtpd( dspac, Rs.uw, &dspctl ); }});
1715                            0x6: extr_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, RS,
1716                                                              NOROUND, SATURATE, &dspctl ); }});
1717                            0x7: extrv_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, Rs.uw,
1718                                                               NOROUND, SATURATE, &dspctl ); }});
1719                        }
1720                    }
1721                    0x2: decode OP_LO {
1722                        format DspIntOp {
1723                            0x2: rddsp({{ Rd.uw = readDSPControl( &dspctl, RDDSPMASK ); }});
1724                            0x3: wrdsp({{ writeDSPControl( &dspctl, Rs.uw, WRDSPMASK ); }});
1725                        }
1726                    }
1727                    0x3: decode OP_LO {
1728                        format DspHiLoOp {
1729                            0x2: shilo({{ if( sext<6>(HILOSA) < 0 )
1730                                              dspac = (uint64_t)dspac << -sext<6>(HILOSA);
1731                                          else
1732                                              dspac = (uint64_t)dspac >> sext<6>(HILOSA); }});
1733                            0x3: shilov({{ if( sext<6>(Rs.sw<5:0>) < 0 )
1734                                              dspac = (uint64_t)dspac << -sext<6>(Rs.sw<5:0>);
1735                                           else
1736                                              dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }});
1737                            0x7: mthlip({{ dspac = dspac << 32;
1738                                           dspac |= Rs.uw;
1739                                           dspctl = insertBits( dspctl, 5, 0,
1740                                                                dspctl<5:0>+32 ); }});
1741                        }
1742                    }
1743                }
1744            }
1745        }
1746    }
1747
1748    0x4: decode OPCODE_LO {
1749        format LoadMemory {
1750            0x0: lb({{ Rt.sw = Mem.sb; }});
1751            0x1: lh({{ Rt.sw = Mem.sh; }});
1752            0x3: lw({{ Rt.sw = Mem.sw; }});
1753            0x4: lbu({{ Rt.uw = Mem.ub; }});
1754            0x5: lhu({{ Rt.uw = Mem.uh; }});
1755        }
1756
1757        format LoadUnalignedMemory {
1758            0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
1759                        Rt.uw = mem_word << mem_shift |
1760                            Rt.uw & mask(mem_shift);
1761                     }});
1762            0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
1763                        Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
1764                            mem_word >> mem_shift;
1765                     }});
1766      }
1767    }
1768
1769    0x5: decode OPCODE_LO {
1770        format StoreMemory {
1771            0x0: sb({{ Mem.ub = Rt<7:0>; }});
1772            0x1: sh({{ Mem.uh = Rt<15:0>; }});
1773            0x3: sw({{ Mem.uw = Rt<31:0>; }});
1774        }
1775
1776        format StoreUnalignedMemory {
1777            0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
1778                        uint32_t mem_shift = 32 - reg_shift;
1779                        mem_word = mem_word & (mask(reg_shift) << mem_shift) |
1780                                   Rt.uw >> reg_shift;
1781                     }});
1782            0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
1783                        mem_word = Rt.uw << reg_shift |
1784                                   mem_word & (mask(reg_shift));
1785                     }});
1786        }
1787
1788        0x7: FailUnimpl::cache();
1789    }
1790
1791    0x6: decode OPCODE_LO {
1792        format LoadMemory {
1793            0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
1794            0x1: lwc1({{ Ft.uw = Mem.uw; }});
1795            0x5: ldc1({{ Ft.ud = Mem.ud; }});
1796        }
1797
1798        0x3: Prefetch::pref();
1799    }
1800
1801
1802    0x7: decode OPCODE_LO {
1803        0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
1804                           {{ uint64_t tmp = write_result;
1805                              Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
1806                           }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
1807
1808        format StoreMemory {
1809            0x1: swc1({{ Mem.uw = Ft.uw; }});
1810            0x5: sdc1({{ Mem.ud = Ft.ud; }});
1811        }
1812    }
1813}
1814
1815
1816