decoder.isa revision 4056:f8f1dffc5913
1// -*- mode:c++ -*- 2 3// Copyright (c) 2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual MIPS32 ISA decoder 34// ----------------------------- 35// The following instructions are specified in the MIPS32 ISA 36// Specification. Decoding closely follows the style specified 37// in the MIPS32 ISA specification document starting with Table 38// A-2 (document available @ www.mips.com) 39// 40decode OPCODE_HI default Unknown::unknown() { 41 //Table A-2 42 0x0: decode OPCODE_LO { 43 0x0: decode FUNCTION_HI { 44 0x0: decode FUNCTION_LO { 45 0x1: decode MOVCI { 46 format BasicOp { 47 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }}); 48 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }}); 49 } 50 } 51 52 format BasicOp { 53 //Table A-3 Note: "Specific encodings of the rd, rs, and 54 //rt fields are used to distinguish SLL, SSNOP, and EHB 55 //functions 56 0x0: decode RS { 57 0x0: decode RT_RD { 58 0x0: decode SA default Nop::nop(){ 59 0x1: WarnUnimpl::ssnop(); 60 0x3: WarnUnimpl::ehb(); 61 } 62 default: sll({{ Rd = Rt.uw << SA; }}); 63 } 64 } 65 66 0x2: decode RS_SRL { 67 0x0:decode SRL { 68 0: srl({{ Rd = Rt.uw >> SA; }}); 69 70 //Hardcoded assuming 32-bit ISA, probably need parameter here 71 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 72 } 73 } 74 75 0x3: decode RS { 76 0x0: sra({{ 77 uint32_t temp = Rt >> SA; 78 if ( (Rt & 0x80000000) > 0 ) { 79 uint32_t mask = 0x80000000; 80 for(int i=0; i < SA; i++) { 81 temp |= mask; 82 mask = mask >> 1; 83 } 84 } 85 Rd = temp; 86 }}); 87 } 88 89 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 90 91 0x6: decode SRLV { 92 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 93 94 //Hardcoded assuming 32-bit ISA, probably need parameter here 95 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 96 } 97 98 0x7: srav({{ 99 int shift_amt = Rs<4:0>; 100 101 uint32_t temp = Rt >> shift_amt; 102 103 if ( (Rt & 0x80000000) > 0 ) { 104 uint32_t mask = 0x80000000; 105 for(int i=0; i < shift_amt; i++) { 106 temp |= mask; 107 mask = mask >> 1; 108 } 109 } 110 111 Rd = temp; 112 }}); 113 } 114 } 115 116 0x1: decode FUNCTION_LO { 117 //Table A-3 Note: "Specific encodings of the hint field are 118 //used to distinguish JR from JR.HB and JALR from JALR.HB" 119 format Jump { 120 0x0: decode HINT { 121 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards); 122 default: jr({{ NNPC = Rs & ~1; }}, IsReturn); 123 } 124 125 0x1: decode HINT { 126 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall, Link 127 , ClearHazards); 128 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall, 129 Link); 130 } 131 } 132 133 format BasicOp { 134 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 135 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 136 0x4: syscall({{ xc->syscall(R2); }}, 137 IsSerializeAfter, IsNonSpeculative); 138 0x7: sync({{ ; }}, IsMemBarrier); 139 } 140 141 format FailUnimpl { 142 0x5: break(); 143 } 144 } 145 146 0x2: decode FUNCTION_LO { 147 format HiLoMiscOp { 148 0x0: mfhi({{ Rd = HI; }}); 149 0x1: mthi({{ HI = Rs; }}); 150 0x2: mflo({{ Rd = LO; }}); 151 0x3: mtlo({{ LO = Rs; }}); 152 } 153 } 154 155 0x3: decode FUNCTION_LO { 156 format HiLoOp { 157 0x0: mult({{ int64_t val = Rs.sd * Rt.sd; }}); 158 0x1: multu({{ uint64_t val = Rs.ud * Rt.ud; }}); 159 0x2: div({{ //Initialized to placate g++ 160 int64_t val = 0; 161 if (Rt.sd != 0) { 162 int64_t hi = Rs.sd % Rt.sd; 163 int64_t lo = Rs.sd / Rt.sd; 164 val = (hi << 32) | lo; 165 } 166 }}); 167 0x3: divu({{ //Initialized to placate g++ 168 uint64_t val = 0; 169 if (Rt.ud != 0) { 170 uint64_t hi = Rs.ud % Rt.ud; 171 uint64_t lo = Rs.ud / Rt.ud; 172 val = (hi << 32) | lo; 173 } 174 }}); 175 } 176 } 177 178 0x4: decode HINT { 179 0x0: decode FUNCTION_LO { 180 format IntOp { 181 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}}); 182 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 183 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); 184 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 185 0x4: and({{ Rd = Rs & Rt;}}); 186 0x5: or({{ Rd = Rs | Rt;}}); 187 0x6: xor({{ Rd = Rs ^ Rt;}}); 188 0x7: nor({{ Rd = ~(Rs | Rt);}}); 189 } 190 } 191 } 192 193 0x5: decode HINT { 194 0x0: decode FUNCTION_LO { 195 format IntOp{ 196 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 197 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 198 } 199 } 200 } 201 202 0x6: decode FUNCTION_LO { 203 format Trap { 204 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 205 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 206 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 207 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 208 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 209 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 210 } 211 } 212 } 213 214 0x1: decode REGIMM_HI { 215 0x0: decode REGIMM_LO { 216 format Branch { 217 0x0: bltz({{ cond = (Rs.sw < 0); }}); 218 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 219 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely); 220 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely); 221 } 222 } 223 224 0x1: decode REGIMM_LO { 225 format Trap { 226 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 227 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 228 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 229 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 230 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 231 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 232 } 233 } 234 235 0x2: decode REGIMM_LO { 236 format Branch { 237 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link); 238 0x1: decode RS { 239 0x0: bal ({{ cond = 1; }}, IsCall, Link); 240 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link); 241 } 242 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely); 243 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely); 244 } 245 } 246 247 0x3: decode REGIMM_LO { 248 format WarnUnimpl { 249 0x7: synci(); 250 } 251 } 252 } 253 254 format Jump { 255 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 256 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall, 257 Link); 258 } 259 260 format Branch { 261 0x4: decode RS_RT { 262 0x0: b({{ cond = 1; }}); 263 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 264 } 265 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 266 0x6: blez({{ cond = (Rs.sw <= 0); }}); 267 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 268 } 269 } 270 271 0x1: decode OPCODE_LO { 272 format IntImmOp { 273 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 274 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 275 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 276 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 277 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 278 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 279 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 280 281 0x7: decode RS { 282 0x0: lui({{ Rt = imm << 16}}); 283 } 284 } 285 } 286 287 0x2: decode OPCODE_LO { 288 //Table A-11 MIPS32 COP0 Encoding of rs Field 289 0x0: decode RS_MSB { 290 0x0: decode RS { 291 format CP0Control { 292 0x0: mfc0({{ Rt = xc->readMiscReg(RD << 5 | SEL); }}); 293 0x4: mtc0({{ xc->setMiscReg(RD << 5 | SEL, Rt); }}); 294 } 295 296 format MipsMT { 297 0x8: mftr(); 298 0xC: mttr(); 299 0xB: decode RD { 300 0x0: decode SC { 301 0x0: dvpe(); 302 0x1: evpe(); 303 } 304 0x1: decode SC { 305 0x0: dmt(); 306 0x1: emt(); 307 0xC: decode SC { 308 0x0: di(); 309 0x1: ei(); 310 } 311 } 312 } 313 } 314 315 format FailUnimpl { 316 0xA: rdpgpr(); 317 0xE: wrpgpr(); 318 } 319 } 320 321 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 322 0x1: decode FUNCTION { 323 format FailUnimpl { 324 0x01: tlbr(); 325 0x02: tlbwi(); 326 0x06: tlbwr(); 327 0x08: tlbp(); 328 329 0x18: eret(); 330 0x1F: deret(); 331 0x20: wait(); 332 } 333 } 334 } 335 336 //Table A-13 MIPS32 COP1 Encoding of rs Field 337 0x1: decode RS_MSB { 338 339 0x0: decode RS_HI { 340 0x0: decode RS_LO { 341 format CP1Control { 342 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 343 344 0x2: cfc1({{ 345 switch (FS) 346 { 347 case 0: 348 Rt = FIR; 349 break; 350 case 25: 351 Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23; 352 break; 353 case 26: 354 Rt = 0 | (FCSR & 0x0003F07C); 355 break; 356 case 28: 357 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003); 358 break; 359 case 31: 360 Rt = FCSR; 361 break; 362 default: 363 panic("FP Control Value (%d) Not Valid"); 364 } 365 }}); 366 367 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 368 369 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 370 371 0x6: ctc1({{ 372 switch (FS) 373 { 374 case 25: 375 FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25 376 | (FCSR & 0x01000000) // bit 24 377 | (FCSR & 0x004FFFFF);// bit 22...0 378 break; 379 380 case 26: 381 FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18 382 | Rt.uw<17:12> << 12 // bit 17...12 383 | (FCSR & 0x00000F80) << 7// bit 11...7 384 | Rt.uw<6:2> << 2 // bit 6...2 385 | (FCSR & 0x00000002); // bit 1...0 386 break; 387 388 case 28: 389 FCSR = 0 | (FCSR & 0xFE000000) // move 31...25 390 | Rt.uw<2:2> << 24 // bit 24 391 | (FCSR & 0x00FFF000) << 23// bit 23...12 392 | Rt.uw<11:7> << 7 // bit 24 393 | (FCSR & 0x000007E) 394 | Rt.uw<1:0>;// bit 22...0 395 break; 396 397 case 31: 398 FCSR = Rt.uw; 399 break; 400 401 default: 402 panic("FP Control Value (%d) Not Available. Ignoring Access to" 403 "Floating Control Status Register", FS); 404 } 405 }}); 406 407 0x7: mthc1({{ 408 uint64_t fs_hi = Rt.uw; 409 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 410 Fs.ud = (fs_hi << 32) | fs_lo; 411 }}); 412 413 } 414 } 415 416 0x1: decode ND { 417 format Branch { 418 0x0: decode TF { 419 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 420 }}); 421 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 422 }}); 423 } 424 0x1: decode TF { 425 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 426 }}, Likely); 427 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 428 }}, Likely); 429 } 430 } 431 } 432 } 433 434 0x1: decode RS_HI { 435 0x2: decode RS_LO { 436 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 437 //(( single-precision floating point)) 438 0x0: decode FUNCTION_HI { 439 0x0: decode FUNCTION_LO { 440 format FloatOp { 441 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 442 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 443 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 444 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 445 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 446 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 447 0x7: neg_s({{ Fd.sf = -Fs.sf;}}); 448 } 449 450 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}}); 451 } 452 453 0x1: decode FUNCTION_LO { 454 format FloatConvertOp { 455 0x0: round_l_s({{ val = Fs.sf; }}, ToLong, 456 Round); 457 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong, 458 Trunc); 459 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong, 460 Ceil); 461 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong, 462 Floor); 463 0x4: round_w_s({{ val = Fs.sf; }}, ToWord, 464 Round); 465 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord, 466 Trunc); 467 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord, 468 Ceil); 469 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord, 470 Floor); 471 } 472 } 473 474 0x2: decode FUNCTION_LO { 475 0x1: decode MOVCF { 476 format BasicOp { 477 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }}); 478 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }}); 479 } 480 } 481 482 format BasicOp { 483 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 484 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 485 } 486 487 format FloatOp { 488 0x5: recip_s({{ Fd = 1 / Fs; }}); 489 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); 490 } 491 } 492 493 0x4: decode FUNCTION_LO { 494 format FloatConvertOp { 495 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 496 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 497 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 498 } 499 500 0x6: FloatOp::cvt_ps_s({{ 501 Fd.ud = (uint64_t) Fs.uw << 32 | 502 (uint64_t) Ft.uw; 503 }}); 504 } 505 506 0x6: decode FUNCTION_LO { 507 format FloatCompareOp { 508 0x0: c_f_s({{ cond = 0; }}, SinglePrecision, 509 UnorderedFalse); 510 0x1: c_un_s({{ cond = 0; }}, SinglePrecision, 511 UnorderedTrue); 512 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 513 UnorderedFalse); 514 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 515 UnorderedTrue); 516 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 517 UnorderedFalse); 518 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 519 UnorderedTrue); 520 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }}, 521 UnorderedFalse); 522 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }}, 523 UnorderedTrue); 524 } 525 } 526 527 0x7: decode FUNCTION_LO { 528 format FloatCompareOp { 529 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 530 UnorderedFalse, QnanException); 531 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 532 UnorderedTrue, QnanException); 533 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}}, 534 UnorderedFalse, QnanException); 535 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 536 UnorderedTrue, QnanException); 537 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 538 UnorderedFalse, QnanException); 539 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 540 UnorderedTrue, QnanException); 541 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 542 UnorderedFalse, QnanException); 543 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 544 UnorderedTrue, QnanException); 545 } 546 } 547 } 548 549 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 550 0x1: decode FUNCTION_HI { 551 0x0: decode FUNCTION_LO { 552 format FloatOp { 553 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 554 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 555 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 556 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); 557 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 558 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 559 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); 560 } 561 562 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); 563 } 564 565 0x1: decode FUNCTION_LO { 566 format FloatConvertOp { 567 0x0: round_l_d({{ val = Fs.df; }}, ToLong, 568 Round); 569 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong, 570 Trunc); 571 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong, 572 Ceil); 573 0x3: floor_l_d({{ val = Fs.df; }}, ToLong, 574 Floor); 575 0x4: round_w_d({{ val = Fs.df; }}, ToWord, 576 Round); 577 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord, 578 Trunc); 579 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord, 580 Ceil); 581 0x7: floor_w_d({{ val = Fs.df; }}, ToWord, 582 Floor); 583 } 584 } 585 586 0x2: decode FUNCTION_LO { 587 0x1: decode MOVCF { 588 format BasicOp { 589 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ? 590 Fs.df : Fd.df; 591 }}); 592 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ? 593 Fs.df : Fd.df; 594 }}); 595 } 596 } 597 598 format BasicOp { 599 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }}); 600 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }}); 601 } 602 603 format FloatOp { 604 0x5: recip_d({{ Fd.df = 1 / Fs.df }}); 605 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }}); 606 } 607 } 608 609 0x4: decode FUNCTION_LO { 610 format FloatConvertOp { 611 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 612 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 613 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 614 } 615 } 616 617 0x6: decode FUNCTION_LO { 618 format FloatCompareOp { 619 0x0: c_f_d({{ cond = 0; }}, DoublePrecision, 620 UnorderedFalse); 621 0x1: c_un_d({{ cond = 0; }}, DoublePrecision, 622 UnorderedTrue); 623 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 624 UnorderedFalse); 625 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 626 UnorderedTrue); 627 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 628 UnorderedFalse); 629 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 630 UnorderedTrue); 631 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }}, 632 UnorderedFalse); 633 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }}, 634 UnorderedTrue); 635 } 636 } 637 638 0x7: decode FUNCTION_LO { 639 format FloatCompareOp { 640 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 641 UnorderedFalse, QnanException); 642 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 643 UnorderedTrue, QnanException); 644 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }}, 645 UnorderedFalse, QnanException); 646 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }}, 647 UnorderedTrue, QnanException); 648 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }}, 649 UnorderedFalse, QnanException); 650 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 651 UnorderedTrue, QnanException); 652 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 653 UnorderedFalse, QnanException); 654 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 655 UnorderedTrue, QnanException); 656 } 657 } 658 } 659 660 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 661 0x4: decode FUNCTION { 662 format FloatConvertOp { 663 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 664 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 665 0x26: FailUnimpl::cvt_ps_w(); 666 } 667 } 668 669 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 670 //Note: "1. Format type L is legal only if 64-bit floating point operations 671 //are enabled." 672 0x5: decode FUNCTION_HI { 673 format FloatConvertOp { 674 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 675 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 676 0x26: FailUnimpl::cvt_ps_l(); 677 } 678 } 679 680 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 681 //Note: "1. Format type PS is legal only if 64-bit floating point operations 682 //are enabled. " 683 0x6: decode FUNCTION_HI { 684 0x0: decode FUNCTION_LO { 685 format Float64Op { 686 0x0: add_ps({{ 687 Fd1.sf = Fs1.sf + Ft2.sf; 688 Fd2.sf = Fs2.sf + Ft2.sf; 689 }}); 690 0x1: sub_ps({{ 691 Fd1.sf = Fs1.sf - Ft2.sf; 692 Fd2.sf = Fs2.sf - Ft2.sf; 693 }}); 694 0x2: mul_ps({{ 695 Fd1.sf = Fs1.sf * Ft2.sf; 696 Fd2.sf = Fs2.sf * Ft2.sf; 697 }}); 698 0x5: abs_ps({{ 699 Fd1.sf = fabs(Fs1.sf); 700 Fd2.sf = fabs(Fs2.sf); 701 }}); 702 0x6: mov_ps({{ 703 Fd1.sf = Fs1.sf; 704 Fd2.sf = Fs2.sf; 705 }}); 706 0x7: neg_ps({{ 707 Fd1.sf = -(Fs1.sf); 708 Fd2.sf = -(Fs2.sf); 709 }}); 710 } 711 } 712 713 0x2: decode FUNCTION_LO { 714 0x1: decode MOVCF { 715 format Float64Op { 716 0x0: movf_ps({{ 717 Fd1 = (getCondCode(FCSR, CC) == 0) ? 718 Fs1 : Fd1; 719 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 720 Fs2 : Fd2; 721 }}); 722 0x1: movt_ps({{ 723 Fd2 = (getCondCode(FCSR, CC) == 1) ? 724 Fs1 : Fd1; 725 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 726 Fs2 : Fd2; 727 }}); 728 } 729 } 730 731 format Float64Op { 732 0x2: movz_ps({{ 733 Fd1 = (getCondCode(FCSR, CC) == 0) ? 734 Fs1 : Fd1; 735 Fd2 = (getCondCode(FCSR, CC) == 0) ? 736 Fs2 : Fd2; 737 }}); 738 0x3: movn_ps({{ 739 Fd1 = (getCondCode(FCSR, CC) == 1) ? 740 Fs1 : Fd1; 741 Fd2 = (getCondCode(FCSR, CC) == 1) ? 742 Fs2 : Fd2; 743 }}); 744 } 745 746 } 747 748 0x4: decode FUNCTION_LO { 749 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 750 } 751 752 0x5: decode FUNCTION_LO { 753 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); 754 755 format Float64Op { 756 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 757 Ft1.uw; 758 }}); 759 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 760 Ft2.uw; 761 }}); 762 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 763 Ft1.uw; 764 }}); 765 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 766 Ft2.uw; 767 }}); 768 } 769 } 770 771 0x6: decode FUNCTION_LO { 772 format FloatPSCompareOp { 773 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 774 UnorderedFalse); 775 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 776 UnorderedTrue); 777 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 778 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 779 UnorderedFalse); 780 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 781 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 782 UnorderedTrue); 783 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 784 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 785 UnorderedFalse); 786 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }}, 787 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 788 UnorderedTrue); 789 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }}, 790 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 791 UnorderedFalse); 792 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 793 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 794 UnorderedTrue); 795 } 796 } 797 798 0x7: decode FUNCTION_LO { 799 format FloatPSCompareOp { 800 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 801 UnorderedFalse, QnanException); 802 0x1: c_ngle_ps({{ cond1 = 0; }}, 803 {{ cond2 = 0; }}, 804 UnorderedTrue, QnanException); 805 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 806 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 807 UnorderedFalse, QnanException); 808 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 809 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 810 UnorderedTrue, QnanException); 811 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 812 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 813 UnorderedFalse, QnanException); 814 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 815 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 816 UnorderedTrue, QnanException); 817 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 818 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 819 UnorderedFalse, QnanException); 820 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 821 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 822 UnorderedTrue, QnanException); 823 } 824 } 825 } 826 } 827 } 828 } 829 830 //Table A-19 MIPS32 COP2 Encoding of rs Field 831 0x2: decode RS_MSB { 832 format FailUnimpl { 833 0x0: decode RS_HI { 834 0x0: decode RS_LO { 835 0x0: mfc2(); 836 0x2: cfc2(); 837 0x3: mfhc2(); 838 0x4: mtc2(); 839 0x6: ctc2(); 840 0x7: mftc2(); 841 } 842 843 0x1: decode ND { 844 0x0: decode TF { 845 0x0: bc2f(); 846 0x1: bc2t(); 847 } 848 849 0x1: decode TF { 850 0x0: bc2fl(); 851 0x1: bc2tl(); 852 } 853 } 854 } 855 } 856 } 857 858 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 859 //Note: "COP1X instructions are legal only if 64-bit floating point 860 //operations are enabled." 861 0x3: decode FUNCTION_HI { 862 0x0: decode FUNCTION_LO { 863 format LoadIndexedMemory { 864 0x0: lwxc1({{ Fd.uw = Mem.uw;}}); 865 0x1: ldxc1({{ Fd.ud = Mem.ud;}}); 866 0x5: luxc1({{ Fd.ud = Mem.ud;}}, 867 {{ EA = (Rs + Rt) & ~7; }}); 868 } 869 } 870 871 0x1: decode FUNCTION_LO { 872 format StoreIndexedMemory { 873 0x0: swxc1({{ Mem.uw = Fs.uw;}}); 874 0x1: sdxc1({{ Mem.ud = Fs.ud;}}); 875 0x5: suxc1({{ Mem.ud = Fs.ud;}}, 876 {{ EA = (Rs + Rt) & ~7; }}); 877 } 878 879 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 880 } 881 882 0x3: decode FUNCTION_LO { 883 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) { 884 Fd.ud = Fs.ud; 885 } else if (Rs<2:0> == 4) { 886 #if BYTE_ORDER == BIG_ENDIAN 887 Fd.ud = Fs.ud<31:0> << 32 | 888 Ft.ud<63:32>; 889 #elif BYTE_ORDER == LITTLE_ENDIAN 890 Fd.ud = Ft.ud<31:0> << 32 | 891 Fs.ud<63:32>; 892 #endif 893 } else { 894 Fd.ud = Fd.ud; 895 } 896 }}); 897 } 898 899 format FloatAccOp { 900 0x4: decode FUNCTION_LO { 901 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 902 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 903 0x6: madd_ps({{ 904 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; 905 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; 906 }}); 907 } 908 909 0x5: decode FUNCTION_LO { 910 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); 911 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 912 0x6: msub_ps({{ 913 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; 914 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; 915 }}); 916 } 917 918 0x6: decode FUNCTION_LO { 919 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 920 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 921 0x6: nmadd_ps({{ 922 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df); 923 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df); 924 }}); 925 } 926 927 0x7: decode FUNCTION_LO { 928 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 929 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 930 0x6: nmsub_ps({{ 931 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 932 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 933 }}); 934 } 935 936 } 937 } 938 939 format Branch { 940 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 941 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 942 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 943 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 944 } 945 } 946 947 0x3: decode OPCODE_LO { 948 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 949 0x4: decode FUNCTION_HI { 950 0x0: decode FUNCTION_LO { 951 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd; 952 Rd.sw = temp1<31:0> 953 }}); 954 955 format HiLoOp { 956 0x0: madd({{ int64_t val = ((int64_t) HI << 32 | LO) + 957 (Rs.sd * Rt.sd); 958 }}); 959 0x1: maddu({{ uint64_t val = ((uint64_t) HI << 32 | LO) + 960 (Rs.ud * Rt.ud); 961 }}); 962 0x4: msub({{ int64_t val = ((int64_t) HI << 32 | LO) - 963 (Rs.sd * Rt.sd); 964 }}); 965 0x5: msubu({{ uint64_t val = ((uint64_t) HI << 32 | LO) - 966 (Rs.ud * Rt.ud); 967 }}); 968 } 969 } 970 971 0x4: decode FUNCTION_LO { 972 format BasicOp { 973 0x0: clz({{ int cnt = 32; 974 for (int idx = 31; idx >= 0; idx--) { 975 if( Rs<idx:idx> == 1) { 976 cnt = 31 - idx; 977 break; 978 } 979 } 980 Rd.uw = cnt; 981 }}); 982 0x1: clo({{ int cnt = 32; 983 for (int idx = 31; idx >= 0; idx--) { 984 if( Rs<idx:idx> == 0) { 985 cnt = 31 - idx; 986 break; 987 } 988 } 989 Rd.uw = cnt; 990 }}); 991 } 992 } 993 994 0x7: decode FUNCTION_LO { 995 0x7: FailUnimpl::sdbbp(); 996 } 997 } 998 999 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1000 //of the Architecture 1001 0x7: decode FUNCTION_HI { 1002 0x0: decode FUNCTION_LO { 1003 format BasicOp { 1004 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); 1005 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 1006 bits(Rs.uw, MSB-LSB, 0) << LSB | 1007 bits(Rt.uw, LSB-1, 0); 1008 }}); 1009 } 1010 } 1011 1012 0x1: decode FUNCTION_LO { 1013 format MipsMT { 1014 0x0: fork(); 1015 0x1: yield(); 1016 } 1017 } 1018 1019 //Table A-10 MIPS32 BSHFL Encoding of sa Field 1020 0x4: decode SA { 1021 format BasicOp { 1022 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 | 1023 Rt.uw<31:24> << 16 | 1024 Rt.uw<7:0> << 8 | 1025 Rt.uw<15:8>; 1026 }}); 1027 0x10: seb({{ Rd.sw = Rt.sb; }}); 1028 0x18: seh({{ Rd.sw = Rt.sh; }}); 1029 } 1030 } 1031 1032 0x6: decode FUNCTION_LO { 1033 0x7: FailUnimpl::rdhwr(); 1034 } 1035 } 1036 } 1037 1038 0x4: decode OPCODE_LO { 1039 format LoadMemory { 1040 0x0: lb({{ Rt.sw = Mem.sb; }}); 1041 0x1: lh({{ Rt.sw = Mem.sh; }}); 1042 0x3: lw({{ Rt.sw = Mem.sw; }}); 1043 0x4: lbu({{ Rt.uw = Mem.ub; }}); 1044 0x5: lhu({{ Rt.uw = Mem.uh; }}); 1045 } 1046 1047 format LoadUnalignedMemory { 1048 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset); 1049 Rt.uw = mem_word << mem_shift | 1050 Rt.uw & mask(mem_shift); 1051 }}); 1052 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset; 1053 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) | 1054 mem_word >> mem_shift; 1055 }}); 1056 } 1057 } 1058 1059 0x5: decode OPCODE_LO { 1060 format StoreMemory { 1061 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 1062 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 1063 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 1064 } 1065 1066 format StoreUnalignedMemory { 1067 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset); 1068 uint32_t mem_shift = 32 - reg_shift; 1069 mem_word = mem_word & (mask(reg_shift) << mem_shift) | 1070 Rt.uw >> reg_shift; 1071 }}); 1072 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset; 1073 mem_word = Rt.uw << reg_shift | 1074 mem_word & (mask(reg_shift)); 1075 }}); 1076 } 1077 1078 0x7: FailUnimpl::cache(); 1079 } 1080 1081 0x6: decode OPCODE_LO { 1082 format LoadMemory { 1083 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED); 1084 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 1085 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 1086 } 1087 1088 0x3: Prefetch::pref(); 1089 } 1090 1091 1092 0x7: decode OPCODE_LO { 1093 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, 1094 {{ uint64_t tmp = write_result; 1095 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; 1096 if (tmp == 1) { 1097 xc->setStCondFailures(0); 1098 } 1099 }}, mem_flags=LOCKED, inst_flags = IsStoreConditional); 1100 1101 format StoreMemory { 1102 0x1: swc1({{ Mem.uw = Ft.uw; }}); 1103 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 1104 } 1105 } 1106} 1107 1108 1109