decoder.isa revision 13899:3a981d8482fd
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30// Brett Miller 31// Jaidev Patwardhan 32 33//////////////////////////////////////////////////////////////////// 34// 35// The actual MIPS32 ISA decoder 36// ----------------------------- 37// The following instructions are specified in the MIPS32 ISA 38// Specification. Decoding closely follows the style specified 39// in the MIPS32 ISA specification document starting with Table 40// A-2 (document available @ http://www.mips.com) 41// 42decode OPCODE_HI default Unknown::unknown() { 43 //Table A-2 44 0x0: decode OPCODE_LO { 45 0x0: decode FUNCTION_HI { 46 0x0: decode FUNCTION_LO { 47 0x1: decode MOVCI { 48 format BasicOp { 49 0: movf({{ 50 Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; 51 }}); 52 1: movt({{ 53 Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; 54 }}); 55 } 56 } 57 58 format BasicOp { 59 //Table A-3 Note: "Specific encodings of the rd, rs, and 60 //rt fields are used to distinguish SLL, SSNOP, and EHB 61 //functions 62 0x0: decode RS { 63 0x0: decode RT_RD { 64 0x0: decode SA default Nop::nop() { 65 0x1: ssnop({{;}}); 66 0x3: ehb({{;}}); 67 } 68 default: sll({{ Rd = Rt << SA; }}); 69 } 70 } 71 72 0x2: decode RS_SRL { 73 0x0:decode SRL { 74 0: srl({{ Rd = Rt >> SA; }}); 75 76 //Hardcoded assuming 32-bit ISA, 77 //probably need parameter here 78 1: rotr({{ 79 Rd = (Rt << (32 - SA)) | (Rt >> SA); 80 }}); 81 } 82 } 83 84 0x3: decode RS { 85 0x0: sra({{ 86 uint32_t temp = Rt >> SA; 87 if ( (Rt & 0x80000000) > 0 ) { 88 uint32_t mask = 0x80000000; 89 for(int i=0; i < SA; i++) { 90 temp |= mask; 91 mask = mask >> 1; 92 } 93 } 94 Rd = temp; 95 }}); 96 } 97 98 0x4: sllv({{ Rd = Rt << Rs<4:0>; }}); 99 100 0x6: decode SRLV { 101 0: srlv({{ Rd = Rt >> Rs<4:0>; }}); 102 103 //Hardcoded assuming 32-bit ISA, 104 //probably need parameter here 105 1: rotrv({{ 106 Rd = (Rt << (32 - Rs<4:0>)) | (Rt >> Rs<4:0>); 107 }}); 108 } 109 110 0x7: srav({{ 111 int shift_amt = Rs<4:0>; 112 113 uint32_t temp = Rt >> shift_amt; 114 115 if ((Rt & 0x80000000) > 0) { 116 uint32_t mask = 0x80000000; 117 for (int i = 0; i < shift_amt; i++) { 118 temp |= mask; 119 mask = mask >> 1; 120 } 121 } 122 Rd = temp; 123 }}); 124 } 125 } 126 127 0x1: decode FUNCTION_LO { 128 //Table A-3 Note: "Specific encodings of the hint field are 129 //used to distinguish JR from JR.HB and JALR from JALR.HB" 130 format Jump { 131 0x0: decode HINT { 132 0x1: jr_hb({{ 133 Config1Reg config1 = Config1; 134 if (config1.ca == 0) { 135 NNPC = Rs; 136 } else { 137 panic("MIPS16e not supported\n"); 138 } 139 }}, IsReturn, ClearHazards); 140 default: jr({{ 141 Config1Reg config1 = Config1; 142 if (config1.ca == 0) { 143 NNPC = Rs; 144 } else { 145 panic("MIPS16e not supported\n"); 146 } 147 }}, IsReturn); 148 } 149 150 0x1: decode HINT { 151 0x1: jalr_hb({{ 152 Rd = NNPC; 153 NNPC = Rs; 154 }}, IsCall, ClearHazards); 155 default: jalr({{ 156 Rd = NNPC; 157 NNPC = Rs; 158 }}, IsCall); 159 } 160 } 161 162 format BasicOp { 163 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 164 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 165 0x4: decode FullSystemInt { 166 0: syscall_se({{ xc->syscall(R2, &fault); }}, 167 IsSerializeAfter, IsNonSpeculative); 168 default: syscall({{ fault = std::make_shared<SystemCallFault>(); }}); 169 } 170 0x7: sync({{ ; }}, IsMemBarrier); 171 0x5: break({{fault = std::make_shared<BreakpointFault>();}}); 172 } 173 174 } 175 176 0x2: decode FUNCTION_LO { 177 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, 178 IntMultOp, IsIprAccess); 179 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); 180 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, 181 IntMultOp, IsIprAccess); 182 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 183 } 184 185 0x3: decode FUNCTION_LO { 186 format HiLoRdSelValOp { 187 0x0: mult({{ val = Rs_sd * Rt_sd; }}, IntMultOp); 188 0x1: multu({{ val = Rs_ud * Rt_ud; }}, IntMultOp); 189 } 190 191 format HiLoOp { 192 0x2: div({{ 193 if (Rt_sd != 0) { 194 HI0 = Rs_sd % Rt_sd; 195 LO0 = Rs_sd / Rt_sd; 196 } 197 }}, IntDivOp); 198 199 0x3: divu({{ 200 if (Rt_ud != 0) { 201 HI0 = Rs_ud % Rt_ud; 202 LO0 = Rs_ud / Rt_ud; 203 } 204 }}, IntDivOp); 205 } 206 } 207 208 0x4: decode HINT { 209 0x0: decode FUNCTION_LO { 210 format IntOp { 211 0x0: add({{ 212 uint32_t result; 213 Rd = result = Rs + Rt; 214 if (FullSystem && 215 findOverflow(32, result, Rs, Rt)) { 216 fault = std::make_shared<IntegerOverflowFault>(); 217 } 218 }}); 219 0x1: addu({{ Rd = Rs_sw + Rt_sw;}}); 220 0x2: sub({{ 221 uint32_t result; 222 Rd = result = Rs - Rt; 223 if (FullSystem && 224 findOverflow(32, result, Rs, ~Rt)) { 225 fault = std::make_shared<IntegerOverflowFault>(); 226 } 227 }}); 228 0x3: subu({{ Rd = Rs_sw - Rt_sw; }}); 229 0x4: and({{ Rd = Rs & Rt; }}); 230 0x5: or({{ Rd = Rs | Rt; }}); 231 0x6: xor({{ Rd = Rs ^ Rt; }}); 232 0x7: nor({{ Rd = ~(Rs | Rt); }}); 233 } 234 } 235 } 236 237 0x5: decode HINT { 238 0x0: decode FUNCTION_LO { 239 format IntOp{ 240 0x2: slt({{ Rd = (Rs_sw < Rt_sw) ? 1 : 0 }}); 241 0x3: sltu({{ Rd = (Rs < Rt) ? 1 : 0 }}); 242 } 243 } 244 } 245 246 0x6: decode FUNCTION_LO { 247 format Trap { 248 0x0: tge({{ cond = (Rs_sw >= Rt_sw); }}); 249 0x1: tgeu({{ cond = (Rs >= Rt); }}); 250 0x2: tlt({{ cond = (Rs_sw < Rt_sw); }}); 251 0x3: tltu({{ cond = (Rs < Rt); }}); 252 0x4: teq({{ cond = (Rs_sw == Rt_sw); }}); 253 0x6: tne({{ cond = (Rs_sw != Rt_sw); }}); 254 } 255 } 256 } 257 258 0x1: decode REGIMM_HI { 259 0x0: decode REGIMM_LO { 260 format Branch { 261 0x0: bltz({{ cond = (Rs_sw < 0); }}); 262 0x1: bgez({{ cond = (Rs_sw >= 0); }}); 263 0x2: bltzl({{ cond = (Rs_sw < 0); }}, Likely); 264 0x3: bgezl({{ cond = (Rs_sw >= 0); }}, Likely); 265 } 266 } 267 268 0x1: decode REGIMM_LO { 269 format TrapImm { 270 0x0: tgei( {{ cond = (Rs_sw >= (int16_t)INTIMM); }}); 271 0x1: tgeiu({{ 272 cond = (Rs >= (uint32_t)(int32_t)(int16_t)INTIMM); 273 }}); 274 0x2: tlti( {{ cond = (Rs_sw < (int16_t)INTIMM); }}); 275 0x3: tltiu({{ 276 cond = (Rs < (uint32_t)(int32_t)(int16_t)INTIMM); 277 }}); 278 0x4: teqi( {{ cond = (Rs_sw == (int16_t)INTIMM); }}); 279 0x6: tnei( {{ cond = (Rs_sw != (int16_t)INTIMM); }}); 280 } 281 } 282 283 0x2: decode REGIMM_LO { 284 format Branch { 285 0x0: bltzal({{ cond = (Rs_sw < 0); }}, Link); 286 0x1: decode RS { 287 0x0: bal ({{ cond = 1; }}, IsCall, Link); 288 default: bgezal({{ cond = (Rs_sw >= 0); }}, Link); 289 } 290 0x2: bltzall({{ cond = (Rs_sw < 0); }}, Link, Likely); 291 0x3: bgezall({{ cond = (Rs_sw >= 0); }}, Link, Likely); 292 } 293 } 294 295 0x3: decode REGIMM_LO { 296 // from Table 5-4 MIPS32 REGIMM Encoding of rt Field 297 // (DSP ASE MANUAL) 298 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 299 format WarnUnimpl { 300 0x7: synci(); 301 } 302 } 303 } 304 305 format Jump { 306 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}); 307 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, 308 IsCall, Link); 309 } 310 311 format Branch { 312 0x4: decode RS_RT { 313 0x0: b({{ cond = 1; }}); 314 default: beq({{ cond = (Rs_sw == Rt_sw); }}); 315 } 316 0x5: bne({{ cond = (Rs_sw != Rt_sw); }}); 317 0x6: blez({{ cond = (Rs_sw <= 0); }}); 318 0x7: bgtz({{ cond = (Rs_sw > 0); }}); 319 } 320 } 321 322 0x1: decode OPCODE_LO { 323 format IntImmOp { 324 0x0: addi({{ 325 uint32_t result; 326 Rt = result = Rs + imm; 327 if (FullSystem && 328 findOverflow(32, result, Rs, imm)) { 329 fault = std::make_shared<IntegerOverflowFault>(); 330 } 331 }}); 332 0x1: addiu({{ Rt = Rs_sw + imm; }}); 333 0x2: slti({{ Rt = (Rs_sw < imm) ? 1 : 0 }}); 334 0x3: sltiu({{ Rt = (Rs < (uint32_t)sextImm) ? 1 : 0;}}); 335 0x4: andi({{ Rt = Rs_sw & zextImm; }}); 336 0x5: ori({{ Rt = Rs_sw | zextImm; }}); 337 0x6: xori({{ Rt = Rs_sw ^ zextImm; }}); 338 339 0x7: decode RS { 340 0x0: lui({{ Rt = imm << 16; }}); 341 } 342 } 343 } 344 345 0x2: decode OPCODE_LO { 346 //Table A-11 MIPS32 COP0 Encoding of rs Field 347 0x0: decode RS_MSB { 348 0x0: decode RS { 349 format CP0Control { 350 0x0: mfc0({{ 351 Config3Reg config3 = Config3; 352 PageGrainReg pageGrain = PageGrain; 353 Rt = CP0_RD_SEL; 354 /* Hack for PageMask */ 355 if (RD == 5) { 356 // PageMask 357 if (config3.sp == 0 || pageGrain.esp == 0) 358 Rt &= 0xFFFFE7FF; 359 } 360 }}); 361 0x4: mtc0({{ 362 CP0_RD_SEL = Rt; 363 CauseReg cause = Cause; 364 IntCtlReg intCtl = IntCtl; 365 if (RD == 11) { 366 // Compare 367 if (cause.ti == 1) { 368 cause.ti = 0; 369 int offset = 10; // corresponding to cause.ip0 370 offset += intCtl.ipti - 2; 371 replaceBits(cause, offset, offset, 0); 372 } 373 } 374 Cause = cause; 375 }}); 376 } 377 format CP0Unimpl { 378 0x1: dmfc0(); 379 0x5: dmtc0(); 380 default: unknown(); 381 } 382 format MT_MFTR { 383 // Decode MIPS MT MFTR instruction into sub-instructions 384 0x8: decode MT_U { 385 0x0: mftc0({{ 386 data = readRegOtherThread(xc, RegId(MiscRegClass, 387 (RT << 3 | SEL))); 388 }}); 389 0x1: decode SEL { 390 0x0: mftgpr({{ 391 data = readRegOtherThread(xc, 392 RegId(IntRegClass, RT)); 393 }}); 394 0x1: decode RT { 395 0x0: mftlo_dsp0({{ 396 data = readRegOtherThread(xc, 397 RegId(IntRegClass, INTREG_DSP_LO0)); 398 }}); 399 0x1: mfthi_dsp0({{ 400 data = readRegOtherThread(xc, 401 RegId(IntRegClass, INTREG_DSP_HI0)); 402 }}); 403 0x2: mftacx_dsp0({{ 404 data = readRegOtherThread(xc, 405 RegId(IntRegClass, INTREG_DSP_ACX0)); 406 }}); 407 0x4: mftlo_dsp1({{ 408 data = readRegOtherThread(xc, 409 RegId(IntRegClass, INTREG_DSP_LO1)); 410 }}); 411 0x5: mfthi_dsp1({{ 412 data = readRegOtherThread(xc, 413 RegId(IntRegClass, INTREG_DSP_HI1)); 414 }}); 415 0x6: mftacx_dsp1({{ 416 data = readRegOtherThread(xc, 417 RegId(IntRegClass, INTREG_DSP_ACX1)); 418 }}); 419 0x8: mftlo_dsp2({{ 420 data = readRegOtherThread(xc, 421 RegId(IntRegClass, INTREG_DSP_LO2)); 422 }}); 423 0x9: mfthi_dsp2({{ 424 data = readRegOtherThread(xc, 425 RegId(IntRegClass, INTREG_DSP_HI2)); 426 }}); 427 0x10: mftacx_dsp2({{ 428 data = readRegOtherThread(xc, 429 RegId(IntRegClass, INTREG_DSP_ACX2)); 430 }}); 431 0x12: mftlo_dsp3({{ 432 data = readRegOtherThread(xc, 433 RegId(IntRegClass, INTREG_DSP_LO3)); 434 }}); 435 0x13: mfthi_dsp3({{ 436 data = readRegOtherThread(xc, 437 RegId(IntRegClass, INTREG_DSP_HI3)); 438 }}); 439 0x14: mftacx_dsp3({{ 440 data = readRegOtherThread(xc, 441 RegId(IntRegClass, INTREG_DSP_ACX3)); 442 }}); 443 0x16: mftdsp({{ 444 data = readRegOtherThread(xc, 445 RegId(IntRegClass, INTREG_DSP_CONTROL)); 446 }}); 447 default: CP0Unimpl::unknown(); 448 } 449 0x2: decode MT_H { 450 0x0: mftc1({{ 451 data = readRegOtherThread(xc, 452 RegId(FloatRegClass, RT)); 453 }}); 454 0x1: mfthc1({{ 455 data = readRegOtherThread(xc, 456 RegId(FloatRegClass, RT)); 457 }}); 458 } 459 0x3: cftc1({{ 460 uint32_t fcsr_val = readRegOtherThread(xc, 461 RegId(FloatRegClass, FLOATREG_FCSR)); 462 switch (RT) { 463 case 0: 464 data = readRegOtherThread(xc, 465 RegId(MiscRegClass, FLOATREG_FIR)); 466 break; 467 case 25: 468 data = (fcsr_val & 0xFE000000 >> 24) | 469 (fcsr_val & 0x00800000 >> 23); 470 break; 471 case 26: 472 data = fcsr_val & 0x0003F07C; 473 break; 474 case 28: 475 data = (fcsr_val & 0x00000F80) | 476 (fcsr_val & 0x01000000 >> 21) | 477 (fcsr_val & 0x00000003); 478 break; 479 case 31: 480 data = fcsr_val; 481 break; 482 default: 483 fatal("FP Control Value (%d) Not Valid"); 484 } 485 }}); 486 default: CP0Unimpl::unknown(); 487 } 488 } 489 } 490 491 format MT_MTTR { 492 // Decode MIPS MT MTTR instruction into sub-instructions 493 0xC: decode MT_U { 494 0x0: mttc0({{ setRegOtherThread(xc, 495 RegId(MiscRegClass, (RD << 3 | SEL)), Rt); 496 }}); 497 0x1: decode SEL { 498 0x0: mttgpr({{ setRegOtherThread(xc, 499 RegId(IntRegClass, RD), Rt); 500 }}); 501 0x1: decode RT { 502 0x0: mttlo_dsp0({{ setRegOtherThread(xc, 503 RegId(IntRegClass, INTREG_DSP_LO0), Rt); 504 }}); 505 0x1: mtthi_dsp0({{ setRegOtherThread(xc, 506 RegId(IntRegClass, INTREG_DSP_HI0), Rt); 507 }}); 508 0x2: mttacx_dsp0({{ setRegOtherThread(xc, 509 RegId(IntRegClass, INTREG_DSP_ACX0), Rt); 510 }}); 511 0x4: mttlo_dsp1({{ setRegOtherThread(xc, 512 RegId(IntRegClass, INTREG_DSP_LO1), Rt); 513 }}); 514 0x5: mtthi_dsp1({{ setRegOtherThread(xc, 515 RegId(IntRegClass, INTREG_DSP_HI1), Rt); 516 }}); 517 0x6: mttacx_dsp1({{ setRegOtherThread(xc, 518 RegId(IntRegClass, INTREG_DSP_ACX1), Rt); 519 }}); 520 0x8: mttlo_dsp2({{ setRegOtherThread(xc, 521 RegId(IntRegClass, INTREG_DSP_LO2), Rt); 522 }}); 523 0x9: mtthi_dsp2({{ setRegOtherThread(xc, 524 RegId(IntRegClass, INTREG_DSP_HI2), Rt); 525 }}); 526 0x10: mttacx_dsp2({{ setRegOtherThread(xc, 527 RegId(IntRegClass, INTREG_DSP_ACX2), Rt); 528 }}); 529 0x12: mttlo_dsp3({{ setRegOtherThread(xc, 530 RegId(IntRegClass, INTREG_DSP_LO3), Rt); 531 }}); 532 0x13: mtthi_dsp3({{ setRegOtherThread(xc, 533 RegId(IntRegClass, INTREG_DSP_HI3), Rt); 534 }}); 535 0x14: mttacx_dsp3({{ setRegOtherThread(xc, 536 RegId(IntRegClass, INTREG_DSP_ACX3), Rt); 537 }}); 538 0x16: mttdsp({{ setRegOtherThread(xc, 539 RegId(IntRegClass, INTREG_DSP_CONTROL), Rt); 540 }}); 541 default: CP0Unimpl::unknown(); 542 543 } 544 0x2: mttc1({{ 545 uint64_t data = readRegOtherThread(xc, 546 RegId(FloatRegClass, RD)); 547 data = insertBits(data, MT_H ? 63 : 31, 548 MT_H ? 32 : 0, Rt); 549 setRegOtherThread(xc, RegId(FloatRegClass, RD), 550 data); 551 }}); 552 0x3: cttc1({{ 553 uint32_t data; 554 switch (RD) { 555 case 25: 556 data = (Rt<7:1> << 25) | // move 31-25 557 (FCSR & 0x01000000) | // bit 24 558 (FCSR & 0x004FFFFF); // bit 22-0 559 break; 560 case 26: 561 data = (FCSR & 0xFFFC0000) | // move 31-18 562 Rt<17:12> << 12 | // bit 17-12 563 // bit 11-7 564 (FCSR & 0x00000F80) << 7 | 565 Rt<6:2> << 2 | // bit 6-2 566 (FCSR & 0x00000002); // bit 1...0 567 break; 568 case 28: 569 data = (FCSR & 0xFE000000) | // move 31-25 570 Rt<2:2> << 24 | // bit 24 571 // bit 23-12 572 (FCSR & 0x00FFF000) << 23 | 573 Rt<11:7> << 7 | // bit 24 574 (FCSR & 0x000007E) | 575 Rt<1:0>; // bit 22-0 576 break; 577 case 31: 578 data = Rt; 579 break; 580 default: 581 panic("FP Control Value (%d) " 582 "Not Available. Ignoring " 583 "Access to Floating Control " 584 "S""tatus Register", FS); 585 } 586 setRegOtherThread(xc, 587 RegId(FloatRegClass, FLOATREG_FCSR), data); 588 }}); 589 default: CP0Unimpl::unknown(); 590 } 591 } 592 } 593 0xB: decode RD { 594 format MT_Control { 595 0x0: decode POS { 596 0x0: decode SEL { 597 0x1: decode SC { 598 0x0: dvpe({{ 599 MVPControlReg mvpControl = MVPControl; 600 VPEConf0Reg vpeConf0 = VPEConf0; 601 Rt = MVPControl; 602 if (vpeConf0.mvp == 1) 603 mvpControl.evp = 0; 604 MVPControl = mvpControl; 605 }}); 606 0x1: evpe({{ 607 MVPControlReg mvpControl = MVPControl; 608 VPEConf0Reg vpeConf0 = VPEConf0; 609 Rt = MVPControl; 610 if (vpeConf0.mvp == 1) 611 mvpControl.evp = 1; 612 MVPControl = mvpControl; 613 }}); 614 default:CP0Unimpl::unknown(); 615 } 616 default:CP0Unimpl::unknown(); 617 } 618 default:CP0Unimpl::unknown(); 619 } 620 0x1: decode POS { 621 0xF: decode SEL { 622 0x1: decode SC { 623 0x0: dmt({{ 624 VPEControlReg vpeControl = VPEControl; 625 Rt = vpeControl; 626 vpeControl.te = 0; 627 VPEControl = vpeControl; 628 }}); 629 0x1: emt({{ 630 VPEControlReg vpeControl = VPEControl; 631 Rt = vpeControl; 632 vpeControl.te = 1; 633 VPEControl = vpeControl; 634 }}); 635 default:CP0Unimpl::unknown(); 636 } 637 default:CP0Unimpl::unknown(); 638 } 639 default:CP0Unimpl::unknown(); 640 } 641 } 642 0xC: decode POS { 643 0x0: decode SC { 644 0x0: CP0Control::di({{ 645 StatusReg status = Status; 646 ConfigReg config = Config; 647 // Rev 2.0 or beyond? 648 if (config.ar >= 1) { 649 Rt = status; 650 status.ie = 0; 651 } else { 652 // Enable this else branch once we 653 // actually set values for Config on init 654 fault = std::make_shared<ReservedInstructionFault>(); 655 } 656 Status = status; 657 }}); 658 0x1: CP0Control::ei({{ 659 StatusReg status = Status; 660 ConfigReg config = Config; 661 if (config.ar >= 1) { 662 Rt = status; 663 status.ie = 1; 664 } else { 665 fault = std::make_shared<ReservedInstructionFault>(); 666 } 667 }}); 668 default:CP0Unimpl::unknown(); 669 } 670 } 671 default: CP0Unimpl::unknown(); 672 } 673 format CP0Control { 674 0xA: rdpgpr({{ 675 ConfigReg config = Config; 676 if (config.ar >= 1) { 677 // Rev 2 of the architecture 678 panic("Shadow Sets Not Fully Implemented.\n"); 679 } else { 680 fault = std::make_shared<ReservedInstructionFault>(); 681 } 682 }}); 683 0xE: wrpgpr({{ 684 ConfigReg config = Config; 685 if (config.ar >= 1) { 686 // Rev 2 of the architecture 687 panic("Shadow Sets Not Fully Implemented.\n"); 688 } else { 689 fault = std::make_shared<ReservedInstructionFault>(); 690 } 691 }}); 692 } 693 } 694 695 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 696 0x1: decode FUNCTION { 697 format CP0Control { 698 0x18: eret({{ 699 StatusReg status = Status; 700 ConfigReg config = Config; 701 SRSCtlReg srsCtl = SRSCtl; 702 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 703 if (status.erl == 1) { 704 status.erl = 0; 705 NPC = ErrorEPC; 706 // Need to adjust NNPC, otherwise things break 707 NNPC = ErrorEPC + sizeof(MachInst); 708 } else { 709 NPC = EPC; 710 // Need to adjust NNPC, otherwise things break 711 NNPC = EPC + sizeof(MachInst); 712 status.exl = 0; 713 if (config.ar >=1 && 714 srsCtl.hss > 0 && 715 status.bev == 0) { 716 srsCtl.css = srsCtl.pss; 717 //xc->setShadowSet(srsCtl.pss); 718 } 719 } 720 LLFlag = 0; 721 Status = status; 722 SRSCtl = srsCtl; 723 }}, IsReturn, IsSerializing, IsERET); 724 725 0x1F: deret({{ 726 DebugReg debug = Debug; 727 if (debug.dm == 1) { 728 debug.dm = 1; 729 debug.iexi = 0; 730 NPC = DEPC; 731 } else { 732 NPC = NPC; 733 // Undefined; 734 } 735 Debug = debug; 736 }}, IsReturn, IsSerializing, IsERET); 737 } 738 format CP0TLB { 739 0x01: tlbr({{ 740 MipsISA::PTE *PTEntry = 741 dynamic_cast<MipsISA::TLB *>( 742 xc->tcBase()->getITBPtr())-> 743 getEntry(Index & 0x7FFFFFFF); 744 if (PTEntry == NULL) { 745 fatal("Invalid PTE Entry received on " 746 "a TLBR instruction\n"); 747 } 748 /* Setup PageMask */ 749 // If 1KB pages are not enabled, a read of PageMask 750 // must return 0b00 in bits 12, 11 751 PageMask = (PTEntry->Mask << 11); 752 /* Setup EntryHi */ 753 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 754 /* Setup Entry Lo0 */ 755 EntryLo0 = ((PTEntry->PFN0 << 6) | 756 (PTEntry->C0 << 3) | 757 (PTEntry->D0 << 2) | 758 (PTEntry->V0 << 1) | 759 PTEntry->G); 760 /* Setup Entry Lo1 */ 761 EntryLo1 = ((PTEntry->PFN1 << 6) | 762 (PTEntry->C1 << 3) | 763 (PTEntry->D1 << 2) | 764 (PTEntry->V1 << 1) | 765 PTEntry->G); 766 }}); // Need to hook up to TLB 767 768 0x02: tlbwi({{ 769 //Create PTE 770 MipsISA::PTE newEntry; 771 //Write PTE 772 newEntry.Mask = (Addr)(PageMask >> 11); 773 newEntry.VPN = (Addr)(EntryHi >> 11); 774 /* PageGrain _ ESP Config3 _ SP */ 775 if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { 776 // If 1KB pages are *NOT* enabled, lowest bits of 777 // the mask are 0b11 for TLB writes 778 newEntry.Mask |= 0x3; 779 // Reset bits 0 and 1 if 1KB pages are not enabled 780 newEntry.VPN &= 0xFFFFFFFC; 781 } 782 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 783 784 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 785 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 786 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 787 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 788 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 789 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 790 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 791 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 792 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 793 /* Now, compute the AddrShiftAmount and OffsetMask - 794 TLB optimizations */ 795 /* Addr Shift Amount for 1KB or larger pages */ 796 if ((newEntry.Mask & 0xFFFF) == 3) { 797 newEntry.AddrShiftAmount = 12; 798 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 799 newEntry.AddrShiftAmount = 10; 800 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 801 newEntry.AddrShiftAmount = 14; 802 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 803 newEntry.AddrShiftAmount = 16; 804 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 805 newEntry.AddrShiftAmount = 18; 806 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 807 newEntry.AddrShiftAmount = 20; 808 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 809 newEntry.AddrShiftAmount = 22; 810 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 811 newEntry.AddrShiftAmount = 24; 812 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 813 newEntry.AddrShiftAmount = 26; 814 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 815 newEntry.AddrShiftAmount = 28; 816 } else { 817 fatal("Invalid Mask Pattern Detected!\n"); 818 } 819 newEntry.OffsetMask = 820 (1 << newEntry.AddrShiftAmount) - 1; 821 822 auto ptr = dynamic_cast<MipsISA::TLB *>( 823 xc->tcBase()->getITBPtr()); 824 Config3Reg config3 = Config3; 825 PageGrainReg pageGrain = PageGrain; 826 int SP = 0; 827 if (bits(config3, config3.sp) == 1 && 828 bits(pageGrain, pageGrain.esp) == 1) { 829 SP = 1; 830 } 831 ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 832 }}); 833 0x06: tlbwr({{ 834 //Create PTE 835 MipsISA::PTE newEntry; 836 //Write PTE 837 newEntry.Mask = (Addr)(PageMask >> 11); 838 newEntry.VPN = (Addr)(EntryHi >> 11); 839 /* PageGrain _ ESP Config3 _ SP */ 840 if (bits(PageGrain, 28) == 0 || 841 bits(Config3, 4) == 0) { 842 // If 1KB pages are *NOT* enabled, lowest bits of 843 // the mask are 0b11 for TLB writes 844 newEntry.Mask |= 0x3; 845 // Reset bits 0 and 1 if 1KB pages are not enabled 846 newEntry.VPN &= 0xFFFFFFFC; 847 } 848 newEntry.asid = (uint8_t)(EntryHi & 0xFF); 849 850 newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 851 newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 852 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 853 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 854 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 855 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 856 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 857 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 858 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 859 /* Now, compute the AddrShiftAmount and OffsetMask - 860 TLB optimizations */ 861 /* Addr Shift Amount for 1KB or larger pages */ 862 if ((newEntry.Mask & 0xFFFF) == 3){ 863 newEntry.AddrShiftAmount = 12; 864 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 865 newEntry.AddrShiftAmount = 10; 866 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 867 newEntry.AddrShiftAmount = 14; 868 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 869 newEntry.AddrShiftAmount = 16; 870 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 871 newEntry.AddrShiftAmount = 18; 872 } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 873 newEntry.AddrShiftAmount = 20; 874 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 875 newEntry.AddrShiftAmount = 22; 876 } else if ((newEntry.Mask & 0xF000) == 0x3000) { 877 newEntry.AddrShiftAmount = 24; 878 } else if ((newEntry.Mask & 0xC000) == 0xC000) { 879 newEntry.AddrShiftAmount = 26; 880 } else if ((newEntry.Mask & 0x30000) == 0x30000) { 881 newEntry.AddrShiftAmount = 28; 882 } else { 883 fatal("Invalid Mask Pattern Detected!\n"); 884 } 885 newEntry.OffsetMask = 886 (1 << newEntry.AddrShiftAmount) - 1; 887 888 auto ptr = dynamic_cast<MipsISA::TLB *>( 889 xc->tcBase()->getITBPtr()); 890 Config3Reg config3 = Config3; 891 PageGrainReg pageGrain = PageGrain; 892 int SP = 0; 893 if (bits(config3, config3.sp) == 1 && 894 bits(pageGrain, pageGrain.esp) == 1) { 895 SP = 1; 896 } 897 ptr->insertAt(newEntry, Random, SP); 898 }}); 899 900 0x08: tlbp({{ 901 Config3Reg config3 = Config3; 902 PageGrainReg pageGrain = PageGrain; 903 EntryHiReg entryHi = EntryHi; 904 int tlbIndex; 905 Addr vpn; 906 if (pageGrain.esp == 1 && config3.sp ==1) { 907 vpn = EntryHi >> 11; 908 } else { 909 // Mask off lower 2 bits 910 vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 911 } 912 tlbIndex = dynamic_cast<MipsISA::TLB *>( 913 xc->tcBase()->getITBPtr())-> 914 probeEntry(vpn, entryHi.asid); 915 // Check TLB for entry matching EntryHi 916 if (tlbIndex != -1) { 917 Index = tlbIndex; 918 } else { 919 // else, set Index = 1 << 31 920 Index = (1 << 31); 921 } 922 }}); 923 } 924 format CP0Unimpl { 925 0x20: wait(); 926 } 927 default: CP0Unimpl::unknown(); 928 } 929 } 930 931 //Table A-13 MIPS32 COP1 Encoding of rs Field 932 0x1: decode RS_MSB { 933 0x0: decode RS_HI { 934 0x0: decode RS_LO { 935 format CP1Control { 936 0x0: mfc1 ({{ Rt = Fs_uw; }}); 937 938 0x2: cfc1({{ 939 switch (FS) { 940 case 0: 941 Rt = FIR; 942 break; 943 case 25: 944 Rt = (FCSR & 0xFE000000) >> 24 | 945 (FCSR & 0x00800000) >> 23; 946 break; 947 case 26: 948 Rt = (FCSR & 0x0003F07C); 949 break; 950 case 28: 951 Rt = (FCSR & 0x00000F80) | 952 (FCSR & 0x01000000) >> 21 | 953 (FCSR & 0x00000003); 954 break; 955 case 31: 956 Rt = FCSR; 957 break; 958 default: 959 warn("FP Control Value (%d) Not Valid"); 960 } 961 }}); 962 963 0x3: mfhc1({{ Rt = Fs_ud<63:32>; }}); 964 965 0x4: mtc1({{ Fs_uw = Rt; }}); 966 967 0x6: ctc1({{ 968 switch (FS) { 969 case 25: 970 FCSR = (Rt<7:1> << 25) | // move 31-25 971 (FCSR & 0x01000000) | // bit 24 972 (FCSR & 0x004FFFFF); // bit 22-0 973 break; 974 case 26: 975 FCSR = (FCSR & 0xFFFC0000) | // move 31-18 976 Rt<17:12> << 12 | // bit 17-12 977 (FCSR & 0x00000F80) << 7 | // bit 11-7 978 Rt<6:2> << 2 | // bit 6-2 979 (FCSR & 0x00000002); // bit 1-0 980 break; 981 case 28: 982 FCSR = (FCSR & 0xFE000000) | // move 31-25 983 Rt<2:2> << 24 | // bit 24 984 (FCSR & 0x00FFF000) << 23 | // bit 23-12 985 Rt<11:7> << 7 | // bit 24 986 (FCSR & 0x000007E) | 987 Rt<1:0>; // bit 22-0 988 break; 989 case 31: 990 FCSR = Rt; 991 break; 992 993 default: 994 panic("FP Control Value (%d) " 995 "Not Available. Ignoring Access " 996 "to Floating Control Status " 997 "Register", FS); 998 } 999 }}); 1000 1001 0x7: mthc1({{ 1002 uint64_t fs_hi = Rt; 1003 uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF; 1004 Fs_ud = (fs_hi << 32) | fs_lo; 1005 }}); 1006 1007 } 1008 format CP1Unimpl { 1009 0x1: dmfc1(); 1010 0x5: dmtc1(); 1011 } 1012 } 1013 1014 0x1: decode RS_LO { 1015 0x0: decode ND { 1016 format Branch { 1017 0x0: decode TF { 1018 0x0: bc1f({{ 1019 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1020 }}); 1021 0x1: bc1t({{ 1022 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1023 }}); 1024 } 1025 0x1: decode TF { 1026 0x0: bc1fl({{ 1027 cond = getCondCode(FCSR, BRANCH_CC) == 0; 1028 }}, Likely); 1029 0x1: bc1tl({{ 1030 cond = getCondCode(FCSR, BRANCH_CC) == 1; 1031 }}, Likely); 1032 } 1033 } 1034 } 1035 format CP1Unimpl { 1036 0x1: bc1any2(); 1037 0x2: bc1any4(); 1038 default: unknown(); 1039 } 1040 } 1041 } 1042 1043 0x1: decode RS_HI { 1044 0x2: decode RS_LO { 1045 //Table A-14 MIPS32 COP1 Encoding of Function Field When 1046 //rs=S (( single-precision floating point)) 1047 0x0: decode FUNCTION_HI { 1048 0x0: decode FUNCTION_LO { 1049 format FloatOp { 1050 0x0: add_s({{ Fd_sf = Fs_sf + Ft_sf; }}); 1051 0x1: sub_s({{ Fd_sf = Fs_sf - Ft_sf; }}); 1052 0x2: mul_s({{ Fd_sf = Fs_sf * Ft_sf; }}); 1053 0x3: div_s({{ Fd_sf = Fs_sf / Ft_sf; }}); 1054 0x4: sqrt_s({{ Fd_sf = sqrt(Fs_sf); }}); 1055 0x5: abs_s({{ Fd_sf = fabs(Fs_sf); }}); 1056 0x7: neg_s({{ Fd_sf = -Fs_sf; }}); 1057 } 1058 0x6: BasicOp::mov_s({{ Fd_sf = Fs_sf; }}); 1059 } 1060 0x1: decode FUNCTION_LO { 1061 format FloatConvertOp { 1062 0x0: round_l_s({{ val = Fs_sf; }}, 1063 ToLong, Round); 1064 0x1: trunc_l_s({{ val = Fs_sf; }}, 1065 ToLong, Trunc); 1066 0x2: ceil_l_s({{ val = Fs_sf;}}, 1067 ToLong, Ceil); 1068 0x3: floor_l_s({{ val = Fs_sf; }}, 1069 ToLong, Floor); 1070 0x4: round_w_s({{ val = Fs_sf; }}, 1071 ToWord, Round); 1072 0x5: trunc_w_s({{ val = Fs_sf; }}, 1073 ToWord, Trunc); 1074 0x6: ceil_w_s({{ val = Fs_sf; }}, 1075 ToWord, Ceil); 1076 0x7: floor_w_s({{ val = Fs_sf; }}, 1077 ToWord, Floor); 1078 } 1079 } 1080 1081 0x2: decode FUNCTION_LO { 1082 0x1: decode MOVCF { 1083 format BasicOp { 1084 0x0: movf_s({{ 1085 Fd = (getCondCode(FCSR,CC) == 0) ? 1086 Fs : Fd; 1087 }}); 1088 0x1: movt_s({{ 1089 Fd = (getCondCode(FCSR,CC) == 1) ? 1090 Fs : Fd; 1091 }}); 1092 } 1093 } 1094 1095 format BasicOp { 1096 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 1097 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 1098 } 1099 1100 format FloatOp { 1101 0x5: recip_s({{ Fd = 1 / Fs; }}); 1102 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 1103 } 1104 format CP1Unimpl { 1105 default: unknown(); 1106 } 1107 } 1108 0x3: CP1Unimpl::unknown(); 1109 1110 0x4: decode FUNCTION_LO { 1111 format FloatConvertOp { 1112 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble); 1113 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord); 1114 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong); 1115 } 1116 1117 0x6: FloatOp::cvt_ps_s({{ 1118 Fd_ud = (uint64_t)Fs_uw << 32 | 1119 (uint64_t)Ft_uw; 1120 }}); 1121 format CP1Unimpl { 1122 default: unknown(); 1123 } 1124 } 1125 0x5: CP1Unimpl::unknown(); 1126 1127 0x6: decode FUNCTION_LO { 1128 format FloatCompareOp { 1129 0x0: c_f_s({{ cond = 0; }}, 1130 SinglePrecision, UnorderedFalse); 1131 0x1: c_un_s({{ cond = 0; }}, 1132 SinglePrecision, UnorderedTrue); 1133 0x2: c_eq_s({{ cond = (Fs_sf == Ft_sf); }}, 1134 UnorderedFalse); 1135 0x3: c_ueq_s({{ cond = (Fs_sf == Ft_sf); }}, 1136 UnorderedTrue); 1137 0x4: c_olt_s({{ cond = (Fs_sf < Ft_sf); }}, 1138 UnorderedFalse); 1139 0x5: c_ult_s({{ cond = (Fs_sf < Ft_sf); }}, 1140 UnorderedTrue); 1141 0x6: c_ole_s({{ cond = (Fs_sf <= Ft_sf); }}, 1142 UnorderedFalse); 1143 0x7: c_ule_s({{ cond = (Fs_sf <= Ft_sf); }}, 1144 UnorderedTrue); 1145 } 1146 } 1147 1148 0x7: decode FUNCTION_LO { 1149 format FloatCompareOp { 1150 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 1151 UnorderedFalse, QnanException); 1152 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 1153 UnorderedTrue, QnanException); 1154 0x2: c_seq_s({{ cond = (Fs_sf == Ft_sf); }}, 1155 UnorderedFalse, QnanException); 1156 0x3: c_ngl_s({{ cond = (Fs_sf == Ft_sf); }}, 1157 UnorderedTrue, QnanException); 1158 0x4: c_lt_s({{ cond = (Fs_sf < Ft_sf); }}, 1159 UnorderedFalse, QnanException); 1160 0x5: c_nge_s({{ cond = (Fs_sf < Ft_sf); }}, 1161 UnorderedTrue, QnanException); 1162 0x6: c_le_s({{ cond = (Fs_sf <= Ft_sf); }}, 1163 UnorderedFalse, QnanException); 1164 0x7: c_ngt_s({{ cond = (Fs_sf <= Ft_sf); }}, 1165 UnorderedTrue, QnanException); 1166 } 1167 } 1168 } 1169 1170 //Table A-15 MIPS32 COP1 Encoding of Function Field When 1171 //rs=D 1172 0x1: decode FUNCTION_HI { 1173 0x0: decode FUNCTION_LO { 1174 format FloatOp { 1175 0x0: add_d({{ Fd_df = Fs_df + Ft_df; }}); 1176 0x1: sub_d({{ Fd_df = Fs_df - Ft_df; }}); 1177 0x2: mul_d({{ Fd_df = Fs_df * Ft_df; }}); 1178 0x3: div_d({{ Fd_df = Fs_df / Ft_df; }}); 1179 0x4: sqrt_d({{ Fd_df = sqrt(Fs_df); }}); 1180 0x5: abs_d({{ Fd_df = fabs(Fs_df); }}); 1181 0x7: neg_d({{ Fd_df = -1 * Fs_df; }}); 1182 } 1183 0x6: BasicOp::mov_d({{ Fd_df = Fs_df; }}); 1184 } 1185 1186 0x1: decode FUNCTION_LO { 1187 format FloatConvertOp { 1188 0x0: round_l_d({{ val = Fs_df; }}, 1189 ToLong, Round); 1190 0x1: trunc_l_d({{ val = Fs_df; }}, 1191 ToLong, Trunc); 1192 0x2: ceil_l_d({{ val = Fs_df; }}, 1193 ToLong, Ceil); 1194 0x3: floor_l_d({{ val = Fs_df; }}, 1195 ToLong, Floor); 1196 0x4: round_w_d({{ val = Fs_df; }}, 1197 ToWord, Round); 1198 0x5: trunc_w_d({{ val = Fs_df; }}, 1199 ToWord, Trunc); 1200 0x6: ceil_w_d({{ val = Fs_df; }}, 1201 ToWord, Ceil); 1202 0x7: floor_w_d({{ val = Fs_df; }}, 1203 ToWord, Floor); 1204 } 1205 } 1206 1207 0x2: decode FUNCTION_LO { 1208 0x1: decode MOVCF { 1209 format BasicOp { 1210 0x0: movf_d({{ 1211 Fd_df = (getCondCode(FCSR,CC) == 0) ? 1212 Fs_df : Fd_df; 1213 }}); 1214 0x1: movt_d({{ 1215 Fd_df = (getCondCode(FCSR,CC) == 1) ? 1216 Fs_df : Fd_df; 1217 }}); 1218 } 1219 } 1220 1221 format BasicOp { 1222 0x2: movz_d({{ 1223 Fd_df = (Rt == 0) ? Fs_df : Fd_df; 1224 }}); 1225 0x3: movn_d({{ 1226 Fd_df = (Rt != 0) ? Fs_df : Fd_df; 1227 }}); 1228 } 1229 1230 format FloatOp { 1231 0x5: recip_d({{ Fd_df = 1 / Fs_df; }}); 1232 0x6: rsqrt_d({{ Fd_df = 1 / sqrt(Fs_df); }}); 1233 } 1234 format CP1Unimpl { 1235 default: unknown(); 1236 } 1237 1238 } 1239 0x4: decode FUNCTION_LO { 1240 format FloatConvertOp { 1241 0x0: cvt_s_d({{ val = Fs_df; }}, ToSingle); 1242 0x4: cvt_w_d({{ val = Fs_df; }}, ToWord); 1243 0x5: cvt_l_d({{ val = Fs_df; }}, ToLong); 1244 } 1245 default: CP1Unimpl::unknown(); 1246 } 1247 1248 0x6: decode FUNCTION_LO { 1249 format FloatCompareOp { 1250 0x0: c_f_d({{ cond = 0; }}, 1251 DoublePrecision, UnorderedFalse); 1252 0x1: c_un_d({{ cond = 0; }}, 1253 DoublePrecision, UnorderedTrue); 1254 0x2: c_eq_d({{ cond = (Fs_df == Ft_df); }}, 1255 UnorderedFalse); 1256 0x3: c_ueq_d({{ cond = (Fs_df == Ft_df); }}, 1257 UnorderedTrue); 1258 0x4: c_olt_d({{ cond = (Fs_df < Ft_df); }}, 1259 UnorderedFalse); 1260 0x5: c_ult_d({{ cond = (Fs_df < Ft_df); }}, 1261 UnorderedTrue); 1262 0x6: c_ole_d({{ cond = (Fs_df <= Ft_df); }}, 1263 UnorderedFalse); 1264 0x7: c_ule_d({{ cond = (Fs_df <= Ft_df); }}, 1265 UnorderedTrue); 1266 } 1267 } 1268 1269 0x7: decode FUNCTION_LO { 1270 format FloatCompareOp { 1271 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 1272 UnorderedFalse, QnanException); 1273 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 1274 UnorderedTrue, QnanException); 1275 0x2: c_seq_d({{ cond = (Fs_df == Ft_df); }}, 1276 UnorderedFalse, QnanException); 1277 0x3: c_ngl_d({{ cond = (Fs_df == Ft_df); }}, 1278 UnorderedTrue, QnanException); 1279 0x4: c_lt_d({{ cond = (Fs_df < Ft_df); }}, 1280 UnorderedFalse, QnanException); 1281 0x5: c_nge_d({{ cond = (Fs_df < Ft_df); }}, 1282 UnorderedTrue, QnanException); 1283 0x6: c_le_d({{ cond = (Fs_df <= Ft_df); }}, 1284 UnorderedFalse, QnanException); 1285 0x7: c_ngt_d({{ cond = (Fs_df <= Ft_df); }}, 1286 UnorderedTrue, QnanException); 1287 } 1288 } 1289 default: CP1Unimpl::unknown(); 1290 } 1291 0x2: CP1Unimpl::unknown(); 1292 0x3: CP1Unimpl::unknown(); 1293 0x7: CP1Unimpl::unknown(); 1294 1295 //Table A-16 MIPS32 COP1 Encoding of Function 1296 //Field When rs=W 1297 0x4: decode FUNCTION { 1298 format FloatConvertOp { 1299 0x20: cvt_s_w({{ val = Fs_sw; }}, ToSingle); 1300 0x21: cvt_d_w({{ val = Fs_sw; }}, ToDouble); 1301 0x26: CP1Unimpl::cvt_ps_w(); 1302 } 1303 default: CP1Unimpl::unknown(); 1304 } 1305 1306 //Table A-16 MIPS32 COP1 Encoding of Function Field 1307 //When rs=L1 1308 //Note: "1. Format type L is legal only if 64-bit 1309 //floating point operations are enabled." 1310 0x5: decode FUNCTION { 1311 format FloatConvertOp { 1312 0x20: cvt_s_l({{ val = Fs_sd; }}, ToSingle); 1313 0x21: cvt_d_l({{ val = Fs_sd; }}, ToDouble); 1314 0x26: CP1Unimpl::cvt_ps_l(); 1315 } 1316 default: CP1Unimpl::unknown(); 1317 } 1318 1319 //Table A-17 MIPS64 COP1 Encoding of Function Field 1320 //When rs=PS1 1321 //Note: "1. Format type PS is legal only if 64-bit 1322 //floating point operations are enabled. " 1323 0x6: decode FUNCTION_HI { 1324 0x0: decode FUNCTION_LO { 1325 format Float64Op { 1326 0x0: add_ps({{ 1327 Fd1_sf = Fs1_sf + Ft2_sf; 1328 Fd2_sf = Fs2_sf + Ft2_sf; 1329 }}); 1330 0x1: sub_ps({{ 1331 Fd1_sf = Fs1_sf - Ft2_sf; 1332 Fd2_sf = Fs2_sf - Ft2_sf; 1333 }}); 1334 0x2: mul_ps({{ 1335 Fd1_sf = Fs1_sf * Ft2_sf; 1336 Fd2_sf = Fs2_sf * Ft2_sf; 1337 }}); 1338 0x5: abs_ps({{ 1339 Fd1_sf = fabs(Fs1_sf); 1340 Fd2_sf = fabs(Fs2_sf); 1341 }}); 1342 0x6: mov_ps({{ 1343 Fd1_sf = Fs1_sf; 1344 Fd2_sf = Fs2_sf; 1345 }}); 1346 0x7: neg_ps({{ 1347 Fd1_sf = -(Fs1_sf); 1348 Fd2_sf = -(Fs2_sf); 1349 }}); 1350 default: CP1Unimpl::unknown(); 1351 } 1352 } 1353 0x1: CP1Unimpl::unknown(); 1354 0x2: decode FUNCTION_LO { 1355 0x1: decode MOVCF { 1356 format Float64Op { 1357 0x0: movf_ps({{ 1358 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1359 Fs1 : Fd1; 1360 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 1361 Fs2 : Fd2; 1362 }}); 1363 0x1: movt_ps({{ 1364 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1365 Fs1 : Fd1; 1366 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 1367 Fs2 : Fd2; 1368 }}); 1369 } 1370 } 1371 1372 format Float64Op { 1373 0x2: movz_ps({{ 1374 Fd1 = (getCondCode(FCSR, CC) == 0) ? 1375 Fs1 : Fd1; 1376 Fd2 = (getCondCode(FCSR, CC) == 0) ? 1377 Fs2 : Fd2; 1378 }}); 1379 0x3: movn_ps({{ 1380 Fd1 = (getCondCode(FCSR, CC) == 1) ? 1381 Fs1 : Fd1; 1382 Fd2 = (getCondCode(FCSR, CC) == 1) ? 1383 Fs2 : Fd2; 1384 }}); 1385 } 1386 default: CP1Unimpl::unknown(); 1387 } 1388 0x3: CP1Unimpl::unknown(); 1389 0x4: decode FUNCTION_LO { 1390 0x0: FloatOp::cvt_s_pu({{ Fd_sf = Fs2_sf; }}); 1391 default: CP1Unimpl::unknown(); 1392 } 1393 1394 0x5: decode FUNCTION_LO { 1395 0x0: FloatOp::cvt_s_pl({{ Fd_sf = Fs1_sf; }}); 1396 format Float64Op { 1397 0x4: pll({{ 1398 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft1_uw; 1399 }}); 1400 0x5: plu({{ 1401 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft2_uw; 1402 }}); 1403 0x6: pul({{ 1404 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft1_uw; 1405 }}); 1406 0x7: puu({{ 1407 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft2_uw; 1408 }}); 1409 } 1410 default: CP1Unimpl::unknown(); 1411 } 1412 1413 0x6: decode FUNCTION_LO { 1414 format FloatPSCompareOp { 1415 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1416 UnorderedFalse); 1417 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1418 UnorderedTrue); 1419 0x2: c_eq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1420 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1421 UnorderedFalse); 1422 0x3: c_ueq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1423 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1424 UnorderedTrue); 1425 0x4: c_olt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1426 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1427 UnorderedFalse); 1428 0x5: c_ult_ps({{ cond1 = (Fs_sf < Ft_sf); }}, 1429 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1430 UnorderedTrue); 1431 0x6: c_ole_ps({{ cond1 = (Fs_sf <= Ft_sf); }}, 1432 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1433 UnorderedFalse); 1434 0x7: c_ule_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1435 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1436 UnorderedTrue); 1437 } 1438 } 1439 1440 0x7: decode FUNCTION_LO { 1441 format FloatPSCompareOp { 1442 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1443 UnorderedFalse, QnanException); 1444 0x1: c_ngle_ps({{ cond1 = 0; }}, 1445 {{ cond2 = 0; }}, 1446 UnorderedTrue, QnanException); 1447 0x2: c_seq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1448 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1449 UnorderedFalse, QnanException); 1450 0x3: c_ngl_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1451 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1452 UnorderedTrue, QnanException); 1453 0x4: c_lt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1454 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1455 UnorderedFalse, QnanException); 1456 0x5: c_nge_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1457 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1458 UnorderedTrue, QnanException); 1459 0x6: c_le_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1460 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1461 UnorderedFalse, QnanException); 1462 0x7: c_ngt_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1463 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1464 UnorderedTrue, QnanException); 1465 } 1466 } 1467 } 1468 } 1469 default: CP1Unimpl::unknown(); 1470 } 1471 } 1472 1473 //Table A-19 MIPS32 COP2 Encoding of rs Field 1474 0x2: decode RS_MSB { 1475 format CP2Unimpl { 1476 0x0: decode RS_HI { 1477 0x0: decode RS_LO { 1478 0x0: mfc2(); 1479 0x2: cfc2(); 1480 0x3: mfhc2(); 1481 0x4: mtc2(); 1482 0x6: ctc2(); 1483 0x7: mftc2(); 1484 default: unknown(); 1485 } 1486 1487 0x1: decode ND { 1488 0x0: decode TF { 1489 0x0: bc2f(); 1490 0x1: bc2t(); 1491 default: unknown(); 1492 } 1493 1494 0x1: decode TF { 1495 0x0: bc2fl(); 1496 0x1: bc2tl(); 1497 default: unknown(); 1498 } 1499 default: unknown(); 1500 1501 } 1502 default: unknown(); 1503 } 1504 default: unknown(); 1505 } 1506 } 1507 1508 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1509 //Note: "COP1X instructions are legal only if 64-bit floating point 1510 //operations are enabled." 1511 0x3: decode FUNCTION_HI { 1512 0x0: decode FUNCTION_LO { 1513 format LoadIndexedMemory { 1514 0x0: lwxc1({{ Fd_uw = Mem; }}); 1515 0x1: ldxc1({{ Fd_ud = Mem_ud; }}); 1516 0x5: luxc1({{ Fd_ud = Mem_ud; }}, 1517 {{ EA = (Rs + Rt) & ~7; }}); 1518 } 1519 } 1520 1521 0x1: decode FUNCTION_LO { 1522 format StoreIndexedMemory { 1523 0x0: swxc1({{ Mem = Fs_uw; }}); 1524 0x1: sdxc1({{ Mem_ud = Fs_ud; }}); 1525 0x5: suxc1({{ Mem_ud = Fs_ud; }}, 1526 {{ EA = (Rs + Rt) & ~7; }}); 1527 } 1528 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1529 } 1530 1531 0x3: decode FUNCTION_LO { 1532 0x6: Float64Op::alnv_ps({{ 1533 if (Rs<2:0> == 0) { 1534 Fd_ud = Fs_ud; 1535 } else if (Rs<2:0> == 4) { 1536 if (GuestByteOrder == BigEndianByteOrder) 1537 Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>; 1538 else 1539 Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; 1540 } else { 1541 Fd_ud = Fd_ud; 1542 } 1543 }}); 1544 } 1545 1546 format FloatAccOp { 1547 0x4: decode FUNCTION_LO { 1548 0x0: madd_s({{ Fd_sf = (Fs_sf * Ft_sf) + Fr_sf; }}); 1549 0x1: madd_d({{ Fd_df = (Fs_df * Ft_df) + Fr_df; }}); 1550 0x6: madd_ps({{ 1551 Fd1_sf = (Fs1_df * Ft1_df) + Fr1_df; 1552 Fd2_sf = (Fs2_df * Ft2_df) + Fr2_df; 1553 }}); 1554 } 1555 1556 0x5: decode FUNCTION_LO { 1557 0x0: msub_s({{ Fd_sf = (Fs_sf * Ft_sf) - Fr_sf; }}); 1558 0x1: msub_d({{ Fd_df = (Fs_df * Ft_df) - Fr_df; }}); 1559 0x6: msub_ps({{ 1560 Fd1_sf = (Fs1_df * Ft1_df) - Fr1_df; 1561 Fd2_sf = (Fs2_df * Ft2_df) - Fr2_df; 1562 }}); 1563 } 1564 1565 0x6: decode FUNCTION_LO { 1566 0x0: nmadd_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) - Fr_sf; }}); 1567 0x1: nmadd_d({{ Fd_df = (-1 * Fs_df * Ft_df) - Fr_df; }}); 1568 0x6: nmadd_ps({{ 1569 Fd1_sf = -((Fs1_df * Ft1_df) + Fr1_df); 1570 Fd2_sf = -((Fs2_df * Ft2_df) + Fr2_df); 1571 }}); 1572 } 1573 1574 0x7: decode FUNCTION_LO { 1575 0x0: nmsub_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) + Fr_sf; }}); 1576 0x1: nmsub_d({{ Fd_df = (-1 * Fs_df * Ft_df) + Fr_df; }}); 1577 0x6: nmsub_ps({{ 1578 Fd1_sf = -((Fs1_df * Ft1_df) - Fr1_df); 1579 Fd2_sf = -((Fs2_df * Ft2_df) - Fr2_df); 1580 }}); 1581 } 1582 } 1583 } 1584 1585 format Branch { 1586 0x4: beql({{ cond = (Rs_sw == Rt_sw); }}, Likely); 1587 0x5: bnel({{ cond = (Rs_sw != Rt_sw); }}, Likely); 1588 0x6: blezl({{ cond = (Rs_sw <= 0); }}, Likely); 1589 0x7: bgtzl({{ cond = (Rs_sw > 0); }}, Likely); 1590 } 1591 } 1592 1593 0x3: decode OPCODE_LO { 1594 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1595 0x4: decode FUNCTION_HI { 1596 0x0: decode FUNCTION_LO { 1597 0x2: IntOp::mul({{ 1598 int64_t temp1 = Rs_sd * Rt_sd; 1599 Rd = temp1<31:0>; 1600 }}, IntMultOp); 1601 1602 format HiLoRdSelValOp { 1603 0x0: madd({{ 1604 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1605 (Rs_sd * Rt_sd); 1606 }}, IntMultOp); 1607 0x1: maddu({{ 1608 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1609 (Rs_ud * Rt_ud); 1610 }}, IntMultOp); 1611 0x4: msub({{ 1612 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1613 (Rs_sd * Rt_sd); 1614 }}, IntMultOp); 1615 0x5: msubu({{ 1616 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1617 (Rs_ud * Rt_ud); 1618 }}, IntMultOp); 1619 } 1620 } 1621 1622 0x4: decode FUNCTION_LO { 1623 format BasicOp { 1624 0x0: clz({{ 1625 int cnt = 32; 1626 for (int idx = 31; idx >= 0; idx--) { 1627 if (Rs<idx:idx> == 1) { 1628 cnt = 31 - idx; 1629 break; 1630 } 1631 } 1632 Rd = cnt; 1633 }}); 1634 0x1: clo({{ 1635 int cnt = 32; 1636 for (int idx = 31; idx >= 0; idx--) { 1637 if (Rs<idx:idx> == 0) { 1638 cnt = 31 - idx; 1639 break; 1640 } 1641 } 1642 Rd = cnt; 1643 }}); 1644 } 1645 } 1646 1647 0x7: decode FUNCTION_LO { 1648 0x7: FailUnimpl::sdbbp(); 1649 } 1650 } 1651 1652 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1653 //of the Architecture 1654 0x7: decode FUNCTION_HI { 1655 0x0: decode FUNCTION_LO { 1656 format BasicOp { 1657 0x0: ext({{ Rt = bits(Rs, MSB + LSB, LSB); }}); 1658 0x4: ins({{ 1659 Rt = bits(Rt, 31, MSB + 1) << (MSB + 1) | 1660 bits(Rs, MSB - LSB, 0) << LSB | 1661 bits(Rt, LSB - 1, 0); 1662 }}); 1663 } 1664 } 1665 1666 0x1: decode FUNCTION_LO { 1667 format MT_Control { 1668 0x0: fork({{ 1669 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1670 }}, UserMode); 1671 0x1: yield({{ 1672 Rd = yieldThread(xc->tcBase(), fault, Rs_sw, 1673 YQMask); 1674 }}, UserMode); 1675 } 1676 1677 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1678 0x2: decode OP_HI { 1679 0x0: decode OP_LO { 1680 format LoadIndexedMemory { 1681 0x0: lwx({{ Rd = Mem; }}); 1682 0x4: lhx({{ Rd = Mem_sh; }}); 1683 0x6: lbux({{ Rd = Mem_ub; }}); 1684 } 1685 } 1686 } 1687 0x4: DspIntOp::insv({{ 1688 int pos = dspctl<5:0>; 1689 int size = dspctl<12:7> - 1; 1690 Rt = insertBits(Rt, pos + size, pos, Rs<size:0>); 1691 }}); 1692 } 1693 1694 0x2: decode FUNCTION_LO { 1695 1696 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1697 //(DSP ASE MANUAL) 1698 0x0: decode OP_HI { 1699 0x0: decode OP_LO { 1700 format DspIntOp { 1701 0x0: addu_qb({{ 1702 Rd = dspAdd(Rs, Rt, SIMD_FMT_QB, 1703 NOSATURATE, UNSIGNED, &dspctl); 1704 }}); 1705 0x1: subu_qb({{ 1706 Rd = dspSub(Rs, Rt, SIMD_FMT_QB, 1707 NOSATURATE, UNSIGNED, &dspctl); 1708 }}); 1709 0x4: addu_s_qb({{ 1710 Rd = dspAdd(Rs, Rt, SIMD_FMT_QB, 1711 SATURATE, UNSIGNED, &dspctl); 1712 }}); 1713 0x5: subu_s_qb({{ 1714 Rd = dspSub(Rs, Rt, SIMD_FMT_QB, 1715 SATURATE, UNSIGNED, &dspctl); 1716 }}); 1717 0x6: muleu_s_ph_qbl({{ 1718 Rd = dspMuleu(Rs, Rt, MODE_L, &dspctl); 1719 }}, IntMultOp); 1720 0x7: muleu_s_ph_qbr({{ 1721 Rd = dspMuleu(Rs, Rt, MODE_R, &dspctl); 1722 }}, IntMultOp); 1723 } 1724 } 1725 0x1: decode OP_LO { 1726 format DspIntOp { 1727 0x0: addu_ph({{ 1728 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH, 1729 NOSATURATE, UNSIGNED, &dspctl); 1730 }}); 1731 0x1: subu_ph({{ 1732 Rd = dspSub(Rs, Rt, SIMD_FMT_PH, 1733 NOSATURATE, UNSIGNED, &dspctl); 1734 }}); 1735 0x2: addq_ph({{ 1736 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH, 1737 NOSATURATE, SIGNED, &dspctl); 1738 }}); 1739 0x3: subq_ph({{ 1740 Rd = dspSub(Rs, Rt, SIMD_FMT_PH, 1741 NOSATURATE, SIGNED, &dspctl); 1742 }}); 1743 0x4: addu_s_ph({{ 1744 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH, 1745 SATURATE, UNSIGNED, &dspctl); 1746 }}); 1747 0x5: subu_s_ph({{ 1748 Rd = dspSub(Rs, Rt, SIMD_FMT_PH, 1749 SATURATE, UNSIGNED, &dspctl); 1750 }}); 1751 0x6: addq_s_ph({{ 1752 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH, 1753 SATURATE, SIGNED, &dspctl); 1754 }}); 1755 0x7: subq_s_ph({{ 1756 Rd = dspSub(Rs, Rt, SIMD_FMT_PH, 1757 SATURATE, SIGNED, &dspctl); 1758 }}); 1759 } 1760 } 1761 0x2: decode OP_LO { 1762 format DspIntOp { 1763 0x0: addsc({{ 1764 int64_t dresult; 1765 dresult = Rs_ud + Rt_ud; 1766 Rd = dresult<31:0>; 1767 dspctl = insertBits(dspctl, 13, 13, 1768 dresult<32:32>); 1769 }}); 1770 0x1: addwc({{ 1771 int64_t dresult; 1772 dresult = Rs_sd + Rt_sd + dspctl<13:13>; 1773 Rd = dresult<31:0>; 1774 if (dresult<32:32> != dresult<31:31>) 1775 dspctl = insertBits(dspctl, 20, 20, 1); 1776 }}); 1777 0x2: modsub({{ 1778 Rd = (Rs_sw == 0) ? Rt_sw<23:8> : 1779 Rs_sw - Rt_sw<7:0>; 1780 }}); 1781 0x4: raddu_w_qb({{ 1782 Rd = Rs<31:24> + Rs<23:16> + 1783 Rs<15:8> + Rs<7:0>; 1784 }}); 1785 0x6: addq_s_w({{ 1786 Rd = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W, 1787 SATURATE, SIGNED, &dspctl); 1788 }}); 1789 0x7: subq_s_w({{ 1790 Rd = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W, 1791 SATURATE, SIGNED, &dspctl); 1792 }}); 1793 } 1794 } 1795 0x3: decode OP_LO { 1796 format DspIntOp { 1797 0x4: muleq_s_w_phl({{ 1798 Rd = dspMuleq(Rs_sw, Rt_sw, 1799 MODE_L, &dspctl); 1800 }}, IntMultOp); 1801 0x5: muleq_s_w_phr({{ 1802 Rd = dspMuleq(Rs_sw, Rt_sw, 1803 MODE_R, &dspctl); 1804 }}, IntMultOp); 1805 0x6: mulq_s_ph({{ 1806 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1807 SATURATE, NOROUND, &dspctl); 1808 }}, IntMultOp); 1809 0x7: mulq_rs_ph({{ 1810 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1811 SATURATE, ROUND, &dspctl); 1812 }}, IntMultOp); 1813 } 1814 } 1815 } 1816 1817 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1818 //(DSP ASE MANUAL) 1819 0x1: decode OP_HI { 1820 0x0: decode OP_LO { 1821 format DspIntOp { 1822 0x0: cmpu_eq_qb({{ 1823 dspCmp(Rs, Rt, SIMD_FMT_QB, 1824 UNSIGNED, CMP_EQ, &dspctl); 1825 }}); 1826 0x1: cmpu_lt_qb({{ 1827 dspCmp(Rs, Rt, SIMD_FMT_QB, 1828 UNSIGNED, CMP_LT, &dspctl); 1829 }}); 1830 0x2: cmpu_le_qb({{ 1831 dspCmp(Rs, Rt, SIMD_FMT_QB, 1832 UNSIGNED, CMP_LE, &dspctl); 1833 }}); 1834 0x3: pick_qb({{ 1835 Rd = dspPick(Rs, Rt, SIMD_FMT_QB, &dspctl); 1836 }}); 1837 0x4: cmpgu_eq_qb({{ 1838 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB, 1839 UNSIGNED, CMP_EQ ); 1840 }}); 1841 0x5: cmpgu_lt_qb({{ 1842 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB, 1843 UNSIGNED, CMP_LT); 1844 }}); 1845 0x6: cmpgu_le_qb({{ 1846 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB, 1847 UNSIGNED, CMP_LE); 1848 }}); 1849 } 1850 } 1851 0x1: decode OP_LO { 1852 format DspIntOp { 1853 0x0: cmp_eq_ph({{ 1854 dspCmp(Rs, Rt, SIMD_FMT_PH, 1855 SIGNED, CMP_EQ, &dspctl); 1856 }}); 1857 0x1: cmp_lt_ph({{ 1858 dspCmp(Rs, Rt, SIMD_FMT_PH, 1859 SIGNED, CMP_LT, &dspctl); 1860 }}); 1861 0x2: cmp_le_ph({{ 1862 dspCmp(Rs, Rt, SIMD_FMT_PH, 1863 SIGNED, CMP_LE, &dspctl); 1864 }}); 1865 0x3: pick_ph({{ 1866 Rd = dspPick(Rs, Rt, SIMD_FMT_PH, &dspctl); 1867 }}); 1868 0x4: precrq_qb_ph({{ 1869 Rd = Rs<31:24> << 24 | Rs<15:8> << 16 | 1870 Rt<31:24> << 8 | Rt<15:8>; 1871 }}); 1872 0x5: precr_qb_ph({{ 1873 Rd = Rs<23:16> << 24 | Rs<7:0> << 16 | 1874 Rt<23:16> << 8 | Rt<7:0>; 1875 }}); 1876 0x6: packrl_ph({{ 1877 Rd = dspPack(Rs, Rt, SIMD_FMT_PH); 1878 }}); 1879 0x7: precrqu_s_qb_ph({{ 1880 Rd = dspPrecrqu(Rs, Rt, &dspctl); 1881 }}); 1882 } 1883 } 1884 0x2: decode OP_LO { 1885 format DspIntOp { 1886 0x4: precrq_ph_w({{ 1887 Rd = Rs<31:16> << 16 | Rt<31:16>; 1888 }}); 1889 0x5: precrq_rs_ph_w({{ 1890 Rd = dspPrecrq(Rs, Rt, SIMD_FMT_W, &dspctl); 1891 }}); 1892 } 1893 } 1894 0x3: decode OP_LO { 1895 format DspIntOp { 1896 0x0: cmpgdu_eq_qb({{ 1897 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB, 1898 UNSIGNED, CMP_EQ, &dspctl); 1899 }}); 1900 0x1: cmpgdu_lt_qb({{ 1901 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB, 1902 UNSIGNED, CMP_LT, &dspctl); 1903 }}); 1904 0x2: cmpgdu_le_qb({{ 1905 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB, 1906 UNSIGNED, CMP_LE, &dspctl); 1907 }}); 1908 0x6: precr_sra_ph_w({{ 1909 Rt = dspPrecrSra(Rt, Rs, RD, 1910 SIMD_FMT_W, NOROUND); 1911 }}); 1912 0x7: precr_sra_r_ph_w({{ 1913 Rt = dspPrecrSra(Rt, Rs, RD, 1914 SIMD_FMT_W, ROUND); 1915 }}); 1916 } 1917 } 1918 } 1919 1920 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1921 //(DSP ASE MANUAL) 1922 0x2: decode OP_HI { 1923 0x0: decode OP_LO { 1924 format DspIntOp { 1925 0x1: absq_s_qb({{ 1926 Rd = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl); 1927 }}); 1928 0x2: repl_qb({{ 1929 Rd = RS_RT<7:0> << 24 | RS_RT<7:0> << 16 | 1930 RS_RT<7:0> << 8 | RS_RT<7:0>; 1931 }}); 1932 0x3: replv_qb({{ 1933 Rd = Rt<7:0> << 24 | Rt<7:0> << 16 | 1934 Rt<7:0> << 8 | Rt<7:0>; 1935 }}); 1936 0x4: precequ_ph_qbl({{ 1937 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED, 1938 SIMD_FMT_PH, SIGNED, MODE_L); 1939 }}); 1940 0x5: precequ_ph_qbr({{ 1941 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED, 1942 SIMD_FMT_PH, SIGNED, MODE_R); 1943 }}); 1944 0x6: precequ_ph_qbla({{ 1945 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED, 1946 SIMD_FMT_PH, SIGNED, MODE_LA); 1947 }}); 1948 0x7: precequ_ph_qbra({{ 1949 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED, 1950 SIMD_FMT_PH, SIGNED, MODE_RA); 1951 }}); 1952 } 1953 } 1954 0x1: decode OP_LO { 1955 format DspIntOp { 1956 0x1: absq_s_ph({{ 1957 Rd = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl); 1958 }}); 1959 0x2: repl_ph({{ 1960 Rd = (sext<10>(RS_RT))<15:0> << 16 | 1961 (sext<10>(RS_RT))<15:0>; 1962 }}); 1963 0x3: replv_ph({{ 1964 Rd = Rt<15:0> << 16 | Rt<15:0>; 1965 }}); 1966 0x4: preceq_w_phl({{ 1967 Rd = dspPrece(Rt, SIMD_FMT_PH, SIGNED, 1968 SIMD_FMT_W, SIGNED, MODE_L); 1969 }}); 1970 0x5: preceq_w_phr({{ 1971 Rd = dspPrece(Rt, SIMD_FMT_PH, SIGNED, 1972 SIMD_FMT_W, SIGNED, MODE_R); 1973 }}); 1974 } 1975 } 1976 0x2: decode OP_LO { 1977 format DspIntOp { 1978 0x1: absq_s_w({{ 1979 Rd = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl); 1980 }}); 1981 } 1982 } 1983 0x3: decode OP_LO { 1984 0x3: IntOp::bitrev({{ 1985 Rd = bitrev(Rt<15:0>); 1986 }}); 1987 format DspIntOp { 1988 0x4: preceu_ph_qbl({{ 1989 Rd = dspPrece(Rt, SIMD_FMT_QB, 1990 UNSIGNED, SIMD_FMT_PH, 1991 UNSIGNED, MODE_L); 1992 }}); 1993 0x5: preceu_ph_qbr({{ 1994 Rd = dspPrece(Rt, SIMD_FMT_QB, 1995 UNSIGNED, SIMD_FMT_PH, 1996 UNSIGNED, MODE_R ); 1997 }}); 1998 0x6: preceu_ph_qbla({{ 1999 Rd = dspPrece(Rt, SIMD_FMT_QB, 2000 UNSIGNED, SIMD_FMT_PH, 2001 UNSIGNED, MODE_LA ); 2002 }}); 2003 0x7: preceu_ph_qbra({{ 2004 Rd = dspPrece(Rt, SIMD_FMT_QB, 2005 UNSIGNED, SIMD_FMT_PH, 2006 UNSIGNED, MODE_RA); 2007 }}); 2008 } 2009 } 2010 } 2011 2012 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 2013 //(DSP ASE MANUAL) 2014 0x3: decode OP_HI { 2015 0x0: decode OP_LO { 2016 format DspIntOp { 2017 0x0: shll_qb({{ 2018 Rd = dspShll(Rt_sw, RS, SIMD_FMT_QB, 2019 NOSATURATE, UNSIGNED, &dspctl); 2020 }}); 2021 0x1: shrl_qb({{ 2022 Rd = dspShrl(Rt_sw, RS, SIMD_FMT_QB, 2023 UNSIGNED); 2024 }}); 2025 0x2: shllv_qb({{ 2026 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB, 2027 NOSATURATE, UNSIGNED, &dspctl); 2028 }}); 2029 0x3: shrlv_qb({{ 2030 Rd = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB, 2031 UNSIGNED); 2032 }}); 2033 0x4: shra_qb({{ 2034 Rd = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2035 NOROUND, SIGNED, &dspctl); 2036 }}); 2037 0x5: shra_r_qb({{ 2038 Rd = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2039 ROUND, SIGNED, &dspctl); 2040 }}); 2041 0x6: shrav_qb({{ 2042 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2043 NOROUND, SIGNED, &dspctl); 2044 }}); 2045 0x7: shrav_r_qb({{ 2046 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2047 ROUND, SIGNED, &dspctl); 2048 }}); 2049 } 2050 } 2051 0x1: decode OP_LO { 2052 format DspIntOp { 2053 0x0: shll_ph({{ 2054 Rd = dspShll(Rt, RS, SIMD_FMT_PH, 2055 NOSATURATE, SIGNED, &dspctl); 2056 }}); 2057 0x1: shra_ph({{ 2058 Rd = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2059 NOROUND, SIGNED, &dspctl); 2060 }}); 2061 0x2: shllv_ph({{ 2062 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2063 NOSATURATE, SIGNED, &dspctl); 2064 }}); 2065 0x3: shrav_ph({{ 2066 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2067 NOROUND, SIGNED, &dspctl); 2068 }}); 2069 0x4: shll_s_ph({{ 2070 Rd = dspShll(Rt_sw, RS, SIMD_FMT_PH, 2071 SATURATE, SIGNED, &dspctl); 2072 }}); 2073 0x5: shra_r_ph({{ 2074 Rd = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2075 ROUND, SIGNED, &dspctl); 2076 }}); 2077 0x6: shllv_s_ph({{ 2078 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2079 SATURATE, SIGNED, &dspctl); 2080 }}); 2081 0x7: shrav_r_ph({{ 2082 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2083 ROUND, SIGNED, &dspctl); 2084 }}); 2085 } 2086 } 2087 0x2: decode OP_LO { 2088 format DspIntOp { 2089 0x4: shll_s_w({{ 2090 Rd = dspShll(Rt_sw, RS, SIMD_FMT_W, 2091 SATURATE, SIGNED, &dspctl); 2092 }}); 2093 0x5: shra_r_w({{ 2094 Rd = dspShra(Rt_sw, RS, SIMD_FMT_W, 2095 ROUND, SIGNED, &dspctl); 2096 }}); 2097 0x6: shllv_s_w({{ 2098 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W, 2099 SATURATE, SIGNED, &dspctl); 2100 }}); 2101 0x7: shrav_r_w({{ 2102 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W, 2103 ROUND, SIGNED, &dspctl); 2104 }}); 2105 } 2106 } 2107 0x3: decode OP_LO { 2108 format DspIntOp { 2109 0x1: shrl_ph({{ 2110 Rd = dspShrl(Rt_sw, RS, SIMD_FMT_PH, 2111 UNSIGNED); 2112 }}); 2113 0x3: shrlv_ph({{ 2114 Rd = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH, 2115 UNSIGNED); 2116 }}); 2117 } 2118 } 2119 } 2120 } 2121 2122 0x3: decode FUNCTION_LO { 2123 2124 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2125 //(DSP ASE Rev2 Manual) 2126 0x0: decode OP_HI { 2127 0x0: decode OP_LO { 2128 format DspIntOp { 2129 0x0: adduh_qb({{ 2130 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2131 NOROUND, UNSIGNED); 2132 }}); 2133 0x1: subuh_qb({{ 2134 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2135 NOROUND, UNSIGNED); 2136 }}); 2137 0x2: adduh_r_qb({{ 2138 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2139 ROUND, UNSIGNED); 2140 }}); 2141 0x3: subuh_r_qb({{ 2142 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2143 ROUND, UNSIGNED); 2144 }}); 2145 } 2146 } 2147 0x1: decode OP_LO { 2148 format DspIntOp { 2149 0x0: addqh_ph({{ 2150 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2151 NOROUND, SIGNED); 2152 }}); 2153 0x1: subqh_ph({{ 2154 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2155 NOROUND, SIGNED); 2156 }}); 2157 0x2: addqh_r_ph({{ 2158 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2159 ROUND, SIGNED); 2160 }}); 2161 0x3: subqh_r_ph({{ 2162 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2163 ROUND, SIGNED); 2164 }}); 2165 0x4: mul_ph({{ 2166 Rd = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2167 NOSATURATE, &dspctl); 2168 }}, IntMultOp); 2169 0x6: mul_s_ph({{ 2170 Rd = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2171 SATURATE, &dspctl); 2172 }}, IntMultOp); 2173 } 2174 } 2175 0x2: decode OP_LO { 2176 format DspIntOp { 2177 0x0: addqh_w({{ 2178 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2179 NOROUND, SIGNED); 2180 }}); 2181 0x1: subqh_w({{ 2182 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2183 NOROUND, SIGNED); 2184 }}); 2185 0x2: addqh_r_w({{ 2186 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2187 ROUND, SIGNED); 2188 }}); 2189 0x3: subqh_r_w({{ 2190 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2191 ROUND, SIGNED); 2192 }}); 2193 0x6: mulq_s_w({{ 2194 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2195 SATURATE, NOROUND, &dspctl); 2196 }}, IntMultOp); 2197 0x7: mulq_rs_w({{ 2198 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2199 SATURATE, ROUND, &dspctl); 2200 }}, IntMultOp); 2201 } 2202 } 2203 } 2204 } 2205 2206 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2207 0x4: decode SA { 2208 format BasicOp { 2209 0x02: wsbh({{ 2210 Rd = Rt<23:16> << 24 | Rt<31:24> << 16 | 2211 Rt<7:0> << 8 | Rt<15:8>; 2212 }}); 2213 0x10: seb({{ Rd = Rt_sb; }}); 2214 0x18: seh({{ Rd = Rt_sh; }}); 2215 } 2216 } 2217 2218 0x6: decode FUNCTION_LO { 2219 2220 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2221 //(DSP ASE MANUAL) 2222 0x0: decode OP_HI { 2223 0x0: decode OP_LO { 2224 format DspHiLoOp { 2225 0x0: dpa_w_ph({{ 2226 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2227 SIMD_FMT_PH, SIGNED, MODE_L); 2228 }}, IntMultOp); 2229 0x1: dps_w_ph({{ 2230 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2231 SIMD_FMT_PH, SIGNED, MODE_L); 2232 }}, IntMultOp); 2233 0x2: mulsa_w_ph({{ 2234 dspac = dspMulsa(dspac, Rs_sw, Rt_sw, 2235 ACDST, SIMD_FMT_PH ); 2236 }}, IntMultOp); 2237 0x3: dpau_h_qbl({{ 2238 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2239 SIMD_FMT_QB, UNSIGNED, MODE_L); 2240 }}, IntMultOp); 2241 0x4: dpaq_s_w_ph({{ 2242 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2243 ACDST, SIMD_FMT_PH, 2244 SIMD_FMT_W, NOSATURATE, 2245 MODE_L, &dspctl); 2246 }}, IntMultOp); 2247 0x5: dpsq_s_w_ph({{ 2248 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2249 ACDST, SIMD_FMT_PH, 2250 SIMD_FMT_W, NOSATURATE, 2251 MODE_L, &dspctl); 2252 }}, IntMultOp); 2253 0x6: mulsaq_s_w_ph({{ 2254 dspac = dspMulsaq(dspac, Rs_sw, Rt_sw, 2255 ACDST, SIMD_FMT_PH, 2256 &dspctl); 2257 }}, IntMultOp); 2258 0x7: dpau_h_qbr({{ 2259 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2260 SIMD_FMT_QB, UNSIGNED, MODE_R); 2261 }}, IntMultOp); 2262 } 2263 } 2264 0x1: decode OP_LO { 2265 format DspHiLoOp { 2266 0x0: dpax_w_ph({{ 2267 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2268 SIMD_FMT_PH, SIGNED, MODE_X); 2269 }}, IntMultOp); 2270 0x1: dpsx_w_ph({{ 2271 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2272 SIMD_FMT_PH, SIGNED, MODE_X); 2273 }}, IntMultOp); 2274 0x3: dpsu_h_qbl({{ 2275 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2276 SIMD_FMT_QB, UNSIGNED, MODE_L); 2277 }}, IntMultOp); 2278 0x4: dpaq_sa_l_w({{ 2279 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2280 ACDST, SIMD_FMT_W, 2281 SIMD_FMT_L, SATURATE, 2282 MODE_L, &dspctl); 2283 }}, IntMultOp); 2284 0x5: dpsq_sa_l_w({{ 2285 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2286 ACDST, SIMD_FMT_W, 2287 SIMD_FMT_L, SATURATE, 2288 MODE_L, &dspctl); 2289 }}, IntMultOp); 2290 0x7: dpsu_h_qbr({{ 2291 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2292 SIMD_FMT_QB, UNSIGNED, MODE_R); 2293 }}, IntMultOp); 2294 } 2295 } 2296 0x2: decode OP_LO { 2297 format DspHiLoOp { 2298 0x0: maq_sa_w_phl({{ 2299 dspac = dspMaq(dspac, Rs, Rt, 2300 ACDST, SIMD_FMT_PH, 2301 MODE_L, SATURATE, &dspctl); 2302 }}, IntMultOp); 2303 0x2: maq_sa_w_phr({{ 2304 dspac = dspMaq(dspac, Rs, Rt, 2305 ACDST, SIMD_FMT_PH, 2306 MODE_R, SATURATE, &dspctl); 2307 }}, IntMultOp); 2308 0x4: maq_s_w_phl({{ 2309 dspac = dspMaq(dspac, Rs, Rt, 2310 ACDST, SIMD_FMT_PH, 2311 MODE_L, NOSATURATE, &dspctl); 2312 }}, IntMultOp); 2313 0x6: maq_s_w_phr({{ 2314 dspac = dspMaq(dspac, Rs, Rt, 2315 ACDST, SIMD_FMT_PH, 2316 MODE_R, NOSATURATE, &dspctl); 2317 }}, IntMultOp); 2318 } 2319 } 2320 0x3: decode OP_LO { 2321 format DspHiLoOp { 2322 0x0: dpaqx_s_w_ph({{ 2323 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2324 ACDST, SIMD_FMT_PH, 2325 SIMD_FMT_W, NOSATURATE, 2326 MODE_X, &dspctl); 2327 }}, IntMultOp); 2328 0x1: dpsqx_s_w_ph({{ 2329 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2330 ACDST, SIMD_FMT_PH, 2331 SIMD_FMT_W, NOSATURATE, 2332 MODE_X, &dspctl); 2333 }}, IntMultOp); 2334 0x2: dpaqx_sa_w_ph({{ 2335 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2336 ACDST, SIMD_FMT_PH, 2337 SIMD_FMT_W, SATURATE, 2338 MODE_X, &dspctl); 2339 }}, IntMultOp); 2340 0x3: dpsqx_sa_w_ph({{ 2341 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2342 ACDST, SIMD_FMT_PH, 2343 SIMD_FMT_W, SATURATE, 2344 MODE_X, &dspctl); 2345 }}, IntMultOp); 2346 } 2347 } 2348 } 2349 2350 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2351 0x1: decode OP_HI { 2352 0x0: decode OP_LO { 2353 format IntOp { 2354 0x0: append({{ 2355 Rt = (Rt << RD) | bits(Rs, RD - 1, 0); 2356 }}); 2357 0x1: prepend({{ 2358 Rt = (Rt >> RD) | 2359 (bits(Rs, RD - 1, 0) << (32 - RD)); 2360 }}); 2361 } 2362 } 2363 0x2: decode OP_LO { 2364 format IntOp { 2365 0x0: balign({{ 2366 Rt = (Rt << (8 * BP)) | (Rs >> (8 * (4 - BP))); 2367 }}); 2368 } 2369 } 2370 } 2371 2372 } 2373 0x7: decode FUNCTION_LO { 2374 2375 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2376 //(DSP ASE MANUAL) 2377 0x0: decode OP_HI { 2378 0x0: decode OP_LO { 2379 format DspHiLoOp { 2380 0x0: extr_w({{ 2381 Rt = dspExtr(dspac, SIMD_FMT_W, RS, 2382 NOROUND, NOSATURATE, &dspctl); 2383 }}); 2384 0x1: extrv_w({{ 2385 Rt = dspExtr(dspac, SIMD_FMT_W, Rs, 2386 NOROUND, NOSATURATE, &dspctl); 2387 }}); 2388 0x2: extp({{ 2389 Rt = dspExtp(dspac, RS, &dspctl); 2390 }}); 2391 0x3: extpv({{ 2392 Rt = dspExtp(dspac, Rs, &dspctl); 2393 }}); 2394 0x4: extr_r_w({{ 2395 Rt = dspExtr(dspac, SIMD_FMT_W, RS, 2396 ROUND, NOSATURATE, &dspctl); 2397 }}); 2398 0x5: extrv_r_w({{ 2399 Rt = dspExtr(dspac, SIMD_FMT_W, Rs, 2400 ROUND, NOSATURATE, &dspctl); 2401 }}); 2402 0x6: extr_rs_w({{ 2403 Rt = dspExtr(dspac, SIMD_FMT_W, RS, 2404 ROUND, SATURATE, &dspctl); 2405 }}); 2406 0x7: extrv_rs_w({{ 2407 Rt = dspExtr(dspac, SIMD_FMT_W, Rs, 2408 ROUND, SATURATE, &dspctl); 2409 }}); 2410 } 2411 } 2412 0x1: decode OP_LO { 2413 format DspHiLoOp { 2414 0x2: extpdp({{ 2415 Rt = dspExtpd(dspac, RS, &dspctl); 2416 }}); 2417 0x3: extpdpv({{ 2418 Rt = dspExtpd(dspac, Rs, &dspctl); 2419 }}); 2420 0x6: extr_s_h({{ 2421 Rt = dspExtr(dspac, SIMD_FMT_PH, RS, 2422 NOROUND, SATURATE, &dspctl); 2423 }}); 2424 0x7: extrv_s_h({{ 2425 Rt = dspExtr(dspac, SIMD_FMT_PH, Rs, 2426 NOROUND, SATURATE, &dspctl); 2427 }}); 2428 } 2429 } 2430 0x2: decode OP_LO { 2431 format DspIntOp { 2432 0x2: rddsp({{ 2433 Rd = readDSPControl(&dspctl, RDDSPMASK); 2434 }}); 2435 0x3: wrdsp({{ 2436 writeDSPControl(&dspctl, Rs, WRDSPMASK); 2437 }}); 2438 } 2439 } 2440 0x3: decode OP_LO { 2441 format DspHiLoOp { 2442 0x2: shilo({{ 2443 if ((int64_t)sext<6>(HILOSA) < 0) { 2444 dspac = (uint64_t)dspac << 2445 -sext<6>(HILOSA); 2446 } else { 2447 dspac = (uint64_t)dspac >> 2448 sext<6>(HILOSA); 2449 } 2450 }}); 2451 0x3: shilov({{ 2452 if ((int64_t)sext<6>(Rs_sw<5:0>) < 0) { 2453 dspac = (uint64_t)dspac << 2454 -sext<6>(Rs_sw<5:0>); 2455 } else { 2456 dspac = (uint64_t)dspac >> 2457 sext<6>(Rs_sw<5:0>); 2458 } 2459 }}); 2460 0x7: mthlip({{ 2461 dspac = dspac << 32; 2462 dspac |= Rs; 2463 dspctl = insertBits(dspctl, 5, 0, 2464 dspctl<5:0> + 32); 2465 }}); 2466 } 2467 } 2468 } 2469 0x3: decode OP default FailUnimpl::rdhwr() { 2470 0x0: decode FullSystemInt { 2471 0: decode RD { 2472 29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); 2473 } 2474 } 2475 } 2476 } 2477 } 2478 } 2479 2480 0x4: decode OPCODE_LO { 2481 format LoadMemory { 2482 0x0: lb({{ Rt = Mem_sb; }}); 2483 0x1: lh({{ Rt = Mem_sh; }}); 2484 0x3: lw({{ Rt = Mem_sw; }}); 2485 0x4: lbu({{ Rt = Mem_ub;}}); 2486 0x5: lhu({{ Rt = Mem_uh; }}); 2487 } 2488 2489 format LoadUnalignedMemory { 2490 0x2: lwl({{ 2491 uint32_t mem_shift = 24 - (8 * byte_offset); 2492 Rt = mem_word << mem_shift | (Rt & mask(mem_shift)); 2493 }}); 2494 0x6: lwr({{ 2495 uint32_t mem_shift = 8 * byte_offset; 2496 Rt = (Rt & (mask(mem_shift) << (32 - mem_shift))) | 2497 (mem_word >> mem_shift); 2498 }}); 2499 } 2500 } 2501 2502 0x5: decode OPCODE_LO { 2503 format StoreMemory { 2504 0x0: sb({{ Mem_ub = Rt<7:0>; }}); 2505 0x1: sh({{ Mem_uh = Rt<15:0>; }}); 2506 0x3: sw({{ Mem = Rt<31:0>; }}); 2507 } 2508 2509 format StoreUnalignedMemory { 2510 0x2: swl({{ 2511 uint32_t reg_shift = 24 - (8 * byte_offset); 2512 uint32_t mem_shift = 32 - reg_shift; 2513 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2514 (Rt >> reg_shift); 2515 }}); 2516 0x6: swr({{ 2517 uint32_t reg_shift = 8 * byte_offset; 2518 mem_word = Rt << reg_shift | 2519 (mem_word & (mask(reg_shift))); 2520 }}); 2521 } 2522 format CP0Control { 2523 0x7: cache({{ 2524 //Addr CacheEA = Rs + OFFSET; 2525 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2526 }}); 2527 } 2528 } 2529 2530 0x6: decode OPCODE_LO { 2531 format LoadMemory { 2532 0x0: ll({{ Rt = Mem; }}, mem_flags=LLSC); 2533 0x1: lwc1({{ Ft_uw = Mem; }}); 2534 0x5: ldc1({{ Ft_ud = Mem_ud; }}); 2535 } 2536 0x2: CP2Unimpl::lwc2(); 2537 0x6: CP2Unimpl::ldc2(); 2538 0x3: Prefetch::pref(); 2539 } 2540 2541 2542 0x7: decode OPCODE_LO { 2543 0x0: StoreCond::sc({{ Mem = Rt; }}, 2544 {{ uint64_t tmp = write_result; 2545 Rt = (tmp == 0 || tmp == 1) ? tmp : Rt; 2546 }}, mem_flags=LLSC, 2547 inst_flags = IsStoreConditional); 2548 format StoreMemory { 2549 0x1: swc1({{ Mem = Ft_uw; }}); 2550 0x5: sdc1({{ Mem_ud = Ft_ud; }}); 2551 } 2552 0x2: CP2Unimpl::swc2(); 2553 0x6: CP2Unimpl::sdc2(); 2554 } 2555} 2556 2557 2558