bitfields.isa revision 5222:bb733a878f85
1// -*- mode:c++ -*-
2
3// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
4
5//  This software is part of the M5 simulator.
6
7//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
8//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
9//  TO THESE TERMS AND CONDITIONS.
10
11//  Permission is granted to use, copy, create derivative works and
12//  distribute this software and such derivative works for any purpose,
13//  so long as (1) the copyright notice above, this grant of permission,
14//  and the disclaimer below appear in all copies and derivative works
15//  made, (2) the copyright notice above is augmented as appropriate to
16//  reflect the addition of any new copyrightable work in a derivative
17//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
18//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
19//  advertising or publicity pertaining to the use or distribution of
20//  this software without specific, written prior authorization.
21
22//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
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24//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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26//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
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34
35//Authors: Korey L. Sewell
36//         Jaidev Patwardhan
37
38
39////////////////////////////////////////////////////////////////////
40//
41// Bitfield definitions.
42//
43
44def bitfield OPCODE     <31:26>;
45def bitfield OPCODE_HI  <31:29>;
46def bitfield OPCODE_LO  <28:26>;
47
48def bitfield REGIMM      <20:16>;
49def bitfield REGIMM_HI   <20:19>;
50def bitfield REGIMM_LO   <18:16>;
51
52def bitfield FUNCTION      < 5: 0>;
53def bitfield FUNCTION_HI   < 5: 3>;
54def bitfield FUNCTION_LO   < 2: 0>;
55
56def bitfield RS	      <25:21>;
57def bitfield RS_MSB   <25:25>;
58def bitfield RS_HI    <25:24>;
59def bitfield RS_LO    <23:21>;
60def bitfield RS_SRL   <25:22>;
61def bitfield RS_RT    <25:16>;
62def bitfield RT	      <20:16>;
63def bitfield RT_HI    <20:19>;
64def bitfield RT_LO    <18:16>;
65def bitfield RT_RD    <20:11>;
66def bitfield RD	      <15:11>;
67
68def bitfield INTIMM	  <15: 0>;
69def bitfield RS_RT_INTIMM <25: 0>;
70
71// Floating-point operate format
72def bitfield FMT      <25:21>;
73def bitfield FR       <25:21>;
74def bitfield FT	      <20:16>;
75def bitfield FS	      <15:11>;
76def bitfield FD	      <10:6>;
77
78def bitfield ND       <17:17>;
79def bitfield TF       <16:16>;
80def bitfield MOVCI    <16:16>;
81def bitfield MOVCF    <16:16>;
82def bitfield SRL      <21:21>;
83def bitfield SRLV     < 6: 6>;
84def bitfield SA       <10: 6>;
85
86// Floating Point Condition Codes
87def bitfield CC <10:8>;
88def bitfield BRANCH_CC <20:18>;
89
90// CP0 Register Select
91def bitfield SEL       < 2: 0>;
92
93// INTERRUPTS
94def bitfield SC       < 5: 5>;
95
96// Branch format
97def bitfield OFFSET <15: 0>; // displacement
98
99// Jmp format
100def bitfield JMPTARG	<25: 0>;
101def bitfield HINT	<10: 6>;
102
103def bitfield SYSCALLCODE <25: 6>;
104def bitfield TRAPCODE    <15:13>;
105
106// EXT/INS instructions
107def bitfield MSB	<15:11>;
108def bitfield LSB	<10: 6>;
109
110// M5 instructions
111def bitfield M5FUNC <7:0>;
112
113// DSP instructions
114def bitfield OP        <10:6>;
115def bitfield OP_HI     <10:9>;
116def bitfield OP_LO     <8:6>;
117def bitfield DSPSA     <23:21>;
118def bitfield HILOSA    <25:20>;
119def bitfield RDDSPMASK <21:16>;
120def bitfield WRDSPMASK <16:11>;
121def bitfield ACSRC     <22:21>;
122def bitfield ACDST     <12:11>;
123def bitfield BP        <12:11>;
124
125// MT Instructions
126def bitfield POS   <10: 6>;
127def bitfield MT_U     <5:5>;
128def bitfield MT_H     <4:4>;
129
130//Cache Ops
131def bitfield CACHE_OP <20:16>;
132