xref: /gem5/src/arch/mips/isa/bitfields.isa

// -*- mode:c++ -*-

// Copyright (c) 2007 MIPS Technologies, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Korey Sewell
//          Jaidev Patwardhan

////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//

def bitfield OPCODE     <31:26>;
def bitfield OPCODE_HI  <31:29>;
def bitfield OPCODE_LO  <28:26>;

def bitfield REGIMM      <20:16>;
def bitfield REGIMM_HI   <20:19>;
def bitfield REGIMM_LO   <18:16>;

def bitfield FUNCTION      < 5: 0>;
def bitfield FUNCTION_HI   < 5: 3>;
def bitfield FUNCTION_LO   < 2: 0>;

def bitfield RS       <25:21>;
def bitfield RS_MSB   <25:25>;
def bitfield RS_HI    <25:24>;
def bitfield RS_LO    <23:21>;
def bitfield RS_SRL   <25:22>;
def bitfield RS_RT    <25:16>;
def bitfield RT       <20:16>;
def bitfield RT_HI    <20:19>;
def bitfield RT_LO    <18:16>;
def bitfield RT_RD    <20:11>;
def bitfield RD       <15:11>;

def bitfield INTIMM       <15: 0>;
def bitfield RS_RT_INTIMM <25: 0>;

// Floating-point operate format
def bitfield FMT      <25:21>;
def bitfield FR       <25:21>;
def bitfield FT       <20:16>;
def bitfield FS       <15:11>;
def bitfield FD       <10:6>;

def bitfield ND       <17:17>;
def bitfield TF       <16:16>;
def bitfield MOVCI    <16:16>;
def bitfield MOVCF    <16:16>;
def bitfield SRL      <21:21>;
def bitfield SRLV     < 6: 6>;
def bitfield SA       <10: 6>;

// Floating Point Condition Codes
def bitfield CC <10:8>;
def bitfield BRANCH_CC <20:18>;

// CP0 Register Select
def bitfield SEL       < 2: 0>;

// INTERRUPTS
def bitfield SC       < 5: 5>;

// Branch format
def bitfield OFFSET <15: 0>; // displacement

// Jmp format
def bitfield JMPTARG    <25: 0>;
def bitfield HINT       <10: 6>;

def bitfield SYSCALLCODE <25: 6>;
def bitfield TRAPCODE    <15:13>;

// EXT/INS instructions
def bitfield MSB        <15:11>;
def bitfield LSB        <10: 6>;

// M5 instructions
def bitfield M5FUNC <7:0>;

// DSP instructions
def bitfield OP        <10:6>;
def bitfield OP_HI     <10:9>;
def bitfield OP_LO     <8:6>;
def bitfield DSPSA     <23:21>;
def bitfield HILOSA    <25:20>;
def bitfield RDDSPMASK <21:16>;
def bitfield WRDSPMASK <16:11>;
def bitfield ACSRC     <22:21>;
def bitfield ACDST     <12:11>;
def bitfield BP        <12:11>;

// MT Instructions
def bitfield POS   <10: 6>;
def bitfield MT_U     <5:5>;
def bitfield MT_H     <4:4>;

//Cache Ops
def bitfield CACHE_OP <20:16>;