base.isa revision 5254:c555f8b07345
112SN/A// -*- mode:c++ -*- 210037SARM gem5 Developers 310037SARM gem5 Developers// Copyright (c) 2007 MIPS Technologies, Inc. 410037SARM gem5 Developers// All rights reserved. 510037SARM gem5 Developers// 610037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 710037SARM gem5 Developers// modification, are permitted provided that the following conditions are 810037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 910037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1010037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 1110037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 1210037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 1310037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 141762SN/A// contributors may be used to endorse or promote products derived from 1512SN/A// this software without specific prior written permission. 1612SN/A// 1712SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1812SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1912SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2012SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2112SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2212SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2312SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2412SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2512SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2612SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2712SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2812SN/A// 2912SN/A// Authors: Korey Sewell 3012SN/A 3112SN/A//////////////////////////////////////////////////////////////////// 3212SN/A// 3312SN/A// Base class for MIPS instructions, and some support functions 3412SN/A// 3512SN/A 3612SN/A//Outputs to decoder.hh 3712SN/Aoutput header {{ 3812SN/A 392665Ssaidi@eecs.umich.edu using namespace MipsISA; 402665Ssaidi@eecs.umich.edu 412665Ssaidi@eecs.umich.edu /** 4212SN/A * Base class for all MIPS static instructions. 4312SN/A */ 4411389Sbrandon.potter@amd.com class MipsStaticInst : public StaticInst 4511389Sbrandon.potter@amd.com { 4611389Sbrandon.potter@amd.com protected: 4711389Sbrandon.potter@amd.com 4811389Sbrandon.potter@amd.com // Constructor 4911389Sbrandon.potter@amd.com MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) 5011389Sbrandon.potter@amd.com : StaticInst(mnem, _machInst, __opClass) 5111389Sbrandon.potter@amd.com { 525616Snate@binkert.org } 5312SN/A 5412SN/A /// Print a register name for disassembly given the unique 5511389Sbrandon.potter@amd.com /// dependence tag number (FP or int). 564484Sbinkertn@umich.edu void printReg(std::ostream &os, int reg) const; 572439SN/A 587676Snate@binkert.org std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 598232Snate@binkert.org }; 6011389Sbrandon.potter@amd.com 612423SN/A}}; 622423SN/A 6312SN/A//Ouputs to decoder.cc 6412SN/Aoutput decoder {{ 6512SN/A 6611389Sbrandon.potter@amd.com void MipsStaticInst::printReg(std::ostream &os, int reg) const 6711389Sbrandon.potter@amd.com { 6812SN/A if (reg < FP_Base_DepTag) { 69443SN/A ccprintf(os, "r%d", reg); 70443SN/A } 712207SN/A else { 722207SN/A ccprintf(os, "f%d", reg - FP_Base_DepTag); 73443SN/A } 74468SN/A } 751708SN/A 761708SN/A std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const 77443SN/A { 78468SN/A std::stringstream ss; 79443SN/A 80443SN/A ccprintf(ss, "%-10s ", mnemonic); 81443SN/A 82468SN/A // Need to find standard way to not print 8310037SARM gem5 Developers // this info. Maybe add bool variable to 84443SN/A // class? 85443SN/A if (mnemonic != "syscall") { 86443SN/A if(_numDestRegs > 0){ 872476SN/A printReg(ss, _destRegIdx[0]); 882207SN/A } 892207SN/A 902207SN/A if(_numSrcRegs > 0) { 912207SN/A ss << ", "; 922207SN/A printReg(ss, _srcRegIdx[0]); 934111Sgblack@eecs.umich.edu } 944111Sgblack@eecs.umich.edu 952620SN/A if(_numSrcRegs > 1) { 964111Sgblack@eecs.umich.edu ss << ", "; 974111Sgblack@eecs.umich.edu printReg(ss, _srcRegIdx[1]); 984111Sgblack@eecs.umich.edu } 994111Sgblack@eecs.umich.edu } 1004111Sgblack@eecs.umich.edu 1012207SN/A // Should we define a separate inst. class 1022207SN/A // just for two insts? 1035383Sgblack@eecs.umich.edu if(mnemonic == "sll" || mnemonic == "sra"){ 1045383Sgblack@eecs.umich.edu ccprintf(ss,", %d",SA); 1055383Sgblack@eecs.umich.edu } 1065383Sgblack@eecs.umich.edu 1075383Sgblack@eecs.umich.edu return ss.str(); 1085383Sgblack@eecs.umich.edu } 1095383Sgblack@eecs.umich.edu 1104166Sgblack@eecs.umich.edu}}; 1114166Sgblack@eecs.umich.edu 1125874Sgblack@eecs.umich.edu