base.isa revision 5222
12089SN/A// -*- mode:c++ -*- 22089SN/A 35222Sksewell@umich.edu// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved 45222Sksewell@umich.edu 55222Sksewell@umich.edu// This software is part of the M5 simulator. 65222Sksewell@umich.edu 75222Sksewell@umich.edu// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 85222Sksewell@umich.edu// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 95222Sksewell@umich.edu// TO THESE TERMS AND CONDITIONS. 105222Sksewell@umich.edu 115222Sksewell@umich.edu// Permission is granted to use, copy, create derivative works and 125222Sksewell@umich.edu// distribute this software and such derivative works for any purpose, 135222Sksewell@umich.edu// so long as (1) the copyright notice above, this grant of permission, 145222Sksewell@umich.edu// and the disclaimer below appear in all copies and derivative works 155222Sksewell@umich.edu// made, (2) the copyright notice above is augmented as appropriate to 165222Sksewell@umich.edu// reflect the addition of any new copyrightable work in a derivative 175222Sksewell@umich.edu// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3) 185222Sksewell@umich.edu// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any 195222Sksewell@umich.edu// advertising or publicity pertaining to the use or distribution of 205222Sksewell@umich.edu// this software without specific, written prior authorization. 215222Sksewell@umich.edu 225222Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND 235222Sksewell@umich.edu// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 245222Sksewell@umich.edu// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 255222Sksewell@umich.edu// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 265222Sksewell@umich.edu// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 275222Sksewell@umich.edu// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 285222Sksewell@umich.edu// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 295222Sksewell@umich.edu// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 305222Sksewell@umich.edu// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 315222Sksewell@umich.edu// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 325222Sksewell@umich.edu// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 335222Sksewell@umich.edu// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 345222Sksewell@umich.edu 355222Sksewell@umich.edu//Authors: Korey L. Sewell 362706Sksewell@umich.edu 372088SN/A//////////////////////////////////////////////////////////////////// 382088SN/A// 392089SN/A// Base class for MIPS instructions, and some support functions 402088SN/A// 412088SN/A 422089SN/A//Outputs to decoder.hh 432088SN/Aoutput header {{ 442239SN/A 452239SN/A using namespace MipsISA; 462239SN/A 472131SN/A /** 482131SN/A * Base class for all MIPS static instructions. 492131SN/A */ 502131SN/A class MipsStaticInst : public StaticInst 512131SN/A { 522131SN/A protected: 532131SN/A 542131SN/A // Constructor 552131SN/A MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) 562131SN/A : StaticInst(mnem, _machInst, __opClass) 572088SN/A { 582131SN/A } 592088SN/A 602131SN/A /// Print a register name for disassembly given the unique 612131SN/A /// dependence tag number (FP or int). 622131SN/A void printReg(std::ostream &os, int reg) const; 632088SN/A 642131SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 652131SN/A }; 662088SN/A 672088SN/A}}; 682088SN/A 692089SN/A//Ouputs to decoder.cc 702088SN/Aoutput decoder {{ 712088SN/A 722131SN/A void MipsStaticInst::printReg(std::ostream &os, int reg) const 732131SN/A { 742131SN/A if (reg < FP_Base_DepTag) { 752131SN/A ccprintf(os, "r%d", reg); 762131SN/A } 772131SN/A else { 782131SN/A ccprintf(os, "f%d", reg - FP_Base_DepTag); 792131SN/A } 802131SN/A } 812131SN/A 822131SN/A std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const 832131SN/A { 842131SN/A std::stringstream ss; 852131SN/A 862131SN/A ccprintf(ss, "%-10s ", mnemonic); 872131SN/A 882965Sksewell@umich.edu // Need to find standard way to not print 892965Sksewell@umich.edu // this info. Maybe add bool variable to 902965Sksewell@umich.edu // class? 915222Sksewell@umich.edu if (mnemonic != "syscall") { 922965Sksewell@umich.edu if(_numDestRegs > 0){ 932965Sksewell@umich.edu printReg(ss, _destRegIdx[0]); 942965Sksewell@umich.edu } 952965Sksewell@umich.edu 962965Sksewell@umich.edu if(_numSrcRegs > 0) { 972965Sksewell@umich.edu ss << ", "; 982965Sksewell@umich.edu printReg(ss, _srcRegIdx[0]); 992965Sksewell@umich.edu } 1002965Sksewell@umich.edu 1012965Sksewell@umich.edu if(_numSrcRegs > 1) { 1022965Sksewell@umich.edu ss << ", "; 1032965Sksewell@umich.edu printReg(ss, _srcRegIdx[1]); 1042965Sksewell@umich.edu } 1052479SN/A } 1062479SN/A 1072965Sksewell@umich.edu // Should we define a separate inst. class 1082965Sksewell@umich.edu // just for two insts? 1095222Sksewell@umich.edu if(mnemonic == "sll" || mnemonic == "sra"){ 1102492SN/A ccprintf(ss,", %d",SA); 1112131SN/A } 1122088SN/A 1132131SN/A return ss.str(); 1142131SN/A } 1152088SN/A 1162088SN/A}}; 1172088SN/A 118