base.isa revision 5222
110447Snilay@cs.wisc.edu// -*- mode:c++ -*- 210447Snilay@cs.wisc.edu 310447Snilay@cs.wisc.edu// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved 410447Snilay@cs.wisc.edu 510447Snilay@cs.wisc.edu// This software is part of the M5 simulator. 610447Snilay@cs.wisc.edu 710447Snilay@cs.wisc.edu// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 810447Snilay@cs.wisc.edu// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 910447Snilay@cs.wisc.edu// TO THESE TERMS AND CONDITIONS. 1010447Snilay@cs.wisc.edu 1110447Snilay@cs.wisc.edu// Permission is granted to use, copy, create derivative works and 1210447Snilay@cs.wisc.edu// distribute this software and such derivative works for any purpose, 1310447Snilay@cs.wisc.edu// so long as (1) the copyright notice above, this grant of permission, 1410447Snilay@cs.wisc.edu// and the disclaimer below appear in all copies and derivative works 1510447Snilay@cs.wisc.edu// made, (2) the copyright notice above is augmented as appropriate to 1610447Snilay@cs.wisc.edu// reflect the addition of any new copyrightable work in a derivative 1710447Snilay@cs.wisc.edu// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3) 1810447Snilay@cs.wisc.edu// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any 1910447Snilay@cs.wisc.edu// advertising or publicity pertaining to the use or distribution of 2010447Snilay@cs.wisc.edu// this software without specific, written prior authorization. 2110447Snilay@cs.wisc.edu 2210447Snilay@cs.wisc.edu// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND 2310447Snilay@cs.wisc.edu// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 2410447Snilay@cs.wisc.edu// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 2510447Snilay@cs.wisc.edu// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 2610447Snilay@cs.wisc.edu// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 2710447Snilay@cs.wisc.edu// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 2810447Snilay@cs.wisc.edu// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 2910447Snilay@cs.wisc.edu// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 3010447Snilay@cs.wisc.edu// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 3110447Snilay@cs.wisc.edu// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 3210447Snilay@cs.wisc.edu// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 3310447Snilay@cs.wisc.edu// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 3410447Snilay@cs.wisc.edu 3510447Snilay@cs.wisc.edu//Authors: Korey L. Sewell 3610447Snilay@cs.wisc.edu 3710447Snilay@cs.wisc.edu//////////////////////////////////////////////////////////////////// 3810447Snilay@cs.wisc.edu// 3910447Snilay@cs.wisc.edu// Base class for MIPS instructions, and some support functions 4010447Snilay@cs.wisc.edu// 4110447Snilay@cs.wisc.edu 4210447Snilay@cs.wisc.edu//Outputs to decoder.hh 4310447Snilay@cs.wisc.eduoutput header {{ 4410447Snilay@cs.wisc.edu 4510447Snilay@cs.wisc.edu using namespace MipsISA; 4610447Snilay@cs.wisc.edu 4710447Snilay@cs.wisc.edu /** 4810447Snilay@cs.wisc.edu * Base class for all MIPS static instructions. 4910447Snilay@cs.wisc.edu */ 5010447Snilay@cs.wisc.edu class MipsStaticInst : public StaticInst 5110447Snilay@cs.wisc.edu { 5210447Snilay@cs.wisc.edu protected: 5310447Snilay@cs.wisc.edu 5410447Snilay@cs.wisc.edu // Constructor 5510447Snilay@cs.wisc.edu MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) 5610447Snilay@cs.wisc.edu : StaticInst(mnem, _machInst, __opClass) 5710447Snilay@cs.wisc.edu { 5810447Snilay@cs.wisc.edu } 5910447Snilay@cs.wisc.edu 6010447Snilay@cs.wisc.edu /// Print a register name for disassembly given the unique 6110447Snilay@cs.wisc.edu /// dependence tag number (FP or int). 6210447Snilay@cs.wisc.edu void printReg(std::ostream &os, int reg) const; 6310447Snilay@cs.wisc.edu 6410447Snilay@cs.wisc.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 6510447Snilay@cs.wisc.edu }; 6610447Snilay@cs.wisc.edu 6710447Snilay@cs.wisc.edu}}; 6810447Snilay@cs.wisc.edu 6910447Snilay@cs.wisc.edu//Ouputs to decoder.cc 7010447Snilay@cs.wisc.eduoutput decoder {{ 7110447Snilay@cs.wisc.edu 7210447Snilay@cs.wisc.edu void MipsStaticInst::printReg(std::ostream &os, int reg) const 7310447Snilay@cs.wisc.edu { 7410447Snilay@cs.wisc.edu if (reg < FP_Base_DepTag) { 7510447Snilay@cs.wisc.edu ccprintf(os, "r%d", reg); 7610447Snilay@cs.wisc.edu } 7710447Snilay@cs.wisc.edu else { 7810447Snilay@cs.wisc.edu ccprintf(os, "f%d", reg - FP_Base_DepTag); 7910447Snilay@cs.wisc.edu } 8010447Snilay@cs.wisc.edu } 8110447Snilay@cs.wisc.edu 8210447Snilay@cs.wisc.edu std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const 8310447Snilay@cs.wisc.edu { 8410447Snilay@cs.wisc.edu std::stringstream ss; 8510447Snilay@cs.wisc.edu 8610447Snilay@cs.wisc.edu ccprintf(ss, "%-10s ", mnemonic); 87 88 // Need to find standard way to not print 89 // this info. Maybe add bool variable to 90 // class? 91 if (mnemonic != "syscall") { 92 if(_numDestRegs > 0){ 93 printReg(ss, _destRegIdx[0]); 94 } 95 96 if(_numSrcRegs > 0) { 97 ss << ", "; 98 printReg(ss, _srcRegIdx[0]); 99 } 100 101 if(_numSrcRegs > 1) { 102 ss << ", "; 103 printReg(ss, _srcRegIdx[1]); 104 } 105 } 106 107 // Should we define a separate inst. class 108 // just for two insts? 109 if(mnemonic == "sll" || mnemonic == "sra"){ 110 ccprintf(ss,", %d",SA); 111 } 112 113 return ss.str(); 114 } 115 116}}; 117 118