isa.hh revision 6678 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_MIPS_ISA_HH__
32#define __ARCH_MIPS_ISA_HH__
33
34#include <string>
35#include <queue>
36#include <vector>
37
38#include "arch/mips/registers.hh"
39#include "arch/mips/types.hh"
40#include "sim/eventq.hh"
41#include "sim/faults.hh"
42
43class BaseCPU;
44class Checkpoint;
45class EventManager;
46class ThreadContext;
47
48namespace MipsISA
49{
50    class ISA
51    {
52      public:
53        // The MIPS name for this file is CP0 or Coprocessor 0
54        typedef ISA CP0;
55
56      protected:
57        enum BankType {
58            perProcessor,
59            perThreadContext,
60            perVirtProcessor
61        };
62
63        std::vector<std::vector<MiscReg> > miscRegFile;
64        std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
65        std::vector<BankType> bankType;
66
67        BaseCPU *cpu;
68
69      public:
70        ISA();
71        ISA(BaseCPU *_cpu);
72
73        void init();
74
75        void clear(unsigned tid_or_vpn = 0);
76
77        void reset(std::string core_name, ThreadID num_threads,
78                   unsigned num_vpes, BaseCPU *_cpu);
79
80        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
81
82        unsigned getVPENum(ThreadID tid);
83
84        //////////////////////////////////////////////////////////
85        //
86        // READ/WRITE CP0 STATE
87        //
88        //
89        //////////////////////////////////////////////////////////
90        //@TODO: MIPS MT's register view automatically connects
91        //       Status to TCStatus depending on current thread
92        void updateCP0ReadView(int misc_reg, ThreadID tid) { }
93        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
94
95        //template <class TC>
96        MiscReg readMiscReg(int misc_reg,
97                            ThreadContext *tc, ThreadID tid = 0);
98
99        MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
100        void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
101        void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
102                                ThreadID tid = 0);
103
104        //template <class TC>
105        void setMiscReg(int misc_reg, const MiscReg &val,
106                        ThreadContext *tc, ThreadID tid = 0);
107
108        //////////////////////////////////////////////////////////
109        //
110        // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
111        // TO SCHEDULE EVENTS
112        //
113        //////////////////////////////////////////////////////////
114
115        // Flag that is set when CP0 state has been written to.
116        bool cp0Updated;
117
118        // Enumerated List of CP0 Event Types
119        enum CP0EventType {
120            UpdateCP0
121        };
122
123        // Declare A CP0Event Class for scheduling
124        class CP0Event : public Event
125        {
126          protected:
127            ISA::CP0 *cp0;
128            BaseCPU *cpu;
129            CP0EventType cp0EventType;
130            Fault fault;
131
132          public:
133            /** Constructs a CP0 event. */
134            CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type);
135
136            /** Process this event. */
137            virtual void process();
138
139            /** Returns the description of this event. */
140            const char *description() const;
141
142            /** Schedule This Event */
143            void scheduleEvent(int delay);
144
145            /** Unschedule This Event */
146            void unscheduleEvent();
147        };
148
149        // Schedule a CP0 Update Event
150        void scheduleCP0Update(int delay = 0);
151
152        // If any changes have been made, then check the state for changes
153        // and if necessary alert the CPU
154        void updateCPU();
155
156        // Keep a List of CPU Events that need to be deallocated
157        std::queue<CP0Event*> cp0EventRemoveList;
158
159        static std::string miscRegNames[NumMiscRegs];
160
161      public:
162
163        int
164        flattenIntIndex(int reg)
165        {
166            return reg;
167        }
168
169        int
170        flattenFloatIndex(int reg)
171        {
172            return reg;
173        }
174
175        void serialize(EventManager *em, std::ostream &os)
176        {}
177        void unserialize(EventManager *em, Checkpoint *cp,
178                const std::string &section)
179        {}
180    };
181}
182
183#endif
184