isa.hh revision 13615:5cc9363f5ab7 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_MIPS_ISA_HH__
32#define __ARCH_MIPS_ISA_HH__
33
34#include <queue>
35#include <string>
36#include <vector>
37
38#include "arch/mips/registers.hh"
39#include "arch/mips/types.hh"
40#include "cpu/reg_class.hh"
41#include "sim/eventq.hh"
42#include "sim/sim_object.hh"
43
44class BaseCPU;
45class Checkpoint;
46class EventManager;
47struct MipsISAParams;
48class ThreadContext;
49
50namespace MipsISA
51{
52    class ISA : public SimObject
53    {
54      public:
55        // The MIPS name for this file is CP0 or Coprocessor 0
56        typedef ISA CP0;
57
58        typedef MipsISAParams Params;
59
60      protected:
61        // Number of threads and vpes an individual ISA state can handle
62        uint8_t numThreads;
63        uint8_t numVpes;
64
65        enum BankType {
66            perProcessor,
67            perThreadContext,
68            perVirtProcessor
69        };
70
71        std::vector<std::vector<RegVal> > miscRegFile;
72        std::vector<std::vector<RegVal> > miscRegFile_WriteMask;
73        std::vector<BankType> bankType;
74
75      public:
76        void clear();
77
78        void configCP();
79
80        unsigned getVPENum(ThreadID tid) const;
81
82        //////////////////////////////////////////////////////////
83        //
84        // READ/WRITE CP0 STATE
85        //
86        //
87        //////////////////////////////////////////////////////////
88        //@TODO: MIPS MT's register view automatically connects
89        //       Status to TCStatus depending on current thread
90        void updateCP0ReadView(int misc_reg, ThreadID tid) { }
91        RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
92
93        //template <class TC>
94        RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
95
96        RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val);
97        void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0);
98        void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
99
100        //template <class TC>
101        void setMiscReg(int misc_reg, RegVal val,
102                        ThreadContext *tc, ThreadID tid=0);
103
104        //////////////////////////////////////////////////////////
105        //
106        // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
107        // TO SCHEDULE EVENTS
108        //
109        //////////////////////////////////////////////////////////
110
111        // Flag that is set when CP0 state has been written to.
112        bool cp0Updated;
113
114        // Enumerated List of CP0 Event Types
115        enum CP0EventType {
116            UpdateCP0
117        };
118
119        /** Process a CP0 event */
120        void processCP0Event(BaseCPU *cpu, CP0EventType);
121
122        // Schedule a CP0 Update Event
123        void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
124
125        // If any changes have been made, then check the state for changes
126        // and if necessary alert the CPU
127        void updateCPU(BaseCPU *cpu);
128
129        static std::string miscRegNames[NumMiscRegs];
130
131      public:
132        void startup(ThreadContext *tc) {}
133
134        /// Explicitly import the otherwise hidden startup
135        using SimObject::startup;
136
137        const Params *params() const;
138
139        ISA(Params *p);
140
141        RegId flattenRegId(const RegId& regId) const { return regId; }
142
143        int
144        flattenIntIndex(int reg) const
145        {
146            return reg;
147        }
148
149        int
150        flattenFloatIndex(int reg) const
151        {
152            return reg;
153        }
154
155        int
156        flattenVecIndex(int reg) const
157        {
158            return reg;
159        }
160
161        int
162        flattenVecElemIndex(int reg) const
163        {
164            return reg;
165        }
166
167        int
168        flattenVecPredIndex(int reg) const
169        {
170            return reg;
171        }
172
173        // dummy
174        int
175        flattenCCIndex(int reg) const
176        {
177            return reg;
178        }
179
180        int
181        flattenMiscIndex(int reg) const
182        {
183            return reg;
184        }
185
186    };
187}
188
189#endif
190