isa.hh revision 12124:6edbfe40f4e8
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_MIPS_ISA_HH__
32#define __ARCH_MIPS_ISA_HH__
33
34#include <queue>
35#include <string>
36#include <vector>
37
38#include "arch/mips/registers.hh"
39#include "arch/mips/types.hh"
40#include "cpu/reg_class.hh"
41#include "sim/eventq.hh"
42#include "sim/sim_object.hh"
43
44class BaseCPU;
45class Checkpoint;
46class EventManager;
47struct MipsISAParams;
48class ThreadContext;
49
50namespace MipsISA
51{
52    class ISA : public SimObject
53    {
54      public:
55        // The MIPS name for this file is CP0 or Coprocessor 0
56        typedef ISA CP0;
57
58        typedef MipsISAParams Params;
59
60      protected:
61        // Number of threads and vpes an individual ISA state can handle
62        uint8_t numThreads;
63        uint8_t numVpes;
64
65        enum BankType {
66            perProcessor,
67            perThreadContext,
68            perVirtProcessor
69        };
70
71        std::vector<std::vector<MiscReg> > miscRegFile;
72        std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
73        std::vector<BankType> bankType;
74
75      public:
76        void clear();
77
78        void configCP();
79
80        unsigned getVPENum(ThreadID tid) const;
81
82        //////////////////////////////////////////////////////////
83        //
84        // READ/WRITE CP0 STATE
85        //
86        //
87        //////////////////////////////////////////////////////////
88        //@TODO: MIPS MT's register view automatically connects
89        //       Status to TCStatus depending on current thread
90        void updateCP0ReadView(int misc_reg, ThreadID tid) { }
91        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
92
93        //template <class TC>
94        MiscReg readMiscReg(int misc_reg,
95                            ThreadContext *tc, ThreadID tid = 0);
96
97        MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
98        void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
99        void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
100                                ThreadID tid = 0);
101
102        //template <class TC>
103        void setMiscReg(int misc_reg, const MiscReg &val,
104                        ThreadContext *tc, ThreadID tid = 0);
105
106        //////////////////////////////////////////////////////////
107        //
108        // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
109        // TO SCHEDULE EVENTS
110        //
111        //////////////////////////////////////////////////////////
112
113        // Flag that is set when CP0 state has been written to.
114        bool cp0Updated;
115
116        // Enumerated List of CP0 Event Types
117        enum CP0EventType {
118            UpdateCP0
119        };
120
121        /** Process a CP0 event */
122        void processCP0Event(BaseCPU *cpu, CP0EventType);
123
124        // Schedule a CP0 Update Event
125        void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
126
127        // If any changes have been made, then check the state for changes
128        // and if necessary alert the CPU
129        void updateCPU(BaseCPU *cpu);
130
131        static std::string miscRegNames[NumMiscRegs];
132
133      public:
134        void startup(ThreadContext *tc) {}
135
136        /// Explicitly import the otherwise hidden startup
137        using SimObject::startup;
138
139        const Params *params() const;
140
141        ISA(Params *p);
142
143        RegId flattenRegId(const RegId& regId) const { return regId; }
144
145        int
146        flattenIntIndex(int reg) const
147        {
148            return reg;
149        }
150
151        int
152        flattenFloatIndex(int reg) const
153        {
154            return reg;
155        }
156
157        int
158        flattenVecIndex(int reg) const
159        {
160            return reg;
161        }
162
163        int
164        flattenVecElemIndex(int reg) const
165        {
166            return reg;
167        }
168
169        // dummy
170        int
171        flattenCCIndex(int reg) const
172        {
173            return reg;
174        }
175
176        int
177        flattenMiscIndex(int reg) const
178        {
179            return reg;
180        }
181
182    };
183}
184
185#endif
186