isa.hh revision 10474:799c8ee4ecba 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_MIPS_ISA_HH__
32#define __ARCH_MIPS_ISA_HH__
33
34#include <queue>
35#include <string>
36#include <vector>
37
38#include "arch/mips/registers.hh"
39#include "arch/mips/types.hh"
40#include "sim/eventq.hh"
41#include "sim/sim_object.hh"
42
43class BaseCPU;
44class Checkpoint;
45class EventManager;
46struct MipsISAParams;
47class ThreadContext;
48
49namespace MipsISA
50{
51    class ISA : public SimObject
52    {
53      public:
54        // The MIPS name for this file is CP0 or Coprocessor 0
55        typedef ISA CP0;
56
57        typedef MipsISAParams Params;
58
59      protected:
60        // Number of threads and vpes an individual ISA state can handle
61        uint8_t numThreads;
62        uint8_t numVpes;
63
64        enum BankType {
65            perProcessor,
66            perThreadContext,
67            perVirtProcessor
68        };
69
70        std::vector<std::vector<MiscReg> > miscRegFile;
71        std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
72        std::vector<BankType> bankType;
73
74      public:
75        void clear();
76
77        void configCP();
78
79        unsigned getVPENum(ThreadID tid);
80
81        //////////////////////////////////////////////////////////
82        //
83        // READ/WRITE CP0 STATE
84        //
85        //
86        //////////////////////////////////////////////////////////
87        //@TODO: MIPS MT's register view automatically connects
88        //       Status to TCStatus depending on current thread
89        void updateCP0ReadView(int misc_reg, ThreadID tid) { }
90        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
91
92        //template <class TC>
93        MiscReg readMiscReg(int misc_reg,
94                            ThreadContext *tc, ThreadID tid = 0);
95
96        MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
97        void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
98        void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
99                                ThreadID tid = 0);
100
101        //template <class TC>
102        void setMiscReg(int misc_reg, const MiscReg &val,
103                        ThreadContext *tc, ThreadID tid = 0);
104
105        //////////////////////////////////////////////////////////
106        //
107        // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
108        // TO SCHEDULE EVENTS
109        //
110        //////////////////////////////////////////////////////////
111
112        // Flag that is set when CP0 state has been written to.
113        bool cp0Updated;
114
115        // Enumerated List of CP0 Event Types
116        enum CP0EventType {
117            UpdateCP0
118        };
119
120        // Declare A CP0Event Class for scheduling
121        class CP0Event : public Event
122        {
123          protected:
124            ISA::CP0 *cp0;
125            BaseCPU *cpu;
126            CP0EventType cp0EventType;
127            Fault fault;
128
129          public:
130            /** Constructs a CP0 event. */
131            CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type);
132
133            /** Process this event. */
134            virtual void process();
135
136            /** Returns the description of this event. */
137            const char *description() const;
138
139            /** Schedule This Event */
140            void scheduleEvent(Cycles delay);
141
142            /** Unschedule This Event */
143            void unscheduleEvent();
144        };
145
146        // Schedule a CP0 Update Event
147        void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
148
149        // If any changes have been made, then check the state for changes
150        // and if necessary alert the CPU
151        void updateCPU(BaseCPU *cpu);
152
153        // Keep a List of CPU Events that need to be deallocated
154        std::queue<CP0Event*> cp0EventRemoveList;
155
156        static std::string miscRegNames[NumMiscRegs];
157
158      public:
159        void startup(ThreadContext *tc) {}
160
161        /// Explicitly import the otherwise hidden startup
162        using SimObject::startup;
163
164        const Params *params() const;
165
166        ISA(Params *p);
167
168        int
169        flattenIntIndex(int reg) const
170        {
171            return reg;
172        }
173
174        int
175        flattenFloatIndex(int reg) const
176        {
177            return reg;
178        }
179
180        // dummy
181        int
182        flattenCCIndex(int reg) const
183        {
184            return reg;
185        }
186
187        int
188        flattenMiscIndex(int reg) const
189        {
190            return reg;
191        }
192
193    };
194}
195
196#endif
197