isa.hh revision 9384
16313Sgblack@eecs.umich.edu/*
26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan
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46313Sgblack@eecs.umich.edu *
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66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are
76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright
86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
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146313Sgblack@eecs.umich.edu * this software without specific prior written permission.
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276313Sgblack@eecs.umich.edu *
286313Sgblack@eecs.umich.edu * Authors: Gabe Black
296313Sgblack@eecs.umich.edu */
306313Sgblack@eecs.umich.edu
316313Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_ISA_HH__
326313Sgblack@eecs.umich.edu#define __ARCH_MIPS_ISA_HH__
336313Sgblack@eecs.umich.edu
348229Snate@binkert.org#include <queue>
356334Sgblack@eecs.umich.edu#include <string>
366334Sgblack@eecs.umich.edu#include <vector>
376334Sgblack@eecs.umich.edu
386334Sgblack@eecs.umich.edu#include "arch/mips/registers.hh"
396313Sgblack@eecs.umich.edu#include "arch/mips/types.hh"
406334Sgblack@eecs.umich.edu#include "sim/eventq.hh"
417878Sgblack@eecs.umich.edu#include "sim/fault_fwd.hh"
429384SAndreas.Sandberg@arm.com#include "sim/sim_object.hh"
436313Sgblack@eecs.umich.edu
446334Sgblack@eecs.umich.educlass BaseCPU;
456313Sgblack@eecs.umich.educlass Checkpoint;
466313Sgblack@eecs.umich.educlass EventManager;
479384SAndreas.Sandberg@arm.comstruct MipsISAParams;
486334Sgblack@eecs.umich.educlass ThreadContext;
496313Sgblack@eecs.umich.edu
506313Sgblack@eecs.umich.edunamespace MipsISA
516313Sgblack@eecs.umich.edu{
529384SAndreas.Sandberg@arm.com    class ISA : public SimObject
536313Sgblack@eecs.umich.edu    {
546334Sgblack@eecs.umich.edu      public:
556334Sgblack@eecs.umich.edu        // The MIPS name for this file is CP0 or Coprocessor 0
566334Sgblack@eecs.umich.edu        typedef ISA CP0;
576334Sgblack@eecs.umich.edu
589384SAndreas.Sandberg@arm.com        typedef MipsISAParams Params;
599384SAndreas.Sandberg@arm.com
606313Sgblack@eecs.umich.edu      protected:
618181Sksewell@umich.edu        // Number of threads and vpes an individual ISA state can handle
628181Sksewell@umich.edu        uint8_t numThreads;
638181Sksewell@umich.edu        uint8_t numVpes;
648181Sksewell@umich.edu
656334Sgblack@eecs.umich.edu        enum BankType {
666334Sgblack@eecs.umich.edu            perProcessor,
676334Sgblack@eecs.umich.edu            perThreadContext,
686334Sgblack@eecs.umich.edu            perVirtProcessor
696334Sgblack@eecs.umich.edu        };
706334Sgblack@eecs.umich.edu
716334Sgblack@eecs.umich.edu        std::vector<std::vector<MiscReg> > miscRegFile;
726334Sgblack@eecs.umich.edu        std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
736334Sgblack@eecs.umich.edu        std::vector<BankType> bankType;
746334Sgblack@eecs.umich.edu
756313Sgblack@eecs.umich.edu      public:
768181Sksewell@umich.edu        void clear();
776334Sgblack@eecs.umich.edu
788181Sksewell@umich.edu        void configCP();
796334Sgblack@eecs.umich.edu
806334Sgblack@eecs.umich.edu        unsigned getVPENum(ThreadID tid);
816334Sgblack@eecs.umich.edu
826334Sgblack@eecs.umich.edu        //////////////////////////////////////////////////////////
836334Sgblack@eecs.umich.edu        //
846334Sgblack@eecs.umich.edu        // READ/WRITE CP0 STATE
856334Sgblack@eecs.umich.edu        //
866334Sgblack@eecs.umich.edu        //
876334Sgblack@eecs.umich.edu        //////////////////////////////////////////////////////////
886334Sgblack@eecs.umich.edu        //@TODO: MIPS MT's register view automatically connects
896334Sgblack@eecs.umich.edu        //       Status to TCStatus depending on current thread
906334Sgblack@eecs.umich.edu        void updateCP0ReadView(int misc_reg, ThreadID tid) { }
916334Sgblack@eecs.umich.edu        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
926334Sgblack@eecs.umich.edu
936334Sgblack@eecs.umich.edu        //template <class TC>
946334Sgblack@eecs.umich.edu        MiscReg readMiscReg(int misc_reg,
956334Sgblack@eecs.umich.edu                            ThreadContext *tc, ThreadID tid = 0);
966334Sgblack@eecs.umich.edu
976334Sgblack@eecs.umich.edu        MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
986334Sgblack@eecs.umich.edu        void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
996334Sgblack@eecs.umich.edu        void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
1006334Sgblack@eecs.umich.edu                                ThreadID tid = 0);
1016334Sgblack@eecs.umich.edu
1026334Sgblack@eecs.umich.edu        //template <class TC>
1036334Sgblack@eecs.umich.edu        void setMiscReg(int misc_reg, const MiscReg &val,
1046334Sgblack@eecs.umich.edu                        ThreadContext *tc, ThreadID tid = 0);
1056334Sgblack@eecs.umich.edu
1066334Sgblack@eecs.umich.edu        //////////////////////////////////////////////////////////
1076334Sgblack@eecs.umich.edu        //
1086334Sgblack@eecs.umich.edu        // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
1096334Sgblack@eecs.umich.edu        // TO SCHEDULE EVENTS
1106334Sgblack@eecs.umich.edu        //
1116334Sgblack@eecs.umich.edu        //////////////////////////////////////////////////////////
1126334Sgblack@eecs.umich.edu
1136334Sgblack@eecs.umich.edu        // Flag that is set when CP0 state has been written to.
1146334Sgblack@eecs.umich.edu        bool cp0Updated;
1156334Sgblack@eecs.umich.edu
1166334Sgblack@eecs.umich.edu        // Enumerated List of CP0 Event Types
1176334Sgblack@eecs.umich.edu        enum CP0EventType {
1186334Sgblack@eecs.umich.edu            UpdateCP0
1196334Sgblack@eecs.umich.edu        };
1206334Sgblack@eecs.umich.edu
1216334Sgblack@eecs.umich.edu        // Declare A CP0Event Class for scheduling
1226334Sgblack@eecs.umich.edu        class CP0Event : public Event
1236313Sgblack@eecs.umich.edu        {
1246334Sgblack@eecs.umich.edu          protected:
1256334Sgblack@eecs.umich.edu            ISA::CP0 *cp0;
1266334Sgblack@eecs.umich.edu            BaseCPU *cpu;
1276334Sgblack@eecs.umich.edu            CP0EventType cp0EventType;
1286334Sgblack@eecs.umich.edu            Fault fault;
1296313Sgblack@eecs.umich.edu
1306334Sgblack@eecs.umich.edu          public:
1316334Sgblack@eecs.umich.edu            /** Constructs a CP0 event. */
1326334Sgblack@eecs.umich.edu            CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type);
1336313Sgblack@eecs.umich.edu
1346334Sgblack@eecs.umich.edu            /** Process this event. */
1356334Sgblack@eecs.umich.edu            virtual void process();
1366313Sgblack@eecs.umich.edu
1376334Sgblack@eecs.umich.edu            /** Returns the description of this event. */
1386334Sgblack@eecs.umich.edu            const char *description() const;
1396334Sgblack@eecs.umich.edu
1406334Sgblack@eecs.umich.edu            /** Schedule This Event */
1419180Sandreas.hansson@arm.com            void scheduleEvent(Cycles delay);
1426334Sgblack@eecs.umich.edu
1436334Sgblack@eecs.umich.edu            /** Unschedule This Event */
1446334Sgblack@eecs.umich.edu            void unscheduleEvent();
1456334Sgblack@eecs.umich.edu        };
1466334Sgblack@eecs.umich.edu
1476334Sgblack@eecs.umich.edu        // Schedule a CP0 Update Event
1489180Sandreas.hansson@arm.com        void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
1496334Sgblack@eecs.umich.edu
1506334Sgblack@eecs.umich.edu        // If any changes have been made, then check the state for changes
1516334Sgblack@eecs.umich.edu        // and if necessary alert the CPU
1526806Sgblack@eecs.umich.edu        void updateCPU(BaseCPU *cpu);
1536334Sgblack@eecs.umich.edu
1546334Sgblack@eecs.umich.edu        // Keep a List of CPU Events that need to be deallocated
1556334Sgblack@eecs.umich.edu        std::queue<CP0Event*> cp0EventRemoveList;
1566334Sgblack@eecs.umich.edu
1576334Sgblack@eecs.umich.edu        static std::string miscRegNames[NumMiscRegs];
1586334Sgblack@eecs.umich.edu
1596334Sgblack@eecs.umich.edu      public:
1609384SAndreas.Sandberg@arm.com        const Params *params() const;
1619384SAndreas.Sandberg@arm.com
1629384SAndreas.Sandberg@arm.com        ISA(Params *p);
1636313Sgblack@eecs.umich.edu
1646313Sgblack@eecs.umich.edu        int
1656313Sgblack@eecs.umich.edu        flattenIntIndex(int reg)
1666313Sgblack@eecs.umich.edu        {
1676313Sgblack@eecs.umich.edu            return reg;
1686313Sgblack@eecs.umich.edu        }
1696313Sgblack@eecs.umich.edu
1706313Sgblack@eecs.umich.edu        int
1716313Sgblack@eecs.umich.edu        flattenFloatIndex(int reg)
1726313Sgblack@eecs.umich.edu        {
1736313Sgblack@eecs.umich.edu            return reg;
1746313Sgblack@eecs.umich.edu        }
1756313Sgblack@eecs.umich.edu
1766678Sgblack@eecs.umich.edu        void serialize(EventManager *em, std::ostream &os)
1776678Sgblack@eecs.umich.edu        {}
1786678Sgblack@eecs.umich.edu        void unserialize(EventManager *em, Checkpoint *cp,
1796678Sgblack@eecs.umich.edu                const std::string &section)
1806678Sgblack@eecs.umich.edu        {}
1816313Sgblack@eecs.umich.edu    };
1826313Sgblack@eecs.umich.edu}
1836313Sgblack@eecs.umich.edu
1846313Sgblack@eecs.umich.edu#endif
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