isa.hh revision 8181
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 316313Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_ISA_HH__ 326313Sgblack@eecs.umich.edu#define __ARCH_MIPS_ISA_HH__ 336313Sgblack@eecs.umich.edu 346334Sgblack@eecs.umich.edu#include <string> 356334Sgblack@eecs.umich.edu#include <queue> 366334Sgblack@eecs.umich.edu#include <vector> 376334Sgblack@eecs.umich.edu 386334Sgblack@eecs.umich.edu#include "arch/mips/registers.hh" 396313Sgblack@eecs.umich.edu#include "arch/mips/types.hh" 406334Sgblack@eecs.umich.edu#include "sim/eventq.hh" 417878Sgblack@eecs.umich.edu#include "sim/fault_fwd.hh" 426313Sgblack@eecs.umich.edu 436334Sgblack@eecs.umich.educlass BaseCPU; 446313Sgblack@eecs.umich.educlass Checkpoint; 456313Sgblack@eecs.umich.educlass EventManager; 466334Sgblack@eecs.umich.educlass ThreadContext; 476313Sgblack@eecs.umich.edu 486313Sgblack@eecs.umich.edunamespace MipsISA 496313Sgblack@eecs.umich.edu{ 506313Sgblack@eecs.umich.edu class ISA 516313Sgblack@eecs.umich.edu { 526334Sgblack@eecs.umich.edu public: 536334Sgblack@eecs.umich.edu // The MIPS name for this file is CP0 or Coprocessor 0 546334Sgblack@eecs.umich.edu typedef ISA CP0; 556334Sgblack@eecs.umich.edu 566313Sgblack@eecs.umich.edu protected: 578181Sksewell@umich.edu // Number of threads and vpes an individual ISA state can handle 588181Sksewell@umich.edu uint8_t numThreads; 598181Sksewell@umich.edu uint8_t numVpes; 608181Sksewell@umich.edu 616334Sgblack@eecs.umich.edu enum BankType { 626334Sgblack@eecs.umich.edu perProcessor, 636334Sgblack@eecs.umich.edu perThreadContext, 646334Sgblack@eecs.umich.edu perVirtProcessor 656334Sgblack@eecs.umich.edu }; 666334Sgblack@eecs.umich.edu 676334Sgblack@eecs.umich.edu std::vector<std::vector<MiscReg> > miscRegFile; 686334Sgblack@eecs.umich.edu std::vector<std::vector<MiscReg> > miscRegFile_WriteMask; 696334Sgblack@eecs.umich.edu std::vector<BankType> bankType; 706334Sgblack@eecs.umich.edu 716313Sgblack@eecs.umich.edu public: 728181Sksewell@umich.edu ISA(uint8_t num_threads = 1, uint8_t num_vpes = 1); 736313Sgblack@eecs.umich.edu 748181Sksewell@umich.edu void clear(); 756334Sgblack@eecs.umich.edu 768181Sksewell@umich.edu void configCP(); 776334Sgblack@eecs.umich.edu 786334Sgblack@eecs.umich.edu unsigned getVPENum(ThreadID tid); 796334Sgblack@eecs.umich.edu 806334Sgblack@eecs.umich.edu ////////////////////////////////////////////////////////// 816334Sgblack@eecs.umich.edu // 826334Sgblack@eecs.umich.edu // READ/WRITE CP0 STATE 836334Sgblack@eecs.umich.edu // 846334Sgblack@eecs.umich.edu // 856334Sgblack@eecs.umich.edu ////////////////////////////////////////////////////////// 866334Sgblack@eecs.umich.edu //@TODO: MIPS MT's register view automatically connects 876334Sgblack@eecs.umich.edu // Status to TCStatus depending on current thread 886334Sgblack@eecs.umich.edu void updateCP0ReadView(int misc_reg, ThreadID tid) { } 896334Sgblack@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); 906334Sgblack@eecs.umich.edu 916334Sgblack@eecs.umich.edu //template <class TC> 926334Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg, 936334Sgblack@eecs.umich.edu ThreadContext *tc, ThreadID tid = 0); 946334Sgblack@eecs.umich.edu 956334Sgblack@eecs.umich.edu MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val); 966334Sgblack@eecs.umich.edu void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0); 976334Sgblack@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val, 986334Sgblack@eecs.umich.edu ThreadID tid = 0); 996334Sgblack@eecs.umich.edu 1006334Sgblack@eecs.umich.edu //template <class TC> 1016334Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val, 1026334Sgblack@eecs.umich.edu ThreadContext *tc, ThreadID tid = 0); 1036334Sgblack@eecs.umich.edu 1046334Sgblack@eecs.umich.edu ////////////////////////////////////////////////////////// 1056334Sgblack@eecs.umich.edu // 1066334Sgblack@eecs.umich.edu // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0) 1076334Sgblack@eecs.umich.edu // TO SCHEDULE EVENTS 1086334Sgblack@eecs.umich.edu // 1096334Sgblack@eecs.umich.edu ////////////////////////////////////////////////////////// 1106334Sgblack@eecs.umich.edu 1116334Sgblack@eecs.umich.edu // Flag that is set when CP0 state has been written to. 1126334Sgblack@eecs.umich.edu bool cp0Updated; 1136334Sgblack@eecs.umich.edu 1146334Sgblack@eecs.umich.edu // Enumerated List of CP0 Event Types 1156334Sgblack@eecs.umich.edu enum CP0EventType { 1166334Sgblack@eecs.umich.edu UpdateCP0 1176334Sgblack@eecs.umich.edu }; 1186334Sgblack@eecs.umich.edu 1196334Sgblack@eecs.umich.edu // Declare A CP0Event Class for scheduling 1206334Sgblack@eecs.umich.edu class CP0Event : public Event 1216313Sgblack@eecs.umich.edu { 1226334Sgblack@eecs.umich.edu protected: 1236334Sgblack@eecs.umich.edu ISA::CP0 *cp0; 1246334Sgblack@eecs.umich.edu BaseCPU *cpu; 1256334Sgblack@eecs.umich.edu CP0EventType cp0EventType; 1266334Sgblack@eecs.umich.edu Fault fault; 1276313Sgblack@eecs.umich.edu 1286334Sgblack@eecs.umich.edu public: 1296334Sgblack@eecs.umich.edu /** Constructs a CP0 event. */ 1306334Sgblack@eecs.umich.edu CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type); 1316313Sgblack@eecs.umich.edu 1326334Sgblack@eecs.umich.edu /** Process this event. */ 1336334Sgblack@eecs.umich.edu virtual void process(); 1346313Sgblack@eecs.umich.edu 1356334Sgblack@eecs.umich.edu /** Returns the description of this event. */ 1366334Sgblack@eecs.umich.edu const char *description() const; 1376334Sgblack@eecs.umich.edu 1386334Sgblack@eecs.umich.edu /** Schedule This Event */ 1396334Sgblack@eecs.umich.edu void scheduleEvent(int delay); 1406334Sgblack@eecs.umich.edu 1416334Sgblack@eecs.umich.edu /** Unschedule This Event */ 1426334Sgblack@eecs.umich.edu void unscheduleEvent(); 1436334Sgblack@eecs.umich.edu }; 1446334Sgblack@eecs.umich.edu 1456334Sgblack@eecs.umich.edu // Schedule a CP0 Update Event 1466806Sgblack@eecs.umich.edu void scheduleCP0Update(BaseCPU *cpu, int delay = 0); 1476334Sgblack@eecs.umich.edu 1486334Sgblack@eecs.umich.edu // If any changes have been made, then check the state for changes 1496334Sgblack@eecs.umich.edu // and if necessary alert the CPU 1506806Sgblack@eecs.umich.edu void updateCPU(BaseCPU *cpu); 1516334Sgblack@eecs.umich.edu 1526334Sgblack@eecs.umich.edu // Keep a List of CPU Events that need to be deallocated 1536334Sgblack@eecs.umich.edu std::queue<CP0Event*> cp0EventRemoveList; 1546334Sgblack@eecs.umich.edu 1556334Sgblack@eecs.umich.edu static std::string miscRegNames[NumMiscRegs]; 1566334Sgblack@eecs.umich.edu 1576334Sgblack@eecs.umich.edu public: 1586313Sgblack@eecs.umich.edu 1596313Sgblack@eecs.umich.edu int 1606313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 1616313Sgblack@eecs.umich.edu { 1626313Sgblack@eecs.umich.edu return reg; 1636313Sgblack@eecs.umich.edu } 1646313Sgblack@eecs.umich.edu 1656313Sgblack@eecs.umich.edu int 1666313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 1676313Sgblack@eecs.umich.edu { 1686313Sgblack@eecs.umich.edu return reg; 1696313Sgblack@eecs.umich.edu } 1706313Sgblack@eecs.umich.edu 1716678Sgblack@eecs.umich.edu void serialize(EventManager *em, std::ostream &os) 1726678Sgblack@eecs.umich.edu {} 1736678Sgblack@eecs.umich.edu void unserialize(EventManager *em, Checkpoint *cp, 1746678Sgblack@eecs.umich.edu const std::string §ion) 1756678Sgblack@eecs.umich.edu {} 1766313Sgblack@eecs.umich.edu }; 1776313Sgblack@eecs.umich.edu} 1786313Sgblack@eecs.umich.edu 1796313Sgblack@eecs.umich.edu#endif 180