isa.cc revision 7823:dac01f14f20f
16019Shines@cs.fsu.edu/*
211929SMatteo.Andreozzi@arm.com * Copyright (c) 2009 The Regents of The University of Michigan
37189Sgblack@eecs.umich.edu * All rights reserved.
47189Sgblack@eecs.umich.edu *
57189Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without
67189Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are
77189Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright
87189Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
97189Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
107189Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
117189Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution;
127189Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its
137189Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
146019Shines@cs.fsu.edu * this software without specific prior written permission.
156019Shines@cs.fsu.edu *
166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276019Shines@cs.fsu.edu *
286019Shines@cs.fsu.edu * Authors: Gabe Black
296019Shines@cs.fsu.edu */
306019Shines@cs.fsu.edu
316019Shines@cs.fsu.edu#include "arch/mips/isa.hh"
326019Shines@cs.fsu.edu#include "arch/mips/mt_constants.hh"
336019Shines@cs.fsu.edu#include "arch/mips/mt.hh"
346019Shines@cs.fsu.edu#include "arch/mips/pra_constants.hh"
356019Shines@cs.fsu.edu#include "base/bitfield.hh"
366019Shines@cs.fsu.edu#include "cpu/base.hh"
376019Shines@cs.fsu.edu#include "cpu/thread_context.hh"
386019Shines@cs.fsu.edu
396019Shines@cs.fsu.edunamespace MipsISA
406019Shines@cs.fsu.edu{
416735Sgblack@eecs.umich.edu
426735Sgblack@eecs.umich.edustd::string
4310037SARM gem5 DevelopersISA::miscRegNames[NumMiscRegs] =
4410037SARM gem5 Developers{
456019Shines@cs.fsu.edu    "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
466019Shines@cs.fsu.edu    "Random", "VPEControl", "VPEConf0", "VPEConf1",
476019Shines@cs.fsu.edu        "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
486019Shines@cs.fsu.edu    "EntryLo0", "TCStatus", "TCBind", "TCRestart",
496019Shines@cs.fsu.edu        "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
507362Sgblack@eecs.umich.edu    "EntryLo1", "", "", "", "", "", "", "",
5110037SARM gem5 Developers    "Context", "ContextConfig", "", "", "", "", "", "",
526735Sgblack@eecs.umich.edu    "PageMask", "PageGrain", "", "", "", "", "", "",
538229Snate@binkert.org    "Wired", "SRSConf0", "SRCConf1", "SRSConf2",
546019Shines@cs.fsu.edu        "SRSConf3", "SRSConf4", "", "",
558782Sgblack@eecs.umich.edu    "HWREna", "", "", "", "", "", "", "",
566019Shines@cs.fsu.edu    "BadVAddr", "", "", "", "", "", "", "",
576019Shines@cs.fsu.edu    "Count", "", "", "", "", "", "", "",
586019Shines@cs.fsu.edu    "EntryHi", "", "", "", "", "", "", "",
596019Shines@cs.fsu.edu    "Compare", "", "", "", "", "", "", "",
606019Shines@cs.fsu.edu    "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
6111294Sandreas.hansson@arm.com    "Cause", "", "", "", "", "", "", "",
626019Shines@cs.fsu.edu    "EPC", "", "", "", "", "", "", "",
637362Sgblack@eecs.umich.edu    "PRId", "EBase", "", "", "", "", "", "",
646019Shines@cs.fsu.edu    "Config", "Config1", "Config2", "Config3", "", "", "", "",
656019Shines@cs.fsu.edu    "LLAddr", "", "", "", "", "", "", "",
6610037SARM gem5 Developers    "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
6710037SARM gem5 Developers        "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
6810037SARM gem5 Developers    "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
6910037SARM gem5 Developers        "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
7010037SARM gem5 Developers    "XCContext64", "", "", "", "", "", "", "",
7110037SARM gem5 Developers    "", "", "", "", "", "", "", "",
7210037SARM gem5 Developers    "", "", "", "", "", "", "", "",
7310037SARM gem5 Developers    "Debug", "TraceControl1", "TraceControl2", "UserTraceData",
7410037SARM gem5 Developers        "TraceBPC", "", "", "",
7510037SARM gem5 Developers    "DEPC", "", "", "", "", "", "", "",
766735Sgblack@eecs.umich.edu    "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
7710037SARM gem5 Developers        "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
786735Sgblack@eecs.umich.edu    "ErrCtl", "", "", "", "", "", "", "",
796019Shines@cs.fsu.edu    "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
8010037SARM gem5 Developers    "TagLo0", "DataLo1", "TagLo2", "DataLo3",
8110037SARM gem5 Developers        "TagLo4", "DataLo5", "TagLo6", "DataLo7",
8210037SARM gem5 Developers    "TagHi0", "DataHi1", "TagHi2", "DataHi3",
8310037SARM gem5 Developers        "TagHi4", "DataHi5", "TagHi6", "DataHi7",
8410037SARM gem5 Developers    "ErrorEPC", "", "", "", "", "", "", "",
857362Sgblack@eecs.umich.edu    "DESAVE", "", "", "", "", "", "", "",
8610037SARM gem5 Developers    "LLFlag"
8710037SARM gem5 Developers};
8810037SARM gem5 Developers
8910037SARM gem5 DevelopersISA::ISA()
9010037SARM gem5 Developers{
9110037SARM gem5 Developers    init();
9210037SARM gem5 Developers}
9310037SARM gem5 Developers
9410037SARM gem5 Developersvoid
9510037SARM gem5 DevelopersISA::init()
9610037SARM gem5 Developers{
9710037SARM gem5 Developers    miscRegFile.resize(NumMiscRegs);
9810037SARM gem5 Developers    bankType.resize(NumMiscRegs);
9910037SARM gem5 Developers
10010037SARM gem5 Developers    for (int i=0; i < NumMiscRegs; i++) {
1017611SGene.Wu@arm.com        miscRegFile[i].resize(1);
10210037SARM gem5 Developers        bankType[i] = perProcessor;
10310037SARM gem5 Developers    }
10410037SARM gem5 Developers
10510037SARM gem5 Developers    miscRegFile_WriteMask.resize(NumMiscRegs);
10610037SARM gem5 Developers
10710037SARM gem5 Developers    for (int i = 0; i < NumMiscRegs; i++) {
10810037SARM gem5 Developers        miscRegFile_WriteMask[i].push_back(0);
10910037SARM gem5 Developers    }
11010037SARM gem5 Developers    clear(0);
11110037SARM gem5 Developers}
11210037SARM gem5 Developers
11310037SARM gem5 Developersvoid
11410037SARM gem5 DevelopersISA::clear(unsigned tid_or_vpn)
11510037SARM gem5 Developers{
11610037SARM gem5 Developers    for(int i = 0; i < NumMiscRegs; i++) {
11710037SARM gem5 Developers        miscRegFile[i][tid_or_vpn] = 0;
11810037SARM gem5 Developers        miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1);
11910037SARM gem5 Developers    }
12010037SARM gem5 Developers}
12110037SARM gem5 Developers
12210037SARM gem5 Developersvoid
12310037SARM gem5 DevelopersISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
12410037SARM gem5 Developers{
12510037SARM gem5 Developers    // Initialize all Per-VPE regs
12610037SARM gem5 Developers    uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
12710037SARM gem5 Developers                                MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
12810037SARM gem5 Developers                                MISCREG_YQMASK,
12910037SARM gem5 Developers                                MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK,
13010037SARM gem5 Developers                                MISCREG_VPE_OPT, MISCREG_SRS_CONF0,
13110037SARM gem5 Developers                                MISCREG_SRS_CONF1, MISCREG_SRS_CONF2,
13210037SARM gem5 Developers                                MISCREG_SRS_CONF3, MISCREG_SRS_CONF4,
13310037SARM gem5 Developers                                MISCREG_EBASE
13410037SARM gem5 Developers                              };
13510037SARM gem5 Developers    uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
13610037SARM gem5 Developers    for (int i = 0; i < num_vpe_regs; i++) {
13710037SARM gem5 Developers        if (num_vpes > 1) {
13810037SARM gem5 Developers            miscRegFile[per_vpe_regs[i]].resize(num_vpes);
1397362Sgblack@eecs.umich.edu        }
1407362Sgblack@eecs.umich.edu        bankType[per_vpe_regs[i]] = perVirtProcessor;
1416735Sgblack@eecs.umich.edu    }
1426735Sgblack@eecs.umich.edu
1436735Sgblack@eecs.umich.edu    // Initialize all Per-TC regs
14410037SARM gem5 Developers    uint32_t per_tc_regs[] = { MISCREG_STATUS,
1456735Sgblack@eecs.umich.edu                               MISCREG_TC_STATUS, MISCREG_TC_BIND,
14610037SARM gem5 Developers                               MISCREG_TC_RESTART, MISCREG_TC_HALT,
14710037SARM gem5 Developers                               MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE,
14810037SARM gem5 Developers                               MISCREG_TC_SCHEFBACK,
14910037SARM gem5 Developers                               MISCREG_DEBUG, MISCREG_LLADDR
15010037SARM gem5 Developers                             };
15110037SARM gem5 Developers    uint32_t num_tc_regs = sizeof(per_tc_regs) /  4;
15210037SARM gem5 Developers
1536735Sgblack@eecs.umich.edu    for (int i = 0; i < num_tc_regs; i++) {
15410037SARM gem5 Developers        miscRegFile[per_tc_regs[i]].resize(num_threads);
1556735Sgblack@eecs.umich.edu        bankType[per_tc_regs[i]] = perThreadContext;
1566735Sgblack@eecs.umich.edu    }
15710037SARM gem5 Developers
15810037SARM gem5 Developers
15910037SARM gem5 Developers    if (num_vpes > 1) {
16010037SARM gem5 Developers        for (int i=1; i < num_vpes; i++) {
16110037SARM gem5 Developers            clear(i);
16210037SARM gem5 Developers        }
16310037SARM gem5 Developers    }
1646735Sgblack@eecs.umich.edu
1656735Sgblack@eecs.umich.edu}
16610037SARM gem5 Developers
16710037SARM gem5 Developers//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
16810037SARM gem5 Developersvoid
16910037SARM gem5 DevelopersISA::reset(std::string core_name, ThreadID num_threads,
17010037SARM gem5 Developers                   unsigned num_vpes, BaseCPU *cpu)
1716735Sgblack@eecs.umich.edu{
1726735Sgblack@eecs.umich.edu    DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
1736735Sgblack@eecs.umich.edu            num_threads, num_vpes);
17410037SARM gem5 Developers
17510537Sandreas.hansson@arm.com    MipsISA::CoreSpecific &cp = cpu->coreParams;
17610537Sandreas.hansson@arm.com
17710037SARM gem5 Developers    // Do Default CP0 initialization HERE
17810037SARM gem5 Developers
17910037SARM gem5 Developers    // Do Initialization for MT cores here (eventually use
18010037SARM gem5 Developers    // core_name parameter to toggle this initialization)
18110037SARM gem5 Developers    // ===================================================
18210037SARM gem5 Developers    DPRINTF(MipsPRA, "Initializing CP0 State.... ");
18310037SARM gem5 Developers
18410037SARM gem5 Developers    PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
18510417Sandreas.hansson@arm.com    procId.coOp = cp.CP0_PRId_CompanyOptions;
18612176Sandreas.sandberg@arm.com    procId.coId = cp.CP0_PRId_CompanyID;
18710417Sandreas.hansson@arm.com    procId.procId = cp.CP0_PRId_ProcessorID;
18810417Sandreas.hansson@arm.com    procId.rev = cp.CP0_PRId_Revision;
18910037SARM gem5 Developers    setMiscRegNoEffect(MISCREG_PRID, procId);
1906735Sgblack@eecs.umich.edu
19110037SARM gem5 Developers    // Now, create Write Mask for ProcID register
19210037SARM gem5 Developers    MiscReg procIDMask = 0; // Read-Only register
1936735Sgblack@eecs.umich.edu    replaceBits(procIDMask, 0, 32, 0);
19410037SARM gem5 Developers    setRegMask(MISCREG_PRID, procIDMask);
19510037SARM gem5 Developers
19610037SARM gem5 Developers    // Config
19710037SARM gem5 Developers    ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
19810037SARM gem5 Developers    cfg.be = cp.CP0_Config_BE;
19910037SARM gem5 Developers    cfg.at = cp.CP0_Config_AT;
20010037SARM gem5 Developers    cfg.ar = cp.CP0_Config_AR;
20110037SARM gem5 Developers    cfg.mt = cp.CP0_Config_MT;
20210037SARM gem5 Developers    cfg.vi = cp.CP0_Config_VI;
20310037SARM gem5 Developers    cfg.m = 1;
20410037SARM gem5 Developers    setMiscRegNoEffect(MISCREG_CONFIG, cfg);
20510037SARM gem5 Developers    // Now, create Write Mask for Config register
20610037SARM gem5 Developers    MiscReg cfg_Mask = 0x7FFF0007;
2076019Shines@cs.fsu.edu    replaceBits(cfg_Mask, 0, 32, 0);
2086019Shines@cs.fsu.edu    setRegMask(MISCREG_CONFIG, cfg_Mask);
2096735Sgblack@eecs.umich.edu
2107362Sgblack@eecs.umich.edu    // Config1
2116019Shines@cs.fsu.edu    Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
2126735Sgblack@eecs.umich.edu    cfg1.mmuSize = cp.CP0_Config1_MMU;
2136735Sgblack@eecs.umich.edu    cfg1.is = cp.CP0_Config1_IS;
2146735Sgblack@eecs.umich.edu    cfg1.il = cp.CP0_Config1_IL;
2156019Shines@cs.fsu.edu    cfg1.ia = cp.CP0_Config1_IA;
21610037SARM gem5 Developers    cfg1.ds = cp.CP0_Config1_DS;
21710037SARM gem5 Developers    cfg1.dl = cp.CP0_Config1_DL;
21812176Sandreas.sandberg@arm.com    cfg1.da = cp.CP0_Config1_DA;
21912176Sandreas.sandberg@arm.com    cfg1.fp = cp.CP0_Config1_FP;
22012176Sandreas.sandberg@arm.com    cfg1.ep = cp.CP0_Config1_EP;
22110037SARM gem5 Developers    cfg1.wr = cp.CP0_Config1_WR;
22212176Sandreas.sandberg@arm.com    cfg1.md = cp.CP0_Config1_MD;
22310037SARM gem5 Developers    cfg1.c2 = cp.CP0_Config1_C2;
22410037SARM gem5 Developers    cfg1.pc = cp.CP0_Config1_PC;
22510037SARM gem5 Developers    cfg1.m = cp.CP0_Config1_M;
22610037SARM gem5 Developers    setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
22710037SARM gem5 Developers    // Now, create Write Mask for Config register
22810037SARM gem5 Developers    MiscReg cfg1_Mask = 0; // Read Only Register
22910037SARM gem5 Developers    replaceBits(cfg1_Mask, 0, 32, 0);
23010037SARM gem5 Developers    setRegMask(MISCREG_CONFIG1, cfg1_Mask);
23110037SARM gem5 Developers
23210037SARM gem5 Developers    // Config2
23310037SARM gem5 Developers    Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
23412176Sandreas.sandberg@arm.com    cfg2.tu = cp.CP0_Config2_TU;
23512176Sandreas.sandberg@arm.com    cfg2.ts = cp.CP0_Config2_TS;
23612176Sandreas.sandberg@arm.com    cfg2.tl = cp.CP0_Config2_TL;
23712176Sandreas.sandberg@arm.com    cfg2.ta = cp.CP0_Config2_TA;
23812176Sandreas.sandberg@arm.com    cfg2.su = cp.CP0_Config2_SU;
23912176Sandreas.sandberg@arm.com    cfg2.ss = cp.CP0_Config2_SS;
24012176Sandreas.sandberg@arm.com    cfg2.sl = cp.CP0_Config2_SL;
24112176Sandreas.sandberg@arm.com    cfg2.sa = cp.CP0_Config2_SA;
24212176Sandreas.sandberg@arm.com    cfg2.m = cp.CP0_Config2_M;
24312176Sandreas.sandberg@arm.com    setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
24412176Sandreas.sandberg@arm.com    // Now, create Write Mask for Config register
24512176Sandreas.sandberg@arm.com    MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
24612176Sandreas.sandberg@arm.com    replaceBits(cfg2_Mask, 0, 32, 0);
24712176Sandreas.sandberg@arm.com    setRegMask(MISCREG_CONFIG2, cfg2_Mask);
24812176Sandreas.sandberg@arm.com
24912176Sandreas.sandberg@arm.com    // Config3
25012176Sandreas.sandberg@arm.com    Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
25112176Sandreas.sandberg@arm.com    cfg3.dspp = cp.CP0_Config3_DSPP;
2526019Shines@cs.fsu.edu    cfg3.lpa = cp.CP0_Config3_LPA;
2536019Shines@cs.fsu.edu    cfg3.veic = cp.CP0_Config3_VEIC;
2547400SAli.Saidi@ARM.com    cfg3.vint = cp.CP0_Config3_VInt;
2557400SAli.Saidi@ARM.com    cfg3.sp = cp.CP0_Config3_SP;
2567400SAli.Saidi@ARM.com    cfg3.mt = cp.CP0_Config3_MT;
25710417Sandreas.hansson@arm.com    cfg3.sm = cp.CP0_Config3_SM;
25812176Sandreas.sandberg@arm.com    cfg3.tl = cp.CP0_Config3_TL;
2597400SAli.Saidi@ARM.com    setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
2607189Sgblack@eecs.umich.edu    // Now, create Write Mask for Config register
2617362Sgblack@eecs.umich.edu    MiscReg cfg3_Mask = 0; // Read Only Register
2627189Sgblack@eecs.umich.edu    replaceBits(cfg3_Mask, 0, 32, 0);
2637189Sgblack@eecs.umich.edu    setRegMask(MISCREG_CONFIG3, cfg3_Mask);
2647189Sgblack@eecs.umich.edu
2657640Sgblack@eecs.umich.edu    // EBase - CPUNum
26610037SARM gem5 Developers    EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
26710205SAli.Saidi@ARM.com    eBase.cpuNum = cp.CP0_EBase_CPUNum;
2687189Sgblack@eecs.umich.edu    replaceBits(eBase, 31, 31, 1);
2697189Sgblack@eecs.umich.edu    setMiscRegNoEffect(MISCREG_EBASE, eBase);
2707189Sgblack@eecs.umich.edu    // Now, create Write Mask for Config register
2717189Sgblack@eecs.umich.edu    MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
2727640Sgblack@eecs.umich.edu                                 // entire register is read only
2737640Sgblack@eecs.umich.edu    replaceBits(EB_Mask, 0, 32, 0);
27410037SARM gem5 Developers    setRegMask(MISCREG_EBASE, EB_Mask);
27510205SAli.Saidi@ARM.com
27610205SAli.Saidi@ARM.com    // SRS Control - HSS (Highest Shadow Set)
27710037SARM gem5 Developers    SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
27810205SAli.Saidi@ARM.com    scsCtl.hss = cp.CP0_SrsCtl_HSS;
27910205SAli.Saidi@ARM.com    setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
28010037SARM gem5 Developers    // Now, create Write Mask for the SRS Ctl register
28110205SAli.Saidi@ARM.com    MiscReg SC_Mask = 0x0000F3C0;
28210205SAli.Saidi@ARM.com    replaceBits(SC_Mask, 0, 32, 0);
2838782Sgblack@eecs.umich.edu    setRegMask(MISCREG_SRSCTL, SC_Mask);
2847189Sgblack@eecs.umich.edu
28510417Sandreas.hansson@arm.com    // IntCtl - IPTI, IPPCI
28612176Sandreas.sandberg@arm.com    IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
28712176Sandreas.sandberg@arm.com    intCtl.ipti = cp.CP0_IntCtl_IPTI;
28812176Sandreas.sandberg@arm.com    intCtl.ippci = cp.CP0_IntCtl_IPPCI;
28912176Sandreas.sandberg@arm.com    setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
2907189Sgblack@eecs.umich.edu    // Now, create Write Mask for the IntCtl register
2917189Sgblack@eecs.umich.edu    MiscReg IC_Mask = 0x000003E0;
2927362Sgblack@eecs.umich.edu    replaceBits(IC_Mask, 0, 32, 0);
2937197Sgblack@eecs.umich.edu    setRegMask(MISCREG_INTCTL, IC_Mask);
2947197Sgblack@eecs.umich.edu
29510037SARM gem5 Developers    // Watch Hi - M - FIXME (More than 1 Watch register)
2967197Sgblack@eecs.umich.edu    WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
29710037SARM gem5 Developers    watchHi.m = cp.CP0_WatchHi_M;
29810037SARM gem5 Developers    setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
29910037SARM gem5 Developers    // Now, create Write Mask for the IntCtl register
30010037SARM gem5 Developers    MiscReg wh_Mask = 0x7FFF0FFF;
3018782Sgblack@eecs.umich.edu    replaceBits(wh_Mask, 0, 32, 0);
3027197Sgblack@eecs.umich.edu    setRegMask(MISCREG_WATCHHI0, wh_Mask);
30310417Sandreas.hansson@arm.com
30412176Sandreas.sandberg@arm.com    // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
30512176Sandreas.sandberg@arm.com    PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
30612176Sandreas.sandberg@arm.com    perfCntCtl.m = cp.CP0_PerfCtr_M;
30712176Sandreas.sandberg@arm.com    perfCntCtl.w = cp.CP0_PerfCtr_W;
30810037SARM gem5 Developers    setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
30910037SARM gem5 Developers    // Now, create Write Mask for the IntCtl register
31010037SARM gem5 Developers    MiscReg pc_Mask = 0x00007FF;
31110037SARM gem5 Developers    replaceBits(pc_Mask, 0, 32, 0);
31210037SARM gem5 Developers    setRegMask(MISCREG_PERFCNT0, pc_Mask);
31310037SARM gem5 Developers
31410037SARM gem5 Developers    // Random
31510037SARM gem5 Developers    setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
31610037SARM gem5 Developers    // Now, create Write Mask for the IntCtl register
31710417Sandreas.hansson@arm.com    MiscReg random_Mask = 0;
31812176Sandreas.sandberg@arm.com    replaceBits(random_Mask, 0, 32, 0);
31912176Sandreas.sandberg@arm.com    setRegMask(MISCREG_CP0_RANDOM, random_Mask);
32012176Sandreas.sandberg@arm.com
32110037SARM gem5 Developers    // PageGrain
32210037SARM gem5 Developers    PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
32310037SARM gem5 Developers    pageGrain.esp = cp.CP0_Config3_SP;
32410037SARM gem5 Developers    setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
32510037SARM gem5 Developers    // Now, create Write Mask for the IntCtl register
32610037SARM gem5 Developers    MiscReg pg_Mask = 0x10000000;
32710037SARM gem5 Developers    replaceBits(pg_Mask, 0, 32, 0);
32810037SARM gem5 Developers    setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
32910037SARM gem5 Developers
33010037SARM gem5 Developers    // Status
33110037SARM gem5 Developers    StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
33210037SARM gem5 Developers    // Only CU0 and IE are modified on a reset - everything else needs
33310037SARM gem5 Developers    // to be controlled on a per CPU model basis
33410037SARM gem5 Developers
33510037SARM gem5 Developers    // Enable CP0 on reset
33612176Sandreas.sandberg@arm.com    // status.cu0 = 1;
33710037SARM gem5 Developers
33810037SARM gem5 Developers    // Enable ERL bit on a reset
33910037SARM gem5 Developers    status.erl = 1;
34010037SARM gem5 Developers    // Enable BEV bit on a reset
34110037SARM gem5 Developers    status.bev = 1;
34210037SARM gem5 Developers
34310037SARM gem5 Developers    setMiscRegNoEffect(MISCREG_STATUS, status);
34410037SARM gem5 Developers    // Now, create Write Mask for the Status register
34510037SARM gem5 Developers    MiscReg stat_Mask = 0xFF78FF17;
34610037SARM gem5 Developers    replaceBits(stat_Mask, 0, 32, 0);
34710037SARM gem5 Developers    setRegMask(MISCREG_STATUS, stat_Mask);
34810037SARM gem5 Developers
34910037SARM gem5 Developers
35010037SARM gem5 Developers    // MVPConf0
35110037SARM gem5 Developers    MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
35212176Sandreas.sandberg@arm.com    mvpConf0.tca = 1;
35310037SARM gem5 Developers    mvpConf0.pvpe = num_vpes - 1;
35410037SARM gem5 Developers    mvpConf0.ptc = num_threads - 1;
35510037SARM gem5 Developers    setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
35610037SARM gem5 Developers
35710037SARM gem5 Developers    // VPEConf0
35810037SARM gem5 Developers    VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
35911576SDylan.Johnson@ARM.com    vpeConf0.mvp = 1;
36012176Sandreas.sandberg@arm.com    setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
36110037SARM gem5 Developers
36210037SARM gem5 Developers    // TCBind
36310037SARM gem5 Developers    for (ThreadID tid = 0; tid < num_threads; tid++) {
36410037SARM gem5 Developers        TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
36510037SARM gem5 Developers        tcBind.curTC = tid;
36610037SARM gem5 Developers        setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
36710037SARM gem5 Developers    }
36810037SARM gem5 Developers    // TCHalt
36910037SARM gem5 Developers    TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
37010037SARM gem5 Developers    tcHalt.h = 0;
37110037SARM gem5 Developers    setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
37210037SARM gem5 Developers
37310037SARM gem5 Developers    // TCStatus
37410037SARM gem5 Developers    // Set TCStatus Activated to 1 for the initial thread that is running
37510037SARM gem5 Developers    TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
37612176Sandreas.sandberg@arm.com    tcStatus.a = 1;
3777197Sgblack@eecs.umich.edu    setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
3787362Sgblack@eecs.umich.edu
3797362Sgblack@eecs.umich.edu    // Set Dynamically Allocatable bit to 1 for all other threads
3807362Sgblack@eecs.umich.edu    for (ThreadID tid = 1; tid < num_threads; tid++) {
3817362Sgblack@eecs.umich.edu        tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
3827362Sgblack@eecs.umich.edu        tcStatus.da = 1;
38310037SARM gem5 Developers        setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
38410037SARM gem5 Developers    }
38510037SARM gem5 Developers
38610037SARM gem5 Developers
38710037SARM gem5 Developers    MiscReg mask = 0x7FFFFFFF;
38810037SARM gem5 Developers
3897362Sgblack@eecs.umich.edu    // Now, create Write Mask for the Index register
39010037SARM gem5 Developers    replaceBits(mask, 0, 32, 0);
39110037SARM gem5 Developers    setRegMask(MISCREG_INDEX, mask);
39210037SARM gem5 Developers
39310037SARM gem5 Developers    mask = 0x3FFFFFFF;
39410037SARM gem5 Developers    replaceBits(mask, 0, 32, 0);
39510037SARM gem5 Developers    setRegMask(MISCREG_ENTRYLO0, mask);
3967362Sgblack@eecs.umich.edu    setRegMask(MISCREG_ENTRYLO1, mask);
39710037SARM gem5 Developers
39810037SARM gem5 Developers    mask = 0xFF800000;
39910037SARM gem5 Developers    replaceBits(mask, 0, 32, 0);
40010037SARM gem5 Developers    setRegMask(MISCREG_CONTEXT, mask);
40110037SARM gem5 Developers
40210037SARM gem5 Developers    mask = 0x1FFFF800;
4037362Sgblack@eecs.umich.edu    replaceBits(mask, 0, 32, 0);
4047362Sgblack@eecs.umich.edu    setRegMask(MISCREG_PAGEMASK, mask);
40510537Sandreas.hansson@arm.com
40610537Sandreas.hansson@arm.com    mask = 0x0;
40710537Sandreas.hansson@arm.com    replaceBits(mask, 0, 32, 0);
40810537Sandreas.hansson@arm.com    setRegMask(MISCREG_BADVADDR, mask);
40910537Sandreas.hansson@arm.com    setRegMask(MISCREG_LLADDR, mask);
41010037SARM gem5 Developers
4117362Sgblack@eecs.umich.edu    mask = 0x08C00300;
4127362Sgblack@eecs.umich.edu    replaceBits(mask, 0, 32, 0);
41310417Sandreas.hansson@arm.com    setRegMask(MISCREG_CAUSE, mask);
41412176Sandreas.sandberg@arm.com
41510037SARM gem5 Developers}
41612176Sandreas.sandberg@arm.com
41712176Sandreas.sandberg@arm.cominline unsigned
41812176Sandreas.sandberg@arm.comISA::getVPENum(ThreadID tid)
41912176Sandreas.sandberg@arm.com{
42012176Sandreas.sandberg@arm.com    TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
42110037SARM gem5 Developers    return tcBind.curVPE;
4227362Sgblack@eecs.umich.edu}
4237362Sgblack@eecs.umich.edu
4247362Sgblack@eecs.umich.eduMiscReg
4257362Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
4267362Sgblack@eecs.umich.edu{
42710037SARM gem5 Developers    unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
42810037SARM gem5 Developers        ? tid : getVPENum(tid);
42910037SARM gem5 Developers    DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
4307362Sgblack@eecs.umich.edu            misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
43110037SARM gem5 Developers            miscRegFile[misc_reg][reg_sel]);
43210037SARM gem5 Developers    return miscRegFile[misc_reg][reg_sel];
43310037SARM gem5 Developers}
43410037SARM gem5 Developers
4357362Sgblack@eecs.umich.edu//@TODO: MIPS MT's register view automatically connects
43610037SARM gem5 Developers//       Status to TCStatus depending on current thread
43712176Sandreas.sandberg@arm.com//template <class TC>
43810037SARM gem5 DevelopersMiscReg
43912176Sandreas.sandberg@arm.comISA::readMiscReg(int misc_reg, ThreadContext *tc,  ThreadID tid)
44012176Sandreas.sandberg@arm.com{
4417362Sgblack@eecs.umich.edu    unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
4427362Sgblack@eecs.umich.edu        ? tid : getVPENum(tid);
4437362Sgblack@eecs.umich.edu    DPRINTF(MipsPRA,
4447362Sgblack@eecs.umich.edu            "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
4457362Sgblack@eecs.umich.edu            misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
44610037SARM gem5 Developers            miscRegFile[misc_reg][reg_sel]);
44710037SARM gem5 Developers
44810037SARM gem5 Developers    return miscRegFile[misc_reg][reg_sel];
44910037SARM gem5 Developers}
45010037SARM gem5 Developers
45110037SARM gem5 Developersvoid
45210037SARM gem5 DevelopersISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
4537362Sgblack@eecs.umich.edu{
45410037SARM gem5 Developers    unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
45510037SARM gem5 Developers        ? tid : getVPENum(tid);
45610037SARM gem5 Developers    DPRINTF(MipsPRA,
45710037SARM gem5 Developers            "[tid:%i]: Setting (direct set) CP0 Register:%u "
45810037SARM gem5 Developers            "Select:%u (%s) to %#x.\n",
45910037SARM gem5 Developers            tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
46010037SARM gem5 Developers
46110037SARM gem5 Developers    miscRegFile[misc_reg][reg_sel] = val;
46210037SARM gem5 Developers}
4637362Sgblack@eecs.umich.edu
46410037SARM gem5 Developersvoid
46512176Sandreas.sandberg@arm.comISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
46610037SARM gem5 Developers{
46712176Sandreas.sandberg@arm.com    unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
46812176Sandreas.sandberg@arm.com        ? tid : getVPENum(tid);
46912176Sandreas.sandberg@arm.com    DPRINTF(MipsPRA,
47012176Sandreas.sandberg@arm.com            "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
4717362Sgblack@eecs.umich.edu            tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
4727362Sgblack@eecs.umich.edu    miscRegFile_WriteMask[misc_reg][reg_sel] = val;
47310037SARM gem5 Developers}
47410037SARM gem5 Developers
47510037SARM gem5 Developers// PROGRAMMER'S NOTES:
47610037SARM gem5 Developers// (1) Some CP0 Registers have fields that cannot
47710037SARM gem5 Developers// be overwritten. Make sure to handle those particular registers
47810037SARM gem5 Developers// with care!
47910037SARM gem5 Developersvoid
48010037SARM gem5 DevelopersISA::setMiscReg(int misc_reg, const MiscReg &val,
48110037SARM gem5 Developers                    ThreadContext *tc, ThreadID tid)
48210037SARM gem5 Developers{
48310037SARM gem5 Developers    int reg_sel = (bankType[misc_reg] == perThreadContext)
48410037SARM gem5 Developers        ? tid : getVPENum(tid);
48512176Sandreas.sandberg@arm.com
48610037SARM gem5 Developers    DPRINTF(MipsPRA,
48710037SARM gem5 Developers            "[tid:%i]: Setting CP0 Register:%u "
48810037SARM gem5 Developers            "Select:%u (%s) to %#x, with effect.\n",
48910037SARM gem5 Developers            tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
49010037SARM gem5 Developers
49112176Sandreas.sandberg@arm.com    MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
49212176Sandreas.sandberg@arm.com
49312176Sandreas.sandberg@arm.com    miscRegFile[misc_reg][reg_sel] = cp0_val;
49410037SARM gem5 Developers
49510037SARM gem5 Developers    scheduleCP0Update(tc->getCpuPtr(), 1);
49610037SARM gem5 Developers}
49710037SARM gem5 Developers
49810037SARM gem5 Developers/**
49910037SARM gem5 Developers * This method doesn't need to adjust the Control Register Offset
50010037SARM gem5 Developers * since it has already been done in the calling method
50110037SARM gem5 Developers * (setRegWithEffect)
50210037SARM gem5 Developers*/
50310037SARM gem5 DevelopersMiscReg
50410037SARM gem5 DevelopersISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
50512176Sandreas.sandberg@arm.com{
50612176Sandreas.sandberg@arm.com    MiscReg retVal = val;
50712176Sandreas.sandberg@arm.com
50812176Sandreas.sandberg@arm.com    // Mask off read-only regions
50910037SARM gem5 Developers    retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
51010037SARM gem5 Developers    MiscReg curVal = miscRegFile[misc_reg][reg_sel];
51110037SARM gem5 Developers    // Mask off current alue with inverse mask (clear writeable bits)
51210037SARM gem5 Developers    curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
51310037SARM gem5 Developers    retVal |= curVal; // Combine the two
51410037SARM gem5 Developers    DPRINTF(MipsPRA,
51510037SARM gem5 Developers            "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
51610037SARM gem5 Developers            "current val: %lx, written val: %x\n",
51710037SARM gem5 Developers            miscRegFile_WriteMask[misc_reg][reg_sel],
51810037SARM gem5 Developers            ~miscRegFile_WriteMask[misc_reg][reg_sel],
51910037SARM gem5 Developers            val, miscRegFile[misc_reg][reg_sel], retVal);
52010037SARM gem5 Developers    return retVal;
52110037SARM gem5 Developers}
52210037SARM gem5 Developers
52310037SARM gem5 Developersvoid
52410037SARM gem5 DevelopersISA::scheduleCP0Update(BaseCPU *cpu, int delay)
52510037SARM gem5 Developers{
52610417Sandreas.hansson@arm.com    if (!cp0Updated) {
52712176Sandreas.sandberg@arm.com        cp0Updated = true;
52810037SARM gem5 Developers
52910037SARM gem5 Developers        //schedule UPDATE
53010037SARM gem5 Developers        CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
53110037SARM gem5 Developers        cpu->schedule(cp0_event, curTick() + cpu->ticks(delay));
53210037SARM gem5 Developers    }
53310037SARM gem5 Developers}
53410037SARM gem5 Developers
53510037SARM gem5 Developersvoid
53610037SARM gem5 DevelopersISA::updateCPU(BaseCPU *cpu)
53710037SARM gem5 Developers{
53810037SARM gem5 Developers    ///////////////////////////////////////////////////////////////////
53910037SARM gem5 Developers    //
54010037SARM gem5 Developers    // EVALUATE CP0 STATE FOR MIPS MT
54110037SARM gem5 Developers    //
54210417Sandreas.hansson@arm.com    ///////////////////////////////////////////////////////////////////
54312176Sandreas.sandberg@arm.com    MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
54412176Sandreas.sandberg@arm.com    ThreadID num_threads = mvpConf0.ptc + 1;
54512176Sandreas.sandberg@arm.com
54610037SARM gem5 Developers    for (ThreadID tid = 0; tid < num_threads; tid++) {
5476019Shines@cs.fsu.edu        TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
5487652Sminkyu.jeong@arm.com        TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid);
5497652Sminkyu.jeong@arm.com
5507652Sminkyu.jeong@arm.com        //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
5517652Sminkyu.jeong@arm.com        if (tcHalt.h == 1 || tcStatus.a == 0)  {
5527652Sminkyu.jeong@arm.com            haltThread(cpu->getContext(tid));
55310417Sandreas.hansson@arm.com        } else if (tcHalt.h == 0 && tcStatus.a == 1) {
55412176Sandreas.sandberg@arm.com            restoreThread(cpu->getContext(tid));
5557652Sminkyu.jeong@arm.com        }
5567652Sminkyu.jeong@arm.com    }
5578518Sgeoffrey.blake@arm.com
5588518Sgeoffrey.blake@arm.com    num_threads = mvpConf0.ptc + 1;
5598518Sgeoffrey.blake@arm.com
5608518Sgeoffrey.blake@arm.com    // Toggle update flag after we finished updating
5618518Sgeoffrey.blake@arm.com    cp0Updated = false;
56210417Sandreas.hansson@arm.com}
56312176Sandreas.sandberg@arm.com
5648518Sgeoffrey.blake@arm.comISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
5658518Sgeoffrey.blake@arm.com    : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
56610037SARM gem5 Developers{  }
56710037SARM gem5 Developers
56810037SARM gem5 Developersvoid
56910037SARM gem5 DevelopersISA::CP0Event::process()
57010037SARM gem5 Developers{
57110037SARM gem5 Developers    switch (cp0EventType)
57210037SARM gem5 Developers    {
57311929SMatteo.Andreozzi@arm.com      case UpdateCP0:
57412032Sandreas.sandberg@arm.com        cp0->updateCPU(cpu);
57512032Sandreas.sandberg@arm.com        break;
57611929SMatteo.Andreozzi@arm.com    }
57711929SMatteo.Andreozzi@arm.com}
57811929SMatteo.Andreozzi@arm.com
57911929SMatteo.Andreozzi@arm.comconst char *
58011929SMatteo.Andreozzi@arm.comISA::CP0Event::description() const
58111929SMatteo.Andreozzi@arm.com{
58211929SMatteo.Andreozzi@arm.com    return "Coprocessor-0 event";
58311929SMatteo.Andreozzi@arm.com}
58411929SMatteo.Andreozzi@arm.com
58511929SMatteo.Andreozzi@arm.comvoid
58611929SMatteo.Andreozzi@arm.comISA::CP0Event::scheduleEvent(int delay)
58711929SMatteo.Andreozzi@arm.com{
58811929SMatteo.Andreozzi@arm.com    cpu->reschedule(this, curTick() + cpu->ticks(delay), true);
58911929SMatteo.Andreozzi@arm.com}
59011929SMatteo.Andreozzi@arm.com
59111929SMatteo.Andreozzi@arm.comvoid
59211929SMatteo.Andreozzi@arm.comISA::CP0Event::unscheduleEvent()
59311929SMatteo.Andreozzi@arm.com{
59411929SMatteo.Andreozzi@arm.com    if (scheduled())
59511929SMatteo.Andreozzi@arm.com        squash();
59611929SMatteo.Andreozzi@arm.com}
59711929SMatteo.Andreozzi@arm.com
59811929SMatteo.Andreozzi@arm.com}
5997811Ssteve.reinhardt@amd.com