interrupts.hh revision 5222:bb733a878f85
1/*
2 * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
3 *
4 * This software is part of the M5 simulator.
5 *
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8 * TO THESE TERMS AND CONDITIONS.
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11 * distribute this software and such derivative works for any purpose,
12 * so long as (1) the copyright notice above, this grant of permission,
13 * and the disclaimer below appear in all copies and derivative works
14 * made, (2) the copyright notice above is augmented as appropriate to
15 * reflect the addition of any new copyrightable work in a derivative
16 * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
17 * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
18 * advertising or publicity pertaining to the use or distribution of
19 * this software without specific, written prior authorization.
20 *
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34 * Authors: Richard Strong
35 */
36
37#ifndef __ARCH_MIPS_INTERRUPT_HH__
38#define __ARCH_MIPS_INTERRUPT_HH__
39
40
41#include "arch/mips/faults.hh"
42#include "base/compiler.hh"
43
44
45
46namespace MipsISA
47{
48class Interrupts
49{
50    /*
51      protected:
52      uint8_t intstatus;
53      bool oncputimerintr;
54      public:
55      Interrupts()
56      {
57      intstatus = 0;
58      newInfoSet = false;
59      oncputimerintr = false;
60
61      }
62      //  post(int int_num, int index) is responsible
63      //  for posting an interrupt. It sets a bit
64      //  in intstatus corresponding to Cause IP*. The
65      //  MIPS register Cause is updated by updateIntrInfo
66      //  which is called by check_interrupts
67      //
68      void post(int int_num, int index);
69      // clear(int int_num, int index) is responsible
70      //  for clearing an interrupt. It clear a bit
71      //  in intstatus corresponding to Cause IP*. The
72      //  MIPS register Cause is updated by updateIntrInfo
73      //  which is called by check_interrupts
74      //
75      void clear(int int_num, int index);
76      //  clear_all() is responsible
77      //  for clearing all interrupts. It clears all bits
78      //  in intstatus corresponding to Cause IP*. The
79      //  MIPS register Cause is updated by updateIntrInfo
80      //  which is called by check_interrupts
81      //
82      void clear_all();
83
84      // getInterrupt(ThreadContext * tc) checks if an interrupt
85      //  should be returned. It ands the interrupt mask and
86      //  and interrupt pending bits to see if one exists. It
87      //  also makes sure interrupts are enabled (IE) and
88      //  that ERL and ERX are not set
89      //
90      Fault getInterrupt(ThreadContext * tc);
91
92      // updateIntrInfo(ThreadContext *tc) const syncs the
93      //  MIPS cause register with the instatus variable. instatus
94      //  is essentially a copy of the MIPS cause[IP7:IP0]
95      //
96      void updateIntrInfo(ThreadContext *tc) const;
97      void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
98      bool onCpuTimerInterrupt(ThreadContext *tc) const;
99
100      uint64_t get_vec(int int_num);
101
102      bool check_interrupts(ThreadContext * tc) const{
103      //return (intstatus != 0) && !(tc->readPC() & 0x3);
104      if (oncputimerintr == false){
105      updateIntrInfo(tc);
106      return ((intstatus != 0) || onCpuTimerInterrupt(tc));
107      }
108      else
109      return true;
110
111      }
112    */
113
114
115  protected:
116    //uint8_t intstatus;
117    //bool oncputimerintr;
118  public:
119    Interrupts()
120    {
121        //intstatus = 0;
122        newInfoSet = false;
123        //oncputimerintr = false;
124
125    }
126    //  post(int int_num, int index) is responsible
127    //  for posting an interrupt. It sets a bit
128    //  in intstatus corresponding to Cause IP*. The
129    //  MIPS register Cause is updated by updateIntrInfo
130    //  which is called by check_interrupts
131    //
132    void post(int int_num, ThreadContext* tc);
133    void post(int int_num, int index);
134
135    // clear(int int_num, int index) is responsible
136    //  for clearing an interrupt. It clear a bit
137    //  in intstatus corresponding to Cause IP*. The
138    //  MIPS register Cause is updated by updateIntrInfo
139    //  which is called by check_interrupts
140    //
141    void clear(int int_num, ThreadContext* tc);
142    void clear(int int_num, int index);
143
144    //  clear_all() is responsible
145    //  for clearing all interrupts. It clears all bits
146    //  in intstatus corresponding to Cause IP*. The
147    //  MIPS register Cause is updated by updateIntrInfo
148    //  which is called by check_interrupts
149    //
150    void clear_all(ThreadContext* tc);
151    void clear_all();
152
153    // getInterrupt(ThreadContext * tc) checks if an interrupt
154    //  should be returned. It ands the interrupt mask and
155    //  and interrupt pending bits to see if one exists. It
156    //  also makes sure interrupts are enabled (IE) and
157    //  that ERL and ERX are not set
158    //
159    Fault getInterrupt(ThreadContext * tc);
160
161    // updateIntrInfo(ThreadContext *tc) const syncs the
162    //  MIPS cause register with the instatus variable. instatus
163    //  is essentially a copy of the MIPS cause[IP7:IP0]
164    //
165    void updateIntrInfo(ThreadContext *tc) const;
166    bool interruptsPending(ThreadContext *tc) const;
167    bool onCpuTimerInterrupt(ThreadContext *tc) const;
168
169    uint64_t get_vec(int int_num);
170
171    bool check_interrupts(ThreadContext * tc) const{
172        return interruptsPending(tc);
173    }
174
175
176    void serialize(std::ostream &os)
177    {
178        fatal("Serialization of Interrupts Unimplemented for MIPS");
179        //SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
180        //SERIALIZE_SCALAR(intstatus);
181    }
182
183    void unserialize(Checkpoint *cp, const std::string &section)
184    {
185        fatal("Unserialization of Interrupts Unimplemented for MIPS");
186        //UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
187        //UNSERIALIZE_SCALAR(intstatus);
188    }
189
190
191
192  private:
193    bool newInfoSet;
194    int newIpl;
195    int newSummary;
196
197};
198
199}
200
201#endif
202
203