interrupts.hh revision 12429:beefb9f5f551
11060SN/A/* 214025Sgiacomo.gabrielli@arm.com * Copyright (c) 2007 MIPS Technologies, Inc. 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * Redistribution and use in source and binary forms, with or without 67944SGiacomo.Gabrielli@arm.com * modification, are permitted provided that the following conditions are 77944SGiacomo.Gabrielli@arm.com * met: redistributions of source code must retain the above copyright 87944SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer; 97944SGiacomo.Gabrielli@arm.com * redistributions in binary form must reproduce the above copyright 107944SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the 117944SGiacomo.Gabrielli@arm.com * documentation and/or other materials provided with the distribution; 127944SGiacomo.Gabrielli@arm.com * neither the name of the copyright holders nor the names of its 137944SGiacomo.Gabrielli@arm.com * contributors may be used to endorse or promote products derived from 142702SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271060SN/A * 281060SN/A * Authors: Rick Strong 291060SN/A */ 301060SN/A 311060SN/A#ifndef __ARCH_MIPS_INTERRUPT_HH__ 321060SN/A#define __ARCH_MIPS_INTERRUPT_HH__ 331060SN/A 341060SN/A#include <string> 351060SN/A 361060SN/A#include "arch/mips/faults.hh" 371060SN/A#include "base/compiler.hh" 381060SN/A#include "base/logging.hh" 392665SN/A#include "params/MipsInterrupts.hh" 402665SN/A#include "sim/serialize.hh" 411060SN/A#include "sim/sim_object.hh" 421060SN/A 439944Smatt.horsnell@ARM.comclass BaseCPU; 449944Smatt.horsnell@ARM.comclass Checkpoint; 459944Smatt.horsnell@ARM.com 461060SN/Anamespace MipsISA 472292SN/A{ 488229Snate@binkert.org 491060SN/Aclass Interrupts : public SimObject 501060SN/A{ 511060SN/A public: 521061SN/A typedef MipsInterruptsParams Params; 536658Snate@binkert.org 546658Snate@binkert.org const Params * 551060SN/A params() const 568232Snate@binkert.org { 578232Snate@binkert.org return dynamic_cast<const Params *>(_params); 582669SN/A } 596658Snate@binkert.org 601060SN/A Interrupts(Params * p) : SimObject(p) 611061SN/A { 6210417Sandreas.hansson@arm.com } 6310417Sandreas.hansson@arm.com 647720Sgblack@eecs.umich.edu void 653794Sgblack@eecs.umich.edu setCPU(BaseCPU *_cpu) 6613453Srekai.gonzalezalberquilla@arm.com {} 6713453Srekai.gonzalezalberquilla@arm.com 6813453Srekai.gonzalezalberquilla@arm.com // post(int int_num, int index) is responsible 6913453Srekai.gonzalezalberquilla@arm.com // for posting an interrupt. It sets a bit 7013453Srekai.gonzalezalberquilla@arm.com // in intstatus corresponding to Cause IP*. The 7113453Srekai.gonzalezalberquilla@arm.com // MIPS register Cause is updated by updateIntrInfo 7213453Srekai.gonzalezalberquilla@arm.com // which is called by checkInterrupts 731060SN/A // 741464SN/A void post(int int_num, ThreadContext *tc); 751061SN/A void post(int int_num, int index); 767720Sgblack@eecs.umich.edu 777720Sgblack@eecs.umich.edu // clear(int int_num, int index) is responsible 784636Sgblack@eecs.umich.edu // for clearing an interrupt. It clear a bit 794636Sgblack@eecs.umich.edu // in intstatus corresponding to Cause IP*. The 804636Sgblack@eecs.umich.edu // MIPS register Cause is updated by updateIntrInfo 814636Sgblack@eecs.umich.edu // which is called by checkInterrupts 824636Sgblack@eecs.umich.edu // 8310417Sandreas.hansson@arm.com void clear(int int_num, ThreadContext* tc); 8410417Sandreas.hansson@arm.com void clear(int int_num, int index); 859046SAli.Saidi@ARM.com 861464SN/A // clearAll() is responsible 872292SN/A // for clearing all interrupts. It clears all bits 881464SN/A // in intstatus corresponding to Cause IP*. The 891464SN/A // MIPS register Cause is updated by updateIntrInfo 901464SN/A // which is called by checkInterrupts 911464SN/A // 921464SN/A void clearAll(ThreadContext *tc); 931464SN/A void clearAll(); 941464SN/A 952678SN/A // getInterrupt(ThreadContext * tc) checks if an interrupt 962669SN/A // should be returned. It ands the interrupt mask and 9713590Srekai.gonzalezalberquilla@arm.com // and interrupt pending bits to see if one exists. It 981060SN/A // also makes sure interrupts are enabled (IE) and 9910031SAli.Saidi@ARM.com // that ERL and ERX are not set 1001060SN/A // 1012731SN/A Fault getInterrupt(ThreadContext *tc); 1022731SN/A 1039046SAli.Saidi@ARM.com // updateIntrInfo(ThreadContext *tc) const syncs the 1049046SAli.Saidi@ARM.com // MIPS cause register with the instatus variable. instatus 1059046SAli.Saidi@ARM.com // is essentially a copy of the MIPS cause[IP7:IP0] 10613953Sgiacomo.gabrielli@arm.com // 1072731SN/A void updateIntrInfo(ThreadContext *tc) const; 1082292SN/A bool interruptsPending(ThreadContext *tc) const; 1092292SN/A bool onCpuTimerInterrupt(ThreadContext *tc) const; 1102292SN/A bool checkInterrupts(ThreadContext *tc) const; 1111060SN/A 1121060SN/A void 1131464SN/A serialize(CheckpointOut &cp) const override 1141060SN/A { 1151060SN/A fatal("Serialization of Interrupts Unimplemented for MIPS"); 1161060SN/A } 1172698SN/A 1182292SN/A void 1191060SN/A unserialize(CheckpointIn &cp) override 1205737Scws3k@cs.virginia.edu { 1215737Scws3k@cs.virginia.edu fatal("Unserialization of Interrupts Unimplemented for MIPS"); 1221060SN/A } 1235737Scws3k@cs.virginia.edu}; 1245375Svilas.sridharan@gmail.com 1252292SN/A} 1262292SN/A 1272292SN/A#endif 1285737Scws3k@cs.virginia.edu 1292292SN/A