interrupts.hh revision 6378
15222Sksewell@umich.edu/* 25254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 35254Sksewell@umich.edu * All rights reserved. 45222Sksewell@umich.edu * 55254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu * this software without specific prior written permission. 155222Sksewell@umich.edu * 165254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu * 285254Sksewell@umich.edu * Authors: Rick Strong 295222Sksewell@umich.edu */ 305222Sksewell@umich.edu 315222Sksewell@umich.edu#ifndef __ARCH_MIPS_INTERRUPT_HH__ 325222Sksewell@umich.edu#define __ARCH_MIPS_INTERRUPT_HH__ 335222Sksewell@umich.edu 345222Sksewell@umich.edu#include "arch/mips/faults.hh" 355222Sksewell@umich.edu#include "base/compiler.hh" 365222Sksewell@umich.edu 375222Sksewell@umich.edunamespace MipsISA 385222Sksewell@umich.edu{ 396378Sgblack@eecs.umich.edu 405222Sksewell@umich.educlass Interrupts 415222Sksewell@umich.edu{ 425222Sksewell@umich.edu public: 435222Sksewell@umich.edu Interrupts() 445222Sksewell@umich.edu { 455222Sksewell@umich.edu newInfoSet = false; 466378Sgblack@eecs.umich.edu } 475222Sksewell@umich.edu 485222Sksewell@umich.edu // post(int int_num, int index) is responsible 495222Sksewell@umich.edu // for posting an interrupt. It sets a bit 505222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 515222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 525704Snate@binkert.org // which is called by checkInterrupts 535222Sksewell@umich.edu // 546378Sgblack@eecs.umich.edu void post(int int_num, ThreadContext *tc); 555222Sksewell@umich.edu void post(int int_num, int index); 565222Sksewell@umich.edu 575222Sksewell@umich.edu // clear(int int_num, int index) is responsible 585222Sksewell@umich.edu // for clearing an interrupt. It clear a bit 595222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 605222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 615704Snate@binkert.org // which is called by checkInterrupts 625222Sksewell@umich.edu // 635222Sksewell@umich.edu void clear(int int_num, ThreadContext* tc); 645222Sksewell@umich.edu void clear(int int_num, int index); 655222Sksewell@umich.edu 665704Snate@binkert.org // clearAll() is responsible 675222Sksewell@umich.edu // for clearing all interrupts. It clears all bits 685222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 695222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 705704Snate@binkert.org // which is called by checkInterrupts 715222Sksewell@umich.edu // 726378Sgblack@eecs.umich.edu void clearAll(ThreadContext *tc); 735704Snate@binkert.org void clearAll(); 745222Sksewell@umich.edu 755222Sksewell@umich.edu // getInterrupt(ThreadContext * tc) checks if an interrupt 765222Sksewell@umich.edu // should be returned. It ands the interrupt mask and 775222Sksewell@umich.edu // and interrupt pending bits to see if one exists. It 785222Sksewell@umich.edu // also makes sure interrupts are enabled (IE) and 795222Sksewell@umich.edu // that ERL and ERX are not set 805222Sksewell@umich.edu // 816378Sgblack@eecs.umich.edu Fault getInterrupt(ThreadContext *tc); 825222Sksewell@umich.edu 835222Sksewell@umich.edu // updateIntrInfo(ThreadContext *tc) const syncs the 845222Sksewell@umich.edu // MIPS cause register with the instatus variable. instatus 855222Sksewell@umich.edu // is essentially a copy of the MIPS cause[IP7:IP0] 865222Sksewell@umich.edu // 875222Sksewell@umich.edu void updateIntrInfo(ThreadContext *tc) const; 885222Sksewell@umich.edu bool interruptsPending(ThreadContext *tc) const; 895222Sksewell@umich.edu bool onCpuTimerInterrupt(ThreadContext *tc) const; 905222Sksewell@umich.edu 915704Snate@binkert.org bool 925704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 935704Snate@binkert.org { 945222Sksewell@umich.edu return interruptsPending(tc); 955222Sksewell@umich.edu } 965222Sksewell@umich.edu 975222Sksewell@umich.edu 986378Sgblack@eecs.umich.edu void 996378Sgblack@eecs.umich.edu serialize(std::ostream &os) 1005222Sksewell@umich.edu { 1015222Sksewell@umich.edu fatal("Serialization of Interrupts Unimplemented for MIPS"); 1025222Sksewell@umich.edu } 1035222Sksewell@umich.edu 1046378Sgblack@eecs.umich.edu void 1056378Sgblack@eecs.umich.edu unserialize(Checkpoint *cp, const std::string §ion) 1065222Sksewell@umich.edu { 1075222Sksewell@umich.edu fatal("Unserialization of Interrupts Unimplemented for MIPS"); 1085222Sksewell@umich.edu } 1095222Sksewell@umich.edu 1105222Sksewell@umich.edu private: 1115222Sksewell@umich.edu bool newInfoSet; 1125222Sksewell@umich.edu int newIpl; 1135222Sksewell@umich.edu int newSummary; 1145222Sksewell@umich.edu}; 1155222Sksewell@umich.edu 1165222Sksewell@umich.edu} 1175222Sksewell@umich.edu 1185222Sksewell@umich.edu#endif 1195222Sksewell@umich.edu 120