interrupts.cc revision 8745
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Steve Reinhardt 30 * Kevin Lim 31 * Korey Sewell 32 */ 33 34#include "arch/mips/interrupts.hh" 35#include "arch/mips/isa_traits.hh" 36#include "arch/mips/pra_constants.hh" 37#include "base/trace.hh" 38#include "cpu/thread_context.hh" 39#include "debug/Interrupt.hh" 40 41namespace MipsISA 42{ 43 44static inline uint8_t 45getCauseIP(ThreadContext *tc) { 46 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 47 return cause.ip; 48} 49 50static inline void 51setCauseIP(ThreadContext *tc, uint8_t val) { 52 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 53 cause.ip = val; 54 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 55} 56 57void 58Interrupts::post(int int_num, ThreadContext* tc) 59{ 60 DPRINTF(Interrupt, "Interrupt %d posted\n", int_num); 61 if (int_num < 0 || int_num >= NumInterruptLevels) 62 panic("int_num out of bounds\n"); 63 64 uint8_t intstatus = getCauseIP(tc); 65 intstatus |= 1 << int_num; 66 setCauseIP(tc, intstatus); 67} 68 69void 70Interrupts::post(int int_num, int index) 71{ 72 fatal("Must use Thread Context when posting MIPS Interrupts in M5"); 73} 74 75void 76Interrupts::clear(int int_num, ThreadContext* tc) 77{ 78 DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num); 79 if (int_num < 0 || int_num >= NumInterruptLevels) 80 panic("int_num out of bounds\n"); 81 82 uint8_t intstatus = getCauseIP(tc); 83 intstatus &= ~(1 << int_num); 84 setCauseIP(tc, intstatus); 85} 86 87void 88Interrupts::clear(int int_num, int index) 89{ 90 fatal("Must use Thread Context when clearing MIPS Interrupts in M5"); 91} 92 93void 94Interrupts::clearAll(ThreadContext *tc) 95{ 96 DPRINTF(Interrupt, "Interrupts all cleared\n"); 97 uint8_t intstatus = 0; 98 setCauseIP(tc, intstatus); 99} 100 101void 102Interrupts::clearAll() 103{ 104 fatal("Must use Thread Context when clearing MIPS Interrupts in M5"); 105} 106 107 108 109Fault 110Interrupts::getInterrupt(ThreadContext * tc) 111{ 112 DPRINTF(Interrupt, "Interrupts getInterrupt\n"); 113 114 //Check if there are any outstanding interrupts 115 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 116 // Interrupts must be enabled, error level must be 0 or interrupts 117 // inhibited, and exception level must be 0 or interrupts inhibited 118 if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) { 119 // Software interrupts & hardware interrupts are handled in software. 120 // So if any interrupt that isn't masked is detected, jump to interrupt 121 // handler 122 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 123 if (status.im && cause.ip) { 124 DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n", 125 (unsigned)status.im, (unsigned)cause.ip); 126 return new InterruptFault; 127 } 128 } 129 130 return NoFault; 131} 132 133bool 134Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const 135{ 136 MiscReg compare = tc->readMiscRegNoEffect(MISCREG_COMPARE); 137 MiscReg count = tc->readMiscRegNoEffect(MISCREG_COUNT); 138 if (compare == count && count != 0) 139 return true; 140 return false; 141} 142 143void 144Interrupts::updateIntrInfo(ThreadContext *tc) const 145{ 146 //Nothing needs to be done. 147} 148 149bool 150Interrupts::interruptsPending(ThreadContext *tc) const 151{ 152 //if there is a on cpu timer interrupt (i.e. Compare == Count) 153 //update CauseIP before proceeding to interrupt 154 if (onCpuTimerInterrupt(tc)) { 155 DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n"); 156 //determine timer interrupt IP # 157 IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL); 158 uint8_t intStatus = getCauseIP(tc); 159 intStatus |= 1 << intCtl.ipti; 160 setCauseIP(tc, intStatus); 161 } 162 163 return (getCauseIP(tc) != 0); 164 165} 166 167} 168 169MipsISA::Interrupts * 170MipsInterruptsParams::create() 171{ 172 return new MipsISA::Interrupts(this); 173} 174