interrupts.cc revision 13615:5cc9363f5ab7 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 *          Kevin Lim
31 *          Korey Sewell
32 */
33
34#include "arch/mips/interrupts.hh"
35
36#include "arch/mips/isa_traits.hh"
37#include "arch/mips/pra_constants.hh"
38#include "base/trace.hh"
39#include "cpu/thread_context.hh"
40#include "debug/Interrupt.hh"
41
42namespace MipsISA
43{
44
45static inline uint8_t
46getCauseIP(ThreadContext *tc) {
47    CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
48    return cause.ip;
49}
50
51static inline void
52setCauseIP(ThreadContext *tc, uint8_t val) {
53    CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
54    cause.ip = val;
55    tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
56}
57
58void
59Interrupts::post(int int_num, ThreadContext* tc)
60{
61    DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
62    if (int_num < 0 || int_num >= NumInterruptLevels)
63        panic("int_num out of bounds\n");
64
65    uint8_t intstatus = getCauseIP(tc);
66    intstatus |= 1 << int_num;
67    setCauseIP(tc, intstatus);
68}
69
70void
71Interrupts::post(int int_num, int index)
72{
73    fatal("Must use Thread Context when posting MIPS Interrupts in M5");
74}
75
76void
77Interrupts::clear(int int_num, ThreadContext* tc)
78{
79    DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num);
80    if (int_num < 0 || int_num >= NumInterruptLevels)
81        panic("int_num out of bounds\n");
82
83    uint8_t intstatus = getCauseIP(tc);
84    intstatus &= ~(1 << int_num);
85    setCauseIP(tc, intstatus);
86}
87
88void
89Interrupts::clear(int int_num, int index)
90{
91    fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
92}
93
94void
95Interrupts::clearAll(ThreadContext *tc)
96{
97    DPRINTF(Interrupt, "Interrupts all cleared\n");
98    uint8_t intstatus = 0;
99    setCauseIP(tc, intstatus);
100}
101
102void
103Interrupts::clearAll()
104{
105    fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
106}
107
108
109bool
110Interrupts::checkInterrupts(ThreadContext *tc) const
111{
112    if (!interruptsPending(tc))
113        return false;
114
115    //Check if there are any outstanding interrupts
116    StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
117    // Interrupts must be enabled, error level must be 0 or interrupts
118    // inhibited, and exception level must be 0 or interrupts inhibited
119    if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
120        // Software interrupts & hardware interrupts are handled in software.
121        // So if any interrupt that isn't masked is detected, jump to interrupt
122        // handler
123        CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
124        if (status.im && cause.ip)
125            return true;
126
127    }
128
129    return false;
130}
131
132Fault
133Interrupts::getInterrupt(ThreadContext * tc)
134{
135    assert(checkInterrupts(tc));
136
137    StatusReg M5_VAR_USED status = tc->readMiscRegNoEffect(MISCREG_STATUS);
138    CauseReg M5_VAR_USED cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
139    DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
140            (unsigned)status.im, (unsigned)cause.ip);
141
142    return std::make_shared<InterruptFault>();
143}
144
145bool
146Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
147{
148    RegVal compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
149    RegVal count = tc->readMiscRegNoEffect(MISCREG_COUNT);
150    if (compare == count && count != 0)
151        return true;
152    return false;
153}
154
155void
156Interrupts::updateIntrInfo(ThreadContext *tc) const
157{
158    //Nothing needs to be done.
159}
160
161bool
162Interrupts::interruptsPending(ThreadContext *tc) const
163{
164    //if there is a on cpu timer interrupt (i.e. Compare == Count)
165    //update CauseIP before proceeding to interrupt
166    if (onCpuTimerInterrupt(tc)) {
167        DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
168        //determine timer interrupt IP #
169        IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL);
170        uint8_t intStatus = getCauseIP(tc);
171        intStatus |= 1 << intCtl.ipti;
172        setCauseIP(tc, intStatus);
173    }
174
175    return (getCauseIP(tc) != 0);
176
177}
178
179}
180
181MipsISA::Interrupts *
182MipsInterruptsParams::create()
183{
184    return new MipsISA::Interrupts(this);
185}
186