faults.hh revision 8568:83f728db3332
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Gabe Black 30 * Korey Sewell 31 * Jaidev Patwardhan 32 */ 33 34#ifndef __MIPS_FAULTS_HH__ 35#define __MIPS_FAULTS_HH__ 36 37#include "sim/faults.hh" 38 39namespace MipsISA 40{ 41 42typedef const Addr FaultVect; 43 44class MipsFaultBase : public FaultBase 45{ 46 protected: 47 virtual bool skipFaultingInstruction() {return false;} 48 virtual bool setRestartAddress() {return true;} 49 public: 50 struct FaultVals 51 { 52 const FaultName name; 53 const FaultVect vect; 54 FaultStat count; 55 }; 56 57 Addr badVAddr; 58 Addr entryHiAsid; 59 Addr entryHiVPN2; 60 Addr entryHiVPN2X; 61 Addr contextBadVPN2; 62#if FULL_SYSTEM 63 void invoke(ThreadContext * tc, 64 StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr) 65 {} 66 void setExceptionState(ThreadContext *, uint8_t); 67 void setHandlerPC(Addr, ThreadContext *); 68#endif 69}; 70 71template <typename T> 72class MipsFault : public MipsFaultBase 73{ 74 protected: 75 static FaultVals vals; 76 public: 77 FaultName name() const { return vals.name; } 78 FaultVect vect() const { return vals.vect; } 79 FaultStat & countStat() { return vals.count; } 80}; 81 82class MachineCheckFault : public MipsFault<MachineCheckFault> 83{ 84 public: 85 bool isMachineCheckFault() {return true;} 86}; 87 88class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt> 89{ 90 public: 91 bool isNonMaskableInterrupt() {return true;} 92}; 93 94class AddressErrorFault : public MipsFault<AddressErrorFault> 95{ 96 public: 97 AddressErrorFault(Addr vaddr) { badVAddr = vaddr; } 98#if FULL_SYSTEM 99 void invoke(ThreadContext * tc, 100 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 101#endif 102 103}; 104 105class StoreAddressErrorFault : public MipsFault<StoreAddressErrorFault> 106{ 107 public: 108 StoreAddressErrorFault(Addr vaddr) { badVAddr = vaddr; } 109#if FULL_SYSTEM 110 void invoke(ThreadContext * tc, 111 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 112#endif 113}; 114 115static inline Fault genMachineCheckFault() 116{ 117 return new MachineCheckFault; 118} 119 120class ResetFault : public MipsFault<ResetFault> 121{ 122 public: 123 void invoke(ThreadContext * tc, 124 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 125 126}; 127 128class SystemCallFault : public MipsFault<SystemCallFault> 129{ 130 public: 131#if FULL_SYSTEM 132 void invoke(ThreadContext * tc, 133 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 134#endif 135}; 136 137class SoftResetFault : public MipsFault<SoftResetFault> 138{ 139 public: 140 void invoke(ThreadContext * tc, 141 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 142}; 143 144class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault> 145{ 146 protected: 147 int coProcID; 148 public: 149 CoprocessorUnusableFault(int _procid) : coProcID(_procid) 150 {} 151 152 void invoke(ThreadContext * tc, 153 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 154}; 155 156class ReservedInstructionFault : public MipsFault<ReservedInstructionFault> 157{ 158 public: 159 void invoke(ThreadContext * tc, 160 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 161}; 162 163class ThreadFault : public MipsFault<ThreadFault> 164{ 165 public: 166 void invoke(ThreadContext * tc, 167 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 168}; 169 170class IntegerOverflowFault : public MipsFault<IntegerOverflowFault> 171{ 172 protected: 173 bool skipFaultingInstruction() {return true;} 174 public: 175#if FULL_SYSTEM 176 void invoke(ThreadContext * tc, 177 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 178#endif 179}; 180 181class InterruptFault : public MipsFault<InterruptFault> 182{ 183 protected: 184 bool setRestartAddress() {return false;} 185 public: 186#if FULL_SYSTEM 187 void invoke(ThreadContext * tc, 188 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 189#endif 190}; 191 192class TrapFault : public MipsFault<TrapFault> 193{ 194 public: 195#if FULL_SYSTEM 196 void invoke(ThreadContext * tc, 197 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 198#endif 199}; 200 201class BreakpointFault : public MipsFault<BreakpointFault> 202{ 203 public: 204#if FULL_SYSTEM 205 void invoke(ThreadContext * tc, 206 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 207#endif 208}; 209 210class ItbRefillFault : public MipsFault<ItbRefillFault> 211{ 212 public: 213 ItbRefillFault(Addr asid, Addr vaddr, Addr vpn) 214 { 215 entryHiAsid = asid; 216 entryHiVPN2 = vpn >> 2; 217 entryHiVPN2X = vpn & 0x3; 218 badVAddr = vaddr; 219 contextBadVPN2 = vpn >> 2; 220 } 221#if FULL_SYSTEM 222 void invoke(ThreadContext * tc, 223 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 224#endif 225}; 226 227class DtbRefillFault : public MipsFault<DtbRefillFault> 228{ 229 public: 230 DtbRefillFault(Addr asid, Addr vaddr, Addr vpn) 231 { 232 entryHiAsid = asid; 233 entryHiVPN2 = vpn >> 2; 234 entryHiVPN2X = vpn & 0x3; 235 badVAddr = vaddr; 236 contextBadVPN2 = vpn >> 2; 237 } 238#if FULL_SYSTEM 239 void invoke(ThreadContext * tc, 240 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 241#endif 242}; 243 244class ItbInvalidFault : public MipsFault<ItbInvalidFault> 245{ 246 public: 247 ItbInvalidFault(Addr asid, Addr vaddr, Addr vpn) 248 { 249 entryHiAsid = asid; 250 entryHiVPN2 = vpn >> 2; 251 entryHiVPN2X = vpn & 0x3; 252 badVAddr = vaddr; 253 contextBadVPN2 = vpn >> 2; 254 } 255#if FULL_SYSTEM 256 void invoke(ThreadContext * tc, 257 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 258#endif 259}; 260 261class TLBModifiedFault : public MipsFault<TLBModifiedFault> 262{ 263 public: 264 TLBModifiedFault(Addr asid, Addr vaddr, Addr vpn) 265 { 266 entryHiAsid = asid; 267 entryHiVPN2 = vpn >> 2; 268 entryHiVPN2X = vpn & 0x3; 269 badVAddr = vaddr; 270 contextBadVPN2 = vpn >> 2; 271 } 272#if FULL_SYSTEM 273 void invoke(ThreadContext * tc, 274 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 275#endif 276}; 277 278class DtbInvalidFault : public MipsFault<DtbInvalidFault> 279{ 280 public: 281 DtbInvalidFault(Addr asid, Addr vaddr, Addr vpn) 282 { 283 entryHiAsid = asid; 284 entryHiVPN2 = vpn >> 2; 285 entryHiVPN2X = vpn & 0x3; 286 badVAddr = vaddr; 287 contextBadVPN2 = vpn >> 2; 288 } 289#if FULL_SYSTEM 290 void invoke(ThreadContext * tc, 291 StaticInst::StaticInstPtr inst = nullStaticInstPtr); 292#endif 293}; 294 295class DspStateDisabledFault : public MipsFault<DspStateDisabledFault> 296{ 297 public: 298 void invoke(ThreadContext * tc, 299 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 300}; 301 302} // namespace MipsISA 303 304#endif // __MIPS_FAULTS_HH__ 305