dsp.hh revision 4661:44458219add1
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Brett Miller
29 */
30
31#ifndef __ARCH_MIPS_DSP_HH__
32#define __ARCH_MIPS_DSP_HH__
33
34#include "arch/mips/types.hh"
35#include "arch/mips/isa_traits.hh"
36#include "base/misc.hh"
37#include "config/full_system.hh"
38#include "sim/host.hh"
39
40class ThreadContext;
41
42namespace MipsISA {
43
44    // SIMD formats
45    enum {
46        SIMD_FMT_L,    // long word
47        SIMD_FMT_W,    // word
48        SIMD_FMT_PH,   // paired halfword
49        SIMD_FMT_QB,   // quad byte
50        SIMD_NUM_FMTS
51    };
52
53    // DSPControl Fields
54    enum {
55        DSP_POS,       // insertion bitfield position
56        DSP_SCOUNT,    // insertion bitfield size
57        DSP_C,         // carry bit
58        DSP_OUFLAG,    // overflow-underflow flag
59        DSP_CCOND,     // condition code
60        DSP_EFI,       // extract fail indicator bit
61        DSP_NUM_FIELDS
62    };
63
64    // compare instruction operations
65    enum {
66        CMP_EQ,        // equal
67        CMP_LT,        // less than
68        CMP_LE         // less than or equal
69    };
70
71    // SIMD operation order modes
72    enum {
73        MODE_L,        // left
74        MODE_R,        // right
75        MODE_LA,       // left-alternate
76        MODE_RA,       // right-alternate
77        MODE_X         // cross
78    };
79
80    // dsp operation parameters
81    enum { UNSIGNED, SIGNED };
82    enum { NOSATURATE, SATURATE };
83    enum { NOROUND, ROUND };
84
85    // DSPControl field positions and masks
86    const uint32_t DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 };
87    const uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS] = { 0x0000003f, 0x00001f80, 0x00002000,
88                                                    0x00ff0000, 0x0f000000, 0x00004000 };
89
90    // SIMD format constants
91    const uint32_t SIMD_MAX_VALS = 4; // maximum values per register
92    const uint32_t SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 }; // number of values in fmt
93    const uint32_t SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 }; // number of bits per value
94    const uint32_t SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 }; // log2( bits per value )
95
96    // DSP maximum values
97    const uint64_t FIXED_L_SMAX = ULL(0x7fffffffffffffff);
98    const uint64_t FIXED_W_SMAX = ULL(0x000000007fffffff);
99    const uint64_t FIXED_H_SMAX = ULL(0x0000000000007fff);
100    const uint64_t FIXED_B_SMAX = ULL(0x000000000000007f);
101    const uint64_t FIXED_L_UMAX = ULL(0xffffffffffffffff);
102    const uint64_t FIXED_W_UMAX = ULL(0x00000000ffffffff);
103    const uint64_t FIXED_H_UMAX = ULL(0x000000000000ffff);
104    const uint64_t FIXED_B_UMAX = ULL(0x00000000000000ff);
105    const uint64_t FIXED_SMAX[SIMD_NUM_FMTS] = { FIXED_L_SMAX, FIXED_W_SMAX, FIXED_H_SMAX, FIXED_B_SMAX };
106    const uint64_t FIXED_UMAX[SIMD_NUM_FMTS] = { FIXED_L_UMAX, FIXED_W_UMAX, FIXED_H_UMAX, FIXED_B_UMAX };
107
108    // DSP minimum values
109    const uint64_t FIXED_L_SMIN = ULL(0x8000000000000000);
110    const uint64_t FIXED_W_SMIN = ULL(0xffffffff80000000);
111    const uint64_t FIXED_H_SMIN = ULL(0xffffffffffff8000);
112    const uint64_t FIXED_B_SMIN = ULL(0xffffffffffffff80);
113    const uint64_t FIXED_L_UMIN = ULL(0x0000000000000000);
114    const uint64_t FIXED_W_UMIN = ULL(0x0000000000000000);
115    const uint64_t FIXED_H_UMIN = ULL(0x0000000000000000);
116    const uint64_t FIXED_B_UMIN = ULL(0x0000000000000000);
117    const uint64_t FIXED_SMIN[SIMD_NUM_FMTS] = { FIXED_L_SMIN, FIXED_W_SMIN, FIXED_H_SMIN, FIXED_B_SMIN };
118    const uint64_t FIXED_UMIN[SIMD_NUM_FMTS] = { FIXED_L_UMIN, FIXED_W_UMIN, FIXED_H_UMIN, FIXED_B_UMIN };
119
120    // DSP utility functions
121    int32_t bitrev( int32_t value );
122    uint64_t dspSaturate( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow );
123    uint64_t checkOverflow( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow );
124    uint64_t signExtend( uint64_t value, int32_t signpos );
125    uint64_t addHalfLsb( uint64_t value, int32_t lsbpos );
126    int32_t dspAbs( int32_t a, int32_t fmt, uint32_t *dspctl );
127    int32_t dspAdd( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl );
128    int32_t dspAddh( int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign );
129    int32_t dspSub( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl );
130    int32_t dspSubh( int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign );
131    int32_t dspShll( int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl );
132    int32_t dspShrl( int32_t a, uint32_t sa, int32_t fmt, int32_t sign );
133    int32_t dspShra( int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl );
134    int32_t dspMul( int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl );
135    int32_t dspMulq( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl );
136    int32_t dspMuleu( int32_t a, int32_t b, int32_t mode, uint32_t *dspctl );
137    int32_t dspMuleq( int32_t a, int32_t b, int32_t mode, uint32_t *dspctl );
138    int64_t dspDpaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt,
139                     int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl );
140    int64_t dspDpsq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt,
141                     int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl );
142    int64_t dspDpa( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode );
143    int64_t dspDps( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode );
144    int64_t dspMaq( int64_t dspac, int32_t a, int32_t b, int32_t ac,
145                    int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl );
146    int64_t dspMulsa( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt );
147    int64_t dspMulsaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl );
148    void dspCmp( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl );
149    int32_t dspCmpg( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op );
150    int32_t dspCmpgd( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl );
151    int32_t dspPrece( int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode );
152    int32_t dspPrecrqu( int32_t a, int32_t b, uint32_t *dspctl );
153    int32_t dspPrecrq( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl );
154    int32_t dspPrecrSra( int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round );
155    int32_t dspPick( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl );
156    int32_t dspPack( int32_t a, int32_t b, int32_t fmt );
157    int32_t dspExtr( int64_t dspac, int32_t fmt, int32_t sa, int32_t round,
158                     int32_t saturate, uint32_t *dspctl );
159    int32_t dspExtp( int64_t dspac, int32_t size, uint32_t *dspctl );
160    int32_t dspExtpd( int64_t dspac, int32_t size, uint32_t *dspctl );
161
162    // SIMD pack/unpack utility functions
163    void simdPack( uint64_t *values_ptr, int32_t *reg, int32_t fmt );
164    void simdUnpack( int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign );
165
166    // DSPControl r/w utility functions
167    void writeDSPControl( uint32_t *dspctl, uint32_t value, uint32_t mask );
168    uint32_t readDSPControl( uint32_t *dspctl, uint32_t mask );
169};
170
171#endif
172