dsp.hh revision 12429:beefb9f5f551 
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Brett Miller
29 */
30
31#ifndef __ARCH_MIPS_DSP_HH__
32#define __ARCH_MIPS_DSP_HH__
33
34#include "arch/mips/isa_traits.hh"
35#include "arch/mips/types.hh"
36#include "base/logging.hh"
37#include "base/types.hh"
38
39class ThreadContext;
40
41namespace MipsISA {
42
43// SIMD formats
44enum {
45    SIMD_FMT_L,    // long word
46    SIMD_FMT_W,    // word
47    SIMD_FMT_PH,   // paired halfword
48    SIMD_FMT_QB,   // quad byte
49    SIMD_NUM_FMTS
50};
51
52// DSPControl Fields
53enum {
54    DSP_POS,       // insertion bitfield position
55    DSP_SCOUNT,    // insertion bitfield size
56    DSP_C,         // carry bit
57    DSP_OUFLAG,    // overflow-underflow flag
58    DSP_CCOND,     // condition code
59    DSP_EFI,       // extract fail indicator bit
60    DSP_NUM_FIELDS
61};
62
63// compare instruction operations
64enum {
65    CMP_EQ,        // equal
66    CMP_LT,        // less than
67    CMP_LE         // less than or equal
68};
69
70// SIMD operation order modes
71enum {
72    MODE_L,        // left
73    MODE_R,        // right
74    MODE_LA,       // left-alternate
75    MODE_RA,       // right-alternate
76    MODE_X         // cross
77};
78
79// dsp operation parameters
80enum { UNSIGNED, SIGNED };
81enum { NOSATURATE, SATURATE };
82enum { NOROUND, ROUND };
83
84// DSPControl field positions and masks
85const uint32_t DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 };
86const uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS] =
87{ 0x0000003f, 0x00001f80, 0x00002000,
88  0x00ff0000, 0x0f000000, 0x00004000 };
89
90/*
91 * SIMD format constants
92 */
93
94// maximum values per register
95const uint32_t SIMD_MAX_VALS = 4;
96// number of values in fmt
97const uint32_t SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 };
98// number of bits per value
99const uint32_t SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 };
100// log2(bits per value)
101const uint32_t SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 };
102
103
104// DSP maximum values
105const uint64_t FIXED_L_SMAX = ULL(0x7fffffffffffffff);
106const uint64_t FIXED_W_SMAX = ULL(0x000000007fffffff);
107const uint64_t FIXED_H_SMAX = ULL(0x0000000000007fff);
108const uint64_t FIXED_B_SMAX = ULL(0x000000000000007f);
109const uint64_t FIXED_L_UMAX = ULL(0xffffffffffffffff);
110const uint64_t FIXED_W_UMAX = ULL(0x00000000ffffffff);
111const uint64_t FIXED_H_UMAX = ULL(0x000000000000ffff);
112const uint64_t FIXED_B_UMAX = ULL(0x00000000000000ff);
113const uint64_t FIXED_SMAX[SIMD_NUM_FMTS] =
114{ FIXED_L_SMAX, FIXED_W_SMAX, FIXED_H_SMAX, FIXED_B_SMAX };
115const uint64_t FIXED_UMAX[SIMD_NUM_FMTS] =
116{ FIXED_L_UMAX, FIXED_W_UMAX, FIXED_H_UMAX, FIXED_B_UMAX };
117
118// DSP minimum values
119const uint64_t FIXED_L_SMIN = ULL(0x8000000000000000);
120const uint64_t FIXED_W_SMIN = ULL(0xffffffff80000000);
121const uint64_t FIXED_H_SMIN = ULL(0xffffffffffff8000);
122const uint64_t FIXED_B_SMIN = ULL(0xffffffffffffff80);
123const uint64_t FIXED_L_UMIN = ULL(0x0000000000000000);
124const uint64_t FIXED_W_UMIN = ULL(0x0000000000000000);
125const uint64_t FIXED_H_UMIN = ULL(0x0000000000000000);
126const uint64_t FIXED_B_UMIN = ULL(0x0000000000000000);
127const uint64_t FIXED_SMIN[SIMD_NUM_FMTS] =
128{ FIXED_L_SMIN, FIXED_W_SMIN, FIXED_H_SMIN, FIXED_B_SMIN };
129const uint64_t FIXED_UMIN[SIMD_NUM_FMTS] =
130{ FIXED_L_UMIN, FIXED_W_UMIN, FIXED_H_UMIN, FIXED_B_UMIN };
131
132// DSP utility functions
133int32_t bitrev(int32_t value);
134uint64_t dspSaturate(uint64_t value, int32_t fmt, int32_t sign,
135                     uint32_t *overflow);
136uint64_t checkOverflow(uint64_t value, int32_t fmt, int32_t sign,
137                       uint32_t *overflow);
138uint64_t signExtend(uint64_t value, int32_t signpos);
139uint64_t addHalfLsb(uint64_t value, int32_t lsbpos);
140int32_t dspAbs(int32_t a, int32_t fmt, uint32_t *dspctl);
141int32_t dspAdd(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
142               int32_t sign, uint32_t *dspctl);
143int32_t dspAddh(int32_t a, int32_t b, int32_t fmt, int32_t round,
144                int32_t sign);
145int32_t dspSub(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
146               int32_t sign, uint32_t *dspctl);
147int32_t dspSubh(int32_t a, int32_t b, int32_t fmt, int32_t round,
148                int32_t sign);
149int32_t dspShll(int32_t a, uint32_t sa, int32_t fmt, int32_t saturate,
150                int32_t sign, uint32_t *dspctl);
151int32_t dspShrl(int32_t a, uint32_t sa, int32_t fmt, int32_t sign);
152int32_t dspShra(int32_t a, uint32_t sa, int32_t fmt, int32_t round,
153                int32_t sign, uint32_t *dspctl);
154int32_t dspMul(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
155               uint32_t *dspctl);
156int32_t dspMulq(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
157                int32_t round, uint32_t *dspctl);
158int32_t dspMuleu(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl);
159int32_t dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl);
160int64_t dspDpaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
161                int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
162                uint32_t *dspctl);
163int64_t dspDpsq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
164                int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
165                uint32_t *dspctl);
166int64_t dspDpa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
167               int32_t sign, int32_t mode);
168int64_t dspDps(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
169               int32_t sign, int32_t mode);
170int64_t dspMaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
171               int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl);
172int64_t dspMulsa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt);
173int64_t dspMulsaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
174                  uint32_t *dspctl);
175void dspCmp(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op,
176            uint32_t *dspctl);
177int32_t dspCmpg(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op);
178int32_t dspCmpgd(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op,
179                 uint32_t *dspctl);
180int32_t dspPrece(int32_t a, int32_t infmt, int32_t insign, int32_t outfmt,
181                 int32_t outsign, int32_t mode);
182int32_t dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl);
183int32_t dspPrecrq(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl);
184int32_t dspPrecrSra(int32_t a, int32_t b, int32_t sa, int32_t fmt,
185                    int32_t round);
186int32_t dspPick(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl);
187int32_t dspPack(int32_t a, int32_t b, int32_t fmt);
188int32_t dspExtr(int64_t dspac, int32_t fmt, int32_t sa, int32_t round,
189                int32_t saturate, uint32_t *dspctl);
190int32_t dspExtp(int64_t dspac, int32_t size, uint32_t *dspctl);
191int32_t dspExtpd(int64_t dspac, int32_t size, uint32_t *dspctl);
192
193// SIMD pack/unpack utility functions
194void simdPack(uint64_t *values_ptr, int32_t *reg, int32_t fmt);
195void simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign);
196
197// DSPControl r/w utility functions
198void writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask);
199uint32_t readDSPControl(uint32_t *dspctl, uint32_t mask);
200
201} // namespace MipsISA
202
203#endif // __ARCH_MIPS_DSP_HH__
204