decoder.hh revision 9024
12SN/A/* 21762SN/A * Copyright (c) 2012 Google 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu */ 302SN/A 312SN/A#ifndef __ARCH_MIPS_DECODER_HH__ 321717SN/A#define __ARCH_MIPS_DECODER_HH__ 331717SN/A 342SN/A#include "arch/generic/decode_cache.hh" 352SN/A#include "arch/mips/types.hh" 362SN/A#include "base/misc.hh" 374182Sgblack@eecs.umich.edu#include "base/types.hh" 38707SN/A#include "cpu/static_inst.hh" 391858SN/A 4056SN/Aclass ThreadContext; 414776Sgblack@eecs.umich.edu 422856Srdreslin@umich.edunamespace MipsISA 432SN/A{ 443520Sgblack@eecs.umich.edu 453520Sgblack@eecs.umich.educlass Decoder 463520Sgblack@eecs.umich.edu{ 473520Sgblack@eecs.umich.edu protected: 482190SN/A ThreadContext * tc; 492315SN/A //The extended machine instruction being generated 502680Sktlim@umich.edu ExtMachInst emi; 512SN/A bool instDone; 522856Srdreslin@umich.edu 532SN/A public: 544182Sgblack@eecs.umich.edu Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) 554182Sgblack@eecs.umich.edu {} 564182Sgblack@eecs.umich.edu 574182Sgblack@eecs.umich.edu ThreadContext *getTC() 584182Sgblack@eecs.umich.edu { 592356SN/A return tc; 602356SN/A } 612356SN/A 622356SN/A void 632356SN/A setTC(ThreadContext *_tc) 642356SN/A { 652356SN/A tc = _tc; 662356SN/A } 673126Sktlim@umich.edu 682356SN/A void 692356SN/A process() 702356SN/A { 715336Shines@cs.fsu.edu } 722356SN/A 732356SN/A void 742856Srdreslin@umich.edu reset() 752SN/A { 761634SN/A instDone = false; 771634SN/A } 781695SN/A 793814Ssaidi@eecs.umich.edu //Use this to give data to the decoder. This should be used 803814Ssaidi@eecs.umich.edu //when there is control flow. 811634SN/A void 821634SN/A moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 832359SN/A { 841695SN/A emi = inst; 855100Ssaidi@eecs.umich.edu instDone = true; 861695SN/A } 875099Ssaidi@eecs.umich.edu 883814Ssaidi@eecs.umich.edu bool 893814Ssaidi@eecs.umich.edu needMoreBytes() 901634SN/A { 913495Sktlim@umich.edu return true; 923495Sktlim@umich.edu } 933495Sktlim@umich.edu 943495Sktlim@umich.edu bool 953495Sktlim@umich.edu instReady() 963495Sktlim@umich.edu { 973495Sktlim@umich.edu return instDone; 983495Sktlim@umich.edu } 993495Sktlim@umich.edu 1003495Sktlim@umich.edu protected: 1013495Sktlim@umich.edu /// A cache of decoded instruction objects. 1023495Sktlim@umich.edu static GenericISA::BasicDecodeCache defaultCache; 1033495Sktlim@umich.edu 1043495Sktlim@umich.edu public: 1051858SN/A StaticInstPtr decodeInst(ExtMachInst mach_inst); 1062SN/A 1073520Sgblack@eecs.umich.edu /// Decode a machine instruction. 1083520Sgblack@eecs.umich.edu /// @param mach_inst The binary instruction to decode. 1093520Sgblack@eecs.umich.edu /// @retval A pointer to the corresponding StaticInst object. 1102SN/A StaticInstPtr 1112SN/A decode(ExtMachInst mach_inst, Addr addr) 1122SN/A { 1132SN/A return defaultCache.decode(this, mach_inst, addr); 1142SN/A } 1154103Ssaidi@eecs.umich.edu 1162SN/A StaticInstPtr 1173521Sgblack@eecs.umich.edu decode(MipsISA::PCState &nextPC) 1183521Sgblack@eecs.umich.edu { 1191917SN/A if (!instDone) 1201917SN/A return NULL; 1211917SN/A instDone = false; 1221917SN/A return decode(emi, nextPC.instAddr()); 1231917SN/A } 1241917SN/A}; 1251917SN/A 1261917SN/A} // namespace MipsISA 1271917SN/A 1281917SN/A#endif // __ARCH_MIPS_DECODER_HH__ 1291917SN/A