system.cc revision 5268
12SN/A/* 21762SN/A * Copyright (c) 2007 MIPS Technologies, Inc. 37534Ssteve.reinhardt@amd.com * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A * 282665Ssaidi@eecs.umich.edu * Authors: Jaidev Patwardhan 292665Ssaidi@eecs.umich.edu */ 302665Ssaidi@eecs.umich.edu 312SN/A#include "arch/vtophys.hh" 322SN/A#include "arch/mips/bare_iron/system.hh" 3311793Sbrandon.potter@amd.com#include "arch/mips/system.hh" 3411793Sbrandon.potter@amd.com#include "cpu/thread_context.hh" 3512334Sgabeblack@google.com#include "cpu/base.hh" 361031SN/A#include "dev/platform.hh" 37330SN/A#include "mem/physical.hh" 388320Ssteve.reinhardt@amd.com#include "mem/port.hh" 3910023Smatt.horsnell@ARM.com#include "params/BareIronMipsSystem.hh" 402SN/A#include "sim/byteswap.hh" 412SN/A 422SN/Ausing namespace std; 432SN/Ausing namespace MipsISA; 442SN/A 452SN/A 462SN/ABareIronMipsSystem::BareIronMipsSystem(Params *p) 472SN/A : MipsSystem(p) 482SN/A{ } 492SN/A 502SN/ABareIronMipsSystem::~BareIronMipsSystem() 512SN/A{ } 522SN/A 532SN/ABareIronMipsSystem * 542SN/ABareIronMipsSystemParams::create() 552SN/A{ 562SN/A return new BareIronMipsSystem(this); 572SN/A} 584762Snate@binkert.org 599983Sstever@gmail.com