xref: /gem5/src/arch/mips/SConscript

# -*- mode:python -*-

# Copyright (c) 2004-2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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#
# Authors: Gabe Black
#          Steve Reinhardt
#          Korey Sewell

Import('*')

if env['TARGET_ISA'] == 'mips':
    Source('bare_iron/system.cc')
    Source('decoder.cc')
    Source('dsp.cc')
    Source('faults.cc')
    Source('idle_event.cc')
    Source('interrupts.cc')
    Source('isa.cc')
    Source('linux/linux.cc')
    Source('linux/process.cc')
    Source('linux/system.cc')
    Source('pagetable.cc')
    Source('process.cc')
    Source('remote_gdb.cc')
    Source('stacktrace.cc')
    Source('system.cc')
    Source('tlb.cc')
    Source('utility.cc')
    Source('vtophys.cc')

    SimObject('MipsInterrupts.py')
    SimObject('MipsISA.py')
    SimObject('MipsSystem.py')
    SimObject('MipsTLB.py')

    DebugFlag('MipsPRA')

    ISADesc('isa/main.isa')