types.hh revision 14176:c6c06f180cb9
1360SN/A/* 21458SN/A * Copyright (c) 2010 Gabe Black 3360SN/A * All rights reserved. 4360SN/A * 5360SN/A * Redistribution and use in source and binary forms, with or without 6360SN/A * modification, are permitted provided that the following conditions are 7360SN/A * met: redistributions of source code must retain the above copyright 8360SN/A * notice, this list of conditions and the following disclaimer; 9360SN/A * redistributions in binary form must reproduce the above copyright 10360SN/A * notice, this list of conditions and the following disclaimer in the 11360SN/A * documentation and/or other materials provided with the distribution; 12360SN/A * neither the name of the copyright holders nor the names of its 13360SN/A * contributors may be used to endorse or promote products derived from 14360SN/A * this software without specific prior written permission. 15360SN/A * 16360SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17360SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18360SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19360SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20360SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21360SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22360SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23360SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24360SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25360SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26360SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu */ 30360SN/A 31360SN/A#ifndef __ARCH_GENERIC_TYPES_HH__ 322093SN/A#define __ARCH_GENERIC_TYPES_HH__ 33360SN/A 34360SN/A#include <iostream> 356712Snate@binkert.org#include <limits> 366712Snate@binkert.org 37360SN/A#include "base/trace.hh" 38360SN/A#include "base/types.hh" 397680Sgblack@eecs.umich.edu#include "sim/serialize.hh" 402474SN/A 41360SN/A// Logical register index type. 426658Snate@binkert.orgtypedef uint16_t RegIndex; 438229Snate@binkert.org 442680Sktlim@umich.edu/** Logical vector register elem index type. */ 458232Snate@binkert.orgusing ElemIndex = uint16_t; 462474SN/A 47360SN/A/** ElemIndex value that indicates that the register is not a vector. */ 488229Snate@binkert.org#define ILLEGAL_ELEM_INDEX std::numeric_limits<ElemIndex>::max() 498229Snate@binkert.org 506029Ssteve.reinhardt@amd.comnamespace GenericISA 51360SN/A{ 52360SN/A 532107SN/A// The guaranteed interface. 54360SN/Aclass PCStateBase : public Serializable 55360SN/A{ 563114Sgblack@eecs.umich.edu protected: 57360SN/A Addr _pc; 586702Sgblack@eecs.umich.edu Addr _npc; 596701Sgblack@eecs.umich.edu 606702Sgblack@eecs.umich.edu PCStateBase() : _pc(0), _npc(0) {} 616111Ssteve.reinhardt@amd.com PCStateBase(Addr val) : _pc(0), _npc(0) { set(val); } 626111Ssteve.reinhardt@amd.com 637823Ssteve.reinhardt@amd.com public: 646701Sgblack@eecs.umich.edu /** 656701Sgblack@eecs.umich.edu * Returns the memory address the bytes of this instruction came from. 666701Sgblack@eecs.umich.edu * 676701Sgblack@eecs.umich.edu * @return Memory address of the current instruction's encoding. 68360SN/A */ 692680Sktlim@umich.edu Addr 70360SN/A instAddr() const 712495SN/A { 727823Ssteve.reinhardt@amd.com return _pc; 73360SN/A } 741450SN/A 755958Sgblack@eecs.umich.edu /** 76360SN/A * Returns the memory address the bytes of the next instruction came from. 77360SN/A * 78360SN/A * @return Memory address of the next instruction's encoding. 791450SN/A */ 803114Sgblack@eecs.umich.edu Addr 812680Sktlim@umich.edu nextInstAddr() const 82360SN/A { 831969SN/A return _npc; 842484SN/A } 852484SN/A 86360SN/A /** 87360SN/A * Returns the current micropc. 88360SN/A * 891450SN/A * @return The current micropc. 903114Sgblack@eecs.umich.edu */ 912680Sktlim@umich.edu MicroPC 92360SN/A microPC() const 936701Sgblack@eecs.umich.edu { 941969SN/A return 0; 956701Sgblack@eecs.umich.edu } 96360SN/A 971458SN/A /** 98360SN/A * Force this PC to reflect a particular value, resetting all its other 99360SN/A * fields around it. This is useful for in place (re)initialization. 100360SN/A * 1011450SN/A * @param val The value to set the PC to. 1028149SChris.Emmons@ARM.com */ 1038149SChris.Emmons@ARM.com void set(Addr val); 1048149SChris.Emmons@ARM.com 1058149SChris.Emmons@ARM.com bool 1068149SChris.Emmons@ARM.com operator == (const PCStateBase &opc) const 1078149SChris.Emmons@ARM.com { 1088149SChris.Emmons@ARM.com return _pc == opc._pc && _npc == opc._npc; 1098149SChris.Emmons@ARM.com } 1108149SChris.Emmons@ARM.com 1118149SChris.Emmons@ARM.com bool 1128149SChris.Emmons@ARM.com operator != (const PCStateBase &opc) const 1138149SChris.Emmons@ARM.com { 1143114Sgblack@eecs.umich.edu return !(*this == opc); 1152680Sktlim@umich.edu } 116360SN/A 1176029Ssteve.reinhardt@amd.com void 1186029Ssteve.reinhardt@amd.com serialize(CheckpointOut &cp) const override 1196701Sgblack@eecs.umich.edu { 1205958Sgblack@eecs.umich.edu SERIALIZE_SCALAR(_pc); 1216701Sgblack@eecs.umich.edu SERIALIZE_SCALAR(_npc); 1226029Ssteve.reinhardt@amd.com } 1236029Ssteve.reinhardt@amd.com 1246029Ssteve.reinhardt@amd.com void 1252834Sksewell@umich.edu unserialize(CheckpointIn &cp) override 126360SN/A { 1271458SN/A UNSERIALIZE_SCALAR(_pc); 128360SN/A UNSERIALIZE_SCALAR(_npc); 129360SN/A } 130360SN/A}; 1311450SN/A 1326109Ssanchezd@stanford.edu 1336109Ssanchezd@stanford.edu/* 1346109Ssanchezd@stanford.edu * Different flavors of PC state. Only ISA specific code should rely on 1356109Ssanchezd@stanford.edu * any particular type of PC state being available. All other code should 1366109Ssanchezd@stanford.edu * use the interface above. 1376701Sgblack@eecs.umich.edu */ 1386109Ssanchezd@stanford.edu 1396701Sgblack@eecs.umich.edu// The most basic type of PC. 1406109Ssanchezd@stanford.edutemplate <class MachInst> 1416109Ssanchezd@stanford.educlass SimplePCState : public PCStateBase 1426109Ssanchezd@stanford.edu{ 1436109Ssanchezd@stanford.edu protected: 1446109Ssanchezd@stanford.edu typedef PCStateBase Base; 1456109Ssanchezd@stanford.edu 1463114Sgblack@eecs.umich.edu public: 147360SN/A 1482107SN/A Addr pc() const { return _pc; } 149360SN/A void pc(Addr val) { _pc = val; } 150360SN/A 151360SN/A Addr npc() const { return _npc; } 1521450SN/A void npc(Addr val) { _npc = val; } 1535748SSteve.Reinhardt@amd.com 154360SN/A void 155360SN/A set(Addr val) 1566701Sgblack@eecs.umich.edu { 1576701Sgblack@eecs.umich.edu pc(val); 1585748SSteve.Reinhardt@amd.com npc(val + sizeof(MachInst)); 1595748SSteve.Reinhardt@amd.com }; 1605748SSteve.Reinhardt@amd.com 1615748SSteve.Reinhardt@amd.com void 1625748SSteve.Reinhardt@amd.com setNPC(Addr val) 1635748SSteve.Reinhardt@amd.com { 1645748SSteve.Reinhardt@amd.com npc(val); 1655748SSteve.Reinhardt@amd.com } 1662474SN/A 1672474SN/A SimplePCState() {} 1685748SSteve.Reinhardt@amd.com SimplePCState(Addr val) { set(val); } 1698601Ssteve.reinhardt@amd.com 1706687Stjones1@inf.ed.ac.uk bool 1716687Stjones1@inf.ed.ac.uk branching() const 1726687Stjones1@inf.ed.ac.uk { 1736687Stjones1@inf.ed.ac.uk return this->npc() != this->pc() + sizeof(MachInst); 1748852Sandreas.hansson@arm.com } 1756687Stjones1@inf.ed.ac.uk 1766687Stjones1@inf.ed.ac.uk // Advance the PC. 1776687Stjones1@inf.ed.ac.uk void 1786687Stjones1@inf.ed.ac.uk advance() 1798852Sandreas.hansson@arm.com { 1806687Stjones1@inf.ed.ac.uk _pc = _npc; 1816687Stjones1@inf.ed.ac.uk _npc += sizeof(MachInst); 1826687Stjones1@inf.ed.ac.uk } 1836687Stjones1@inf.ed.ac.uk}; 1846687Stjones1@inf.ed.ac.uk 1858852Sandreas.hansson@arm.comtemplate <class MachInst> 1866687Stjones1@inf.ed.ac.ukstd::ostream & 1876687Stjones1@inf.ed.ac.ukoperator<<(std::ostream & os, const SimplePCState<MachInst> &pc) 1882474SN/A{ 1891450SN/A ccprintf(os, "(%#x=>%#x)", pc.pc(), pc.npc()); 1905748SSteve.Reinhardt@amd.com return os; 1915748SSteve.Reinhardt@amd.com} 1921458SN/A 1931458SN/A// A PC and microcode PC. 194360SN/Atemplate <class MachInst> 195360SN/Aclass UPCState : public SimplePCState<MachInst> 196360SN/A{ 1971450SN/A protected: 1983114Sgblack@eecs.umich.edu typedef SimplePCState<MachInst> Base; 199360SN/A 2006701Sgblack@eecs.umich.edu MicroPC _upc; 2016701Sgblack@eecs.umich.edu MicroPC _nupc; 2027508Stjones1@inf.ed.ac.uk 2037508Stjones1@inf.ed.ac.uk public: 2047508Stjones1@inf.ed.ac.uk 2057508Stjones1@inf.ed.ac.uk MicroPC upc() const { return _upc; } 2061970SN/A void upc(MicroPC val) { _upc = val; } 2071970SN/A 2081970SN/A MicroPC nupc() const { return _nupc; } 209360SN/A void nupc(MicroPC val) { _nupc = val; } 210360SN/A 211360SN/A MicroPC 2121450SN/A microPC() const 2133114Sgblack@eecs.umich.edu { 214360SN/A return _upc; 2156701Sgblack@eecs.umich.edu } 2166701Sgblack@eecs.umich.edu 2176701Sgblack@eecs.umich.edu void 2186701Sgblack@eecs.umich.edu set(Addr val) 2196701Sgblack@eecs.umich.edu { 220360SN/A Base::set(val); 221360SN/A upc(0); 222360SN/A nupc(1); 223360SN/A } 2248706Sandreas.hansson@arm.com 225360SN/A UPCState() : _upc(0), _nupc(0) {} 2261458SN/A UPCState(Addr val) : _upc(0), _nupc(0) { set(val); } 227360SN/A 228360SN/A bool 2291450SN/A branching() const 2303114Sgblack@eecs.umich.edu { 231360SN/A return this->npc() != this->pc() + sizeof(MachInst) || 2326701Sgblack@eecs.umich.edu this->nupc() != this->upc() + 1; 2336701Sgblack@eecs.umich.edu } 2346701Sgblack@eecs.umich.edu 2356701Sgblack@eecs.umich.edu // Advance the upc within the instruction. 2366701Sgblack@eecs.umich.edu void 237360SN/A uAdvance() 2388706Sandreas.hansson@arm.com { 239360SN/A _upc = _nupc; 240360SN/A _nupc++; 241360SN/A } 242360SN/A 243360SN/A // End the macroop by resetting the upc and advancing the regular pc. 2441458SN/A void 245360SN/A uEnd() 246360SN/A { 247360SN/A this->advance(); 2481450SN/A _upc = 0; 2493114Sgblack@eecs.umich.edu _nupc = 1; 250360SN/A } 2516701Sgblack@eecs.umich.edu 2526701Sgblack@eecs.umich.edu bool 2536701Sgblack@eecs.umich.edu operator == (const UPCState<MachInst> &opc) const 2546701Sgblack@eecs.umich.edu { 255360SN/A return Base::_pc == opc._pc && 256360SN/A Base::_npc == opc._npc && 257360SN/A _upc == opc._upc && _nupc == opc._nupc; 2581458SN/A } 259360SN/A 260360SN/A bool 261360SN/A operator != (const UPCState<MachInst> &opc) const 2621450SN/A { 2634118Sgblack@eecs.umich.edu return !(*this == opc); 2644118Sgblack@eecs.umich.edu } 2656701Sgblack@eecs.umich.edu 2666701Sgblack@eecs.umich.edu void 2676701Sgblack@eecs.umich.edu serialize(CheckpointOut &cp) const override 2686701Sgblack@eecs.umich.edu { 2696701Sgblack@eecs.umich.edu Base::serialize(cp); 2706701Sgblack@eecs.umich.edu SERIALIZE_SCALAR(_upc); 2714118Sgblack@eecs.umich.edu SERIALIZE_SCALAR(_nupc); 2724118Sgblack@eecs.umich.edu } 2734118Sgblack@eecs.umich.edu 2744118Sgblack@eecs.umich.edu void 2754118Sgblack@eecs.umich.edu unserialize(CheckpointIn &cp) override 2764118Sgblack@eecs.umich.edu { 2774118Sgblack@eecs.umich.edu Base::unserialize(cp); 2784118Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(_upc); 2794118Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(_nupc); 2804118Sgblack@eecs.umich.edu } 2816111Ssteve.reinhardt@amd.com}; 2826111Ssteve.reinhardt@amd.com 2836111Ssteve.reinhardt@amd.comtemplate <class MachInst> 2846111Ssteve.reinhardt@amd.comstd::ostream & 2854118Sgblack@eecs.umich.eduoperator<<(std::ostream & os, const UPCState<MachInst> &pc) 2864118Sgblack@eecs.umich.edu{ 2878706Sandreas.hansson@arm.com ccprintf(os, "(%#x=>%#x).(%d=>%d)", 2884118Sgblack@eecs.umich.edu pc.pc(), pc.npc(), pc.upc(), pc.nupc()); 2894118Sgblack@eecs.umich.edu return os; 2904118Sgblack@eecs.umich.edu} 2914118Sgblack@eecs.umich.edu 2924118Sgblack@eecs.umich.edu// A PC with a delay slot. 2934118Sgblack@eecs.umich.edutemplate <class MachInst> 2944118Sgblack@eecs.umich.educlass DelaySlotPCState : public SimplePCState<MachInst> 2954118Sgblack@eecs.umich.edu{ 2964118Sgblack@eecs.umich.edu protected: 2973114Sgblack@eecs.umich.edu typedef SimplePCState<MachInst> Base; 298360SN/A 299360SN/A Addr _nnpc; 3001458SN/A 301360SN/A public: 302360SN/A 303360SN/A Addr nnpc() const { return _nnpc; } 304360SN/A void nnpc(Addr val) { _nnpc = val; } 305360SN/A 3061450SN/A void 3073114Sgblack@eecs.umich.edu set(Addr val) 308360SN/A { 3096701Sgblack@eecs.umich.edu Base::set(val); 3106701Sgblack@eecs.umich.edu nnpc(val + 2 * sizeof(MachInst)); 3116701Sgblack@eecs.umich.edu } 3126701Sgblack@eecs.umich.edu 313360SN/A DelaySlotPCState() {} 314360SN/A DelaySlotPCState(Addr val) { set(val); } 315360SN/A 3168706Sandreas.hansson@arm.com bool 317360SN/A branching() const 3181458SN/A { 319360SN/A return !(this->nnpc() == this->npc() + sizeof(MachInst) && 320360SN/A (this->npc() == this->pc() + sizeof(MachInst) || 3211450SN/A this->npc() == this->pc() + 2 * sizeof(MachInst))); 3225513SMichael.Adler@intel.com } 3235513SMichael.Adler@intel.com 3245513SMichael.Adler@intel.com // Advance the PC. 3256731Svince@csl.cornell.edu void 3266701Sgblack@eecs.umich.edu advance() 3276701Sgblack@eecs.umich.edu { 3286701Sgblack@eecs.umich.edu Base::_pc = Base::_npc; 3295513SMichael.Adler@intel.com Base::_npc = _nnpc; 3305513SMichael.Adler@intel.com _nnpc += sizeof(MachInst); 3315513SMichael.Adler@intel.com } 3325513SMichael.Adler@intel.com 3335513SMichael.Adler@intel.com bool 3345513SMichael.Adler@intel.com operator == (const DelaySlotPCState<MachInst> &opc) const 3355513SMichael.Adler@intel.com { 3365513SMichael.Adler@intel.com return Base::_pc == opc._pc && 3375513SMichael.Adler@intel.com Base::_npc == opc._npc && 3385513SMichael.Adler@intel.com _nnpc == opc._nnpc; 3395513SMichael.Adler@intel.com } 3405513SMichael.Adler@intel.com 3415513SMichael.Adler@intel.com bool 3425513SMichael.Adler@intel.com operator != (const DelaySlotPCState<MachInst> &opc) const 3435513SMichael.Adler@intel.com { 3445513SMichael.Adler@intel.com return !(*this == opc); 3455513SMichael.Adler@intel.com } 3465513SMichael.Adler@intel.com 3475513SMichael.Adler@intel.com void 3485513SMichael.Adler@intel.com serialize(CheckpointOut &cp) const override 3498706Sandreas.hansson@arm.com { 3505513SMichael.Adler@intel.com Base::serialize(cp); 3515513SMichael.Adler@intel.com SERIALIZE_SCALAR(_nnpc); 3525513SMichael.Adler@intel.com } 3535513SMichael.Adler@intel.com 35410203SAli.Saidi@ARM.com void 35510203SAli.Saidi@ARM.com unserialize(CheckpointIn &cp) override 35610203SAli.Saidi@ARM.com { 35710203SAli.Saidi@ARM.com Base::unserialize(cp); 35810203SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_nnpc); 35910203SAli.Saidi@ARM.com } 36010203SAli.Saidi@ARM.com}; 3615513SMichael.Adler@intel.com 3625513SMichael.Adler@intel.comtemplate <class MachInst> 36310203SAli.Saidi@ARM.comstd::ostream & 36410203SAli.Saidi@ARM.comoperator<<(std::ostream & os, const DelaySlotPCState<MachInst> &pc) 3655513SMichael.Adler@intel.com{ 3665513SMichael.Adler@intel.com ccprintf(os, "(%#x=>%#x=>%#x)", 3675513SMichael.Adler@intel.com pc.pc(), pc.npc(), pc.nnpc()); 3688852Sandreas.hansson@arm.com return os; 3695513SMichael.Adler@intel.com} 3705513SMichael.Adler@intel.com 3715513SMichael.Adler@intel.com// A PC with a delay slot and a microcode PC. 3725513SMichael.Adler@intel.comtemplate <class MachInst> 3735513SMichael.Adler@intel.comclass DelaySlotUPCState : public DelaySlotPCState<MachInst> 3746701Sgblack@eecs.umich.edu{ 3756701Sgblack@eecs.umich.edu protected: 3766701Sgblack@eecs.umich.edu typedef DelaySlotPCState<MachInst> Base; 3776701Sgblack@eecs.umich.edu 3785513SMichael.Adler@intel.com MicroPC _upc; 3795513SMichael.Adler@intel.com MicroPC _nupc; 3805513SMichael.Adler@intel.com 3818706Sandreas.hansson@arm.com public: 3825513SMichael.Adler@intel.com 3835513SMichael.Adler@intel.com MicroPC upc() const { return _upc; } 3845513SMichael.Adler@intel.com void upc(MicroPC val) { _upc = val; } 3855513SMichael.Adler@intel.com 3865513SMichael.Adler@intel.com MicroPC nupc() const { return _nupc; } 3873114Sgblack@eecs.umich.edu void nupc(MicroPC val) { _nupc = val; } 388511SN/A 3891706SN/A MicroPC 390360SN/A microPC() const 3916701Sgblack@eecs.umich.edu { 3928852Sandreas.hansson@arm.com return _upc; 3931450SN/A } 394511SN/A 3953669Sbinkertn@umich.edu void 3963669Sbinkertn@umich.edu set(Addr val) 3973669Sbinkertn@umich.edu { 398511SN/A Base::set(val); 3991458SN/A upc(0); 400511SN/A nupc(1); 401511SN/A } 4025513SMichael.Adler@intel.com 4035513SMichael.Adler@intel.com DelaySlotUPCState() {} 4045513SMichael.Adler@intel.com DelaySlotUPCState(Addr val) { set(val); } 4055513SMichael.Adler@intel.com 4065513SMichael.Adler@intel.com bool 4075513SMichael.Adler@intel.com branching() const 4086701Sgblack@eecs.umich.edu { 4098852Sandreas.hansson@arm.com return Base::branching() || this->nupc() != this->upc() + 1; 4105513SMichael.Adler@intel.com } 4115513SMichael.Adler@intel.com 4125513SMichael.Adler@intel.com // Advance the upc within the instruction. 4135513SMichael.Adler@intel.com void 4145513SMichael.Adler@intel.com uAdvance() 4156701Sgblack@eecs.umich.edu { 4165513SMichael.Adler@intel.com _upc = _nupc; 4175513SMichael.Adler@intel.com _nupc++; 4185513SMichael.Adler@intel.com } 4195513SMichael.Adler@intel.com 4205513SMichael.Adler@intel.com // End the macroop by resetting the upc and advancing the regular pc. 4211450SN/A void 4223114Sgblack@eecs.umich.edu uEnd() 423511SN/A { 4241706SN/A this->advance(); 425511SN/A _upc = 0; 4266701Sgblack@eecs.umich.edu _nupc = 1; 4278852Sandreas.hansson@arm.com } 4281458SN/A 429511SN/A bool 4301706SN/A operator == (const DelaySlotUPCState<MachInst> &opc) const 431511SN/A { 4328852Sandreas.hansson@arm.com return Base::_pc == opc._pc && 4331458SN/A Base::_npc == opc._npc && 434511SN/A Base::_nnpc == opc._nnpc && 4353669Sbinkertn@umich.edu _upc == opc._upc && _nupc == opc._nupc; 4363669Sbinkertn@umich.edu } 4373669Sbinkertn@umich.edu 4383669Sbinkertn@umich.edu bool 4391706SN/A operator != (const DelaySlotUPCState<MachInst> &opc) const 4401458SN/A { 441511SN/A return !(*this == opc); 442511SN/A } 4431706SN/A 4443114Sgblack@eecs.umich.edu void 4451706SN/A serialize(CheckpointOut &cp) const override 4461706SN/A { 4471706SN/A Base::serialize(cp); 4486701Sgblack@eecs.umich.edu SERIALIZE_SCALAR(_upc); 4498852Sandreas.hansson@arm.com SERIALIZE_SCALAR(_nupc); 4501706SN/A } 4511706SN/A 4526701Sgblack@eecs.umich.edu void 4531706SN/A unserialize(CheckpointIn &cp) override 4543669Sbinkertn@umich.edu { 4553669Sbinkertn@umich.edu Base::unserialize(cp); 4563669Sbinkertn@umich.edu UNSERIALIZE_SCALAR(_upc); 4571706SN/A UNSERIALIZE_SCALAR(_nupc); 4581706SN/A } 4591706SN/A}; 4601706SN/A 4611706SN/Atemplate <class MachInst> 4626111Ssteve.reinhardt@amd.comstd::ostream & 4636111Ssteve.reinhardt@amd.comoperator<<(std::ostream & os, const DelaySlotUPCState<MachInst> &pc) 4641706SN/A{ 4656701Sgblack@eecs.umich.edu ccprintf(os, "(%#x=>%#x=>%#x).(%d=>%d)", 4666701Sgblack@eecs.umich.edu pc.pc(), pc.npc(), pc.nnpc(), pc.upc(), pc.nupc()); 4671706SN/A return os; 4681706SN/A} 4691706SN/A 4701706SN/A} 4716701Sgblack@eecs.umich.edu 4721706SN/A#endif 4731706SN/A