types.hh revision 12104:edd63f9c6184
110915Sandreas.sandberg@arm.com/*
211313Sandreas.sandberg@arm.com * Copyright (c) 2010 Gabe Black
310915Sandreas.sandberg@arm.com * All rights reserved.
410915Sandreas.sandberg@arm.com *
510915Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without
610915Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are
710915Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright
810915Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer;
910915Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright
1010915Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the
1110915Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution;
1210915Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its
1310915Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from
1410915Sandreas.sandberg@arm.com * this software without specific prior written permission.
1510915Sandreas.sandberg@arm.com *
1610915Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1710915Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1810915Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1910915Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2010915Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2110915Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2210915Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2310915Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2410915Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2510915Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2610915Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2710915Sandreas.sandberg@arm.com *
2810915Sandreas.sandberg@arm.com * Authors: Gabe Black
2910915Sandreas.sandberg@arm.com */
3010915Sandreas.sandberg@arm.com
3110915Sandreas.sandberg@arm.com#ifndef __ARCH_GENERIC_TYPES_HH__
3210915Sandreas.sandberg@arm.com#define __ARCH_GENERIC_TYPES_HH__
3310915Sandreas.sandberg@arm.com
3410915Sandreas.sandberg@arm.com#include <iostream>
3510915Sandreas.sandberg@arm.com
3610915Sandreas.sandberg@arm.com#include "base/trace.hh"
3710915Sandreas.sandberg@arm.com#include "base/types.hh"
3810915Sandreas.sandberg@arm.com#include "sim/serialize.hh"
3910915Sandreas.sandberg@arm.com
4010915Sandreas.sandberg@arm.com// Logical register index type.
4110915Sandreas.sandberg@arm.comtypedef uint16_t RegIndex;
4210915Sandreas.sandberg@arm.com
4310915Sandreas.sandberg@arm.comnamespace GenericISA
4410915Sandreas.sandberg@arm.com{
4510915Sandreas.sandberg@arm.com
4610915Sandreas.sandberg@arm.com// The guaranteed interface.
4710915Sandreas.sandberg@arm.comclass PCStateBase : public Serializable
4810915Sandreas.sandberg@arm.com{
4910915Sandreas.sandberg@arm.com  protected:
5010915Sandreas.sandberg@arm.com    Addr _pc;
5110915Sandreas.sandberg@arm.com    Addr _npc;
5210915Sandreas.sandberg@arm.com
5310915Sandreas.sandberg@arm.com    PCStateBase() : _pc(0), _npc(0) {}
5410915Sandreas.sandberg@arm.com    PCStateBase(Addr val) : _pc(0), _npc(0) { set(val); }
5510915Sandreas.sandberg@arm.com
5610915Sandreas.sandberg@arm.com  public:
5710915Sandreas.sandberg@arm.com    /**
5810915Sandreas.sandberg@arm.com     * Returns the memory address the bytes of this instruction came from.
5910915Sandreas.sandberg@arm.com     *
6010915Sandreas.sandberg@arm.com     * @return Memory address of the current instruction's encoding.
6110915Sandreas.sandberg@arm.com     */
6210915Sandreas.sandberg@arm.com    Addr
6310915Sandreas.sandberg@arm.com    instAddr() const
6410915Sandreas.sandberg@arm.com    {
6510915Sandreas.sandberg@arm.com        return _pc;
6610915Sandreas.sandberg@arm.com    }
6710915Sandreas.sandberg@arm.com
6810915Sandreas.sandberg@arm.com    /**
6910915Sandreas.sandberg@arm.com     * Returns the memory address the bytes of the next instruction came from.
7010915Sandreas.sandberg@arm.com     *
7110915Sandreas.sandberg@arm.com     * @return Memory address of the next instruction's encoding.
7210915Sandreas.sandberg@arm.com     */
7310915Sandreas.sandberg@arm.com    Addr
7410915Sandreas.sandberg@arm.com    nextInstAddr() const
7510915Sandreas.sandberg@arm.com    {
7610915Sandreas.sandberg@arm.com        return _npc;
7710915Sandreas.sandberg@arm.com    }
7810915Sandreas.sandberg@arm.com
7910915Sandreas.sandberg@arm.com    /**
8010915Sandreas.sandberg@arm.com     * Returns the current micropc.
8110915Sandreas.sandberg@arm.com     *
8210915Sandreas.sandberg@arm.com     * @return The current micropc.
8310915Sandreas.sandberg@arm.com     */
8410915Sandreas.sandberg@arm.com    MicroPC
8510915Sandreas.sandberg@arm.com    microPC() const
8610915Sandreas.sandberg@arm.com    {
8710915Sandreas.sandberg@arm.com        return 0;
8811313Sandreas.sandberg@arm.com    }
8911313Sandreas.sandberg@arm.com
9010915Sandreas.sandberg@arm.com    /**
9110915Sandreas.sandberg@arm.com     * Force this PC to reflect a particular value, resetting all its other
9210915Sandreas.sandberg@arm.com     * fields around it. This is useful for in place (re)initialization.
9310915Sandreas.sandberg@arm.com     *
9410915Sandreas.sandberg@arm.com     * @param val The value to set the PC to.
9510915Sandreas.sandberg@arm.com     */
9610915Sandreas.sandberg@arm.com    void set(Addr val);
9710915Sandreas.sandberg@arm.com
9810915Sandreas.sandberg@arm.com    bool
9910915Sandreas.sandberg@arm.com    operator == (const PCStateBase &opc) const
10010915Sandreas.sandberg@arm.com    {
10110915Sandreas.sandberg@arm.com        return _pc == opc._pc && _npc == opc._npc;
10210915Sandreas.sandberg@arm.com    }
10310915Sandreas.sandberg@arm.com
10410915Sandreas.sandberg@arm.com    bool
10510915Sandreas.sandberg@arm.com    operator != (const PCStateBase &opc) const
10610915Sandreas.sandberg@arm.com    {
10710915Sandreas.sandberg@arm.com        return !(*this == opc);
10810915Sandreas.sandberg@arm.com    }
10910915Sandreas.sandberg@arm.com
11010915Sandreas.sandberg@arm.com    void
11110915Sandreas.sandberg@arm.com    serialize(CheckpointOut &cp) const override
11210915Sandreas.sandberg@arm.com    {
11310915Sandreas.sandberg@arm.com        SERIALIZE_SCALAR(_pc);
11410915Sandreas.sandberg@arm.com        SERIALIZE_SCALAR(_npc);
11510915Sandreas.sandberg@arm.com    }
11610915Sandreas.sandberg@arm.com
11710915Sandreas.sandberg@arm.com    void
11810915Sandreas.sandberg@arm.com    unserialize(CheckpointIn &cp) override
11910915Sandreas.sandberg@arm.com    {
12010915Sandreas.sandberg@arm.com        UNSERIALIZE_SCALAR(_pc);
12110915Sandreas.sandberg@arm.com        UNSERIALIZE_SCALAR(_npc);
12210915Sandreas.sandberg@arm.com    }
12310915Sandreas.sandberg@arm.com};
12410915Sandreas.sandberg@arm.com
12510915Sandreas.sandberg@arm.com
12610915Sandreas.sandberg@arm.com/*
12710915Sandreas.sandberg@arm.com * Different flavors of PC state. Only ISA specific code should rely on
12810915Sandreas.sandberg@arm.com * any particular type of PC state being available. All other code should
12910915Sandreas.sandberg@arm.com * use the interface above.
13011313Sandreas.sandberg@arm.com */
13110915Sandreas.sandberg@arm.com
13210915Sandreas.sandberg@arm.com// The most basic type of PC.
13310915Sandreas.sandberg@arm.comtemplate <class MachInst>
13410915Sandreas.sandberg@arm.comclass SimplePCState : public PCStateBase
13510915Sandreas.sandberg@arm.com{
13610915Sandreas.sandberg@arm.com  protected:
13710915Sandreas.sandberg@arm.com    typedef PCStateBase Base;
13810915Sandreas.sandberg@arm.com
13910915Sandreas.sandberg@arm.com  public:
14010915Sandreas.sandberg@arm.com
14110915Sandreas.sandberg@arm.com    Addr pc() const { return _pc; }
14210915Sandreas.sandberg@arm.com    void pc(Addr val) { _pc = val; }
14310915Sandreas.sandberg@arm.com
14410915Sandreas.sandberg@arm.com    Addr npc() const { return _npc; }
14510915Sandreas.sandberg@arm.com    void npc(Addr val) { _npc = val; }
14610915Sandreas.sandberg@arm.com
14710915Sandreas.sandberg@arm.com    void
14810915Sandreas.sandberg@arm.com    set(Addr val)
14910915Sandreas.sandberg@arm.com    {
15010915Sandreas.sandberg@arm.com        pc(val);
15110915Sandreas.sandberg@arm.com        npc(val + sizeof(MachInst));
15210915Sandreas.sandberg@arm.com    };
15310915Sandreas.sandberg@arm.com
15410915Sandreas.sandberg@arm.com    void
15510915Sandreas.sandberg@arm.com    setNPC(Addr val)
15610915Sandreas.sandberg@arm.com    {
15710915Sandreas.sandberg@arm.com        npc(val);
15810915Sandreas.sandberg@arm.com    }
15910915Sandreas.sandberg@arm.com
16010915Sandreas.sandberg@arm.com    SimplePCState() {}
16110915Sandreas.sandberg@arm.com    SimplePCState(Addr val) { set(val); }
16210915Sandreas.sandberg@arm.com
16310915Sandreas.sandberg@arm.com    bool
16410915Sandreas.sandberg@arm.com    branching() const
16510915Sandreas.sandberg@arm.com    {
16610915Sandreas.sandberg@arm.com        return this->npc() != this->pc() + sizeof(MachInst);
16710915Sandreas.sandberg@arm.com    }
16810915Sandreas.sandberg@arm.com
16910915Sandreas.sandberg@arm.com    // Advance the PC.
17010915Sandreas.sandberg@arm.com    void
17110915Sandreas.sandberg@arm.com    advance()
17210915Sandreas.sandberg@arm.com    {
17310915Sandreas.sandberg@arm.com        _pc = _npc;
17410915Sandreas.sandberg@arm.com        _npc += sizeof(MachInst);
17510915Sandreas.sandberg@arm.com    }
17610915Sandreas.sandberg@arm.com};
17710915Sandreas.sandberg@arm.com
17810915Sandreas.sandberg@arm.comtemplate <class MachInst>
17910915Sandreas.sandberg@arm.comstd::ostream &
18010915Sandreas.sandberg@arm.comoperator<<(std::ostream & os, const SimplePCState<MachInst> &pc)
18110915Sandreas.sandberg@arm.com{
18210915Sandreas.sandberg@arm.com    ccprintf(os, "(%#x=>%#x)", pc.pc(), pc.npc());
18310915Sandreas.sandberg@arm.com    return os;
18410915Sandreas.sandberg@arm.com}
18510915Sandreas.sandberg@arm.com
18610915Sandreas.sandberg@arm.com// A PC and microcode PC.
18710915Sandreas.sandberg@arm.comtemplate <class MachInst>
18810915Sandreas.sandberg@arm.comclass UPCState : public SimplePCState<MachInst>
18910915Sandreas.sandberg@arm.com{
19010915Sandreas.sandberg@arm.com  protected:
19110915Sandreas.sandberg@arm.com    typedef SimplePCState<MachInst> Base;
19210915Sandreas.sandberg@arm.com
19310915Sandreas.sandberg@arm.com    MicroPC _upc;
19410915Sandreas.sandberg@arm.com    MicroPC _nupc;
19510915Sandreas.sandberg@arm.com
19610915Sandreas.sandberg@arm.com  public:
19710915Sandreas.sandberg@arm.com
19810915Sandreas.sandberg@arm.com    MicroPC upc() const { return _upc; }
19910915Sandreas.sandberg@arm.com    void upc(MicroPC val) { _upc = val; }
20010915Sandreas.sandberg@arm.com
20110915Sandreas.sandberg@arm.com    MicroPC nupc() const { return _nupc; }
20210915Sandreas.sandberg@arm.com    void nupc(MicroPC val) { _nupc = val; }
20310915Sandreas.sandberg@arm.com
20410915Sandreas.sandberg@arm.com    MicroPC
20510915Sandreas.sandberg@arm.com    microPC() const
20610915Sandreas.sandberg@arm.com    {
20710915Sandreas.sandberg@arm.com        return _upc;
20810915Sandreas.sandberg@arm.com    }
20910915Sandreas.sandberg@arm.com
21010915Sandreas.sandberg@arm.com    void
21110915Sandreas.sandberg@arm.com    set(Addr val)
21210915Sandreas.sandberg@arm.com    {
21310915Sandreas.sandberg@arm.com        Base::set(val);
21410915Sandreas.sandberg@arm.com        upc(0);
21510915Sandreas.sandberg@arm.com        nupc(1);
21610915Sandreas.sandberg@arm.com    }
21710915Sandreas.sandberg@arm.com
21810915Sandreas.sandberg@arm.com    UPCState() : _upc(0), _nupc(0) {}
21910915Sandreas.sandberg@arm.com    UPCState(Addr val) : _upc(0), _nupc(0) { set(val); }
22010915Sandreas.sandberg@arm.com
22110915Sandreas.sandberg@arm.com    bool
22210915Sandreas.sandberg@arm.com    branching() const
22310915Sandreas.sandberg@arm.com    {
22410915Sandreas.sandberg@arm.com        return this->npc() != this->pc() + sizeof(MachInst) ||
22510915Sandreas.sandberg@arm.com               this->nupc() != this->upc() + 1;
22610915Sandreas.sandberg@arm.com    }
22710915Sandreas.sandberg@arm.com
22810915Sandreas.sandberg@arm.com    // Advance the upc within the instruction.
22910915Sandreas.sandberg@arm.com    void
23010915Sandreas.sandberg@arm.com    uAdvance()
23110915Sandreas.sandberg@arm.com    {
23210915Sandreas.sandberg@arm.com        _upc = _nupc;
23310915Sandreas.sandberg@arm.com        _nupc++;
23410915Sandreas.sandberg@arm.com    }
23510915Sandreas.sandberg@arm.com
23610915Sandreas.sandberg@arm.com    // End the macroop by resetting the upc and advancing the regular pc.
23710915Sandreas.sandberg@arm.com    void
23810915Sandreas.sandberg@arm.com    uEnd()
23910915Sandreas.sandberg@arm.com    {
24010915Sandreas.sandberg@arm.com        this->advance();
24110915Sandreas.sandberg@arm.com        _upc = 0;
24210915Sandreas.sandberg@arm.com        _nupc = 1;
24310915Sandreas.sandberg@arm.com    }
24410915Sandreas.sandberg@arm.com
24510915Sandreas.sandberg@arm.com    bool
24610915Sandreas.sandberg@arm.com    operator == (const UPCState<MachInst> &opc) const
24710915Sandreas.sandberg@arm.com    {
24810915Sandreas.sandberg@arm.com        return Base::_pc == opc._pc &&
24910915Sandreas.sandberg@arm.com               Base::_npc == opc._npc &&
25010915Sandreas.sandberg@arm.com               _upc == opc._upc && _nupc == opc._nupc;
25110915Sandreas.sandberg@arm.com    }
25210915Sandreas.sandberg@arm.com
25310915Sandreas.sandberg@arm.com    bool
25410915Sandreas.sandberg@arm.com    operator != (const UPCState<MachInst> &opc) const
25510915Sandreas.sandberg@arm.com    {
25610915Sandreas.sandberg@arm.com        return !(*this == opc);
25710915Sandreas.sandberg@arm.com    }
25810915Sandreas.sandberg@arm.com
25910915Sandreas.sandberg@arm.com    void
26010915Sandreas.sandberg@arm.com    serialize(CheckpointOut &cp) const override
26110915Sandreas.sandberg@arm.com    {
26210915Sandreas.sandberg@arm.com        Base::serialize(cp);
26310915Sandreas.sandberg@arm.com        SERIALIZE_SCALAR(_upc);
26410915Sandreas.sandberg@arm.com        SERIALIZE_SCALAR(_nupc);
26510915Sandreas.sandberg@arm.com    }
26610915Sandreas.sandberg@arm.com
26710915Sandreas.sandberg@arm.com    void
26810915Sandreas.sandberg@arm.com    unserialize(CheckpointIn &cp) override
26910915Sandreas.sandberg@arm.com    {
27010915Sandreas.sandberg@arm.com        Base::unserialize(cp);
27110915Sandreas.sandberg@arm.com        UNSERIALIZE_SCALAR(_upc);
27210915Sandreas.sandberg@arm.com        UNSERIALIZE_SCALAR(_nupc);
27310915Sandreas.sandberg@arm.com    }
27410915Sandreas.sandberg@arm.com};
27510915Sandreas.sandberg@arm.com
27610915Sandreas.sandberg@arm.comtemplate <class MachInst>
27710915Sandreas.sandberg@arm.comstd::ostream &
27810915Sandreas.sandberg@arm.comoperator<<(std::ostream & os, const UPCState<MachInst> &pc)
27910915Sandreas.sandberg@arm.com{
28010915Sandreas.sandberg@arm.com    ccprintf(os, "(%#x=>%#x).(%d=>%d)",
28110915Sandreas.sandberg@arm.com            pc.pc(), pc.npc(), pc.upc(), pc.nupc());
28210915Sandreas.sandberg@arm.com    return os;
28310915Sandreas.sandberg@arm.com}
28410915Sandreas.sandberg@arm.com
28510915Sandreas.sandberg@arm.com// A PC with a delay slot.
28610915Sandreas.sandberg@arm.comtemplate <class MachInst>
28710915Sandreas.sandberg@arm.comclass DelaySlotPCState : public SimplePCState<MachInst>
28810915Sandreas.sandberg@arm.com{
28910915Sandreas.sandberg@arm.com  protected:
29010915Sandreas.sandberg@arm.com    typedef SimplePCState<MachInst> Base;
29110915Sandreas.sandberg@arm.com
29210915Sandreas.sandberg@arm.com    Addr _nnpc;
29310915Sandreas.sandberg@arm.com
29410915Sandreas.sandberg@arm.com  public:
29510915Sandreas.sandberg@arm.com
29610915Sandreas.sandberg@arm.com    Addr nnpc() const { return _nnpc; }
29710915Sandreas.sandberg@arm.com    void nnpc(Addr val) { _nnpc = val; }
29810915Sandreas.sandberg@arm.com
29910915Sandreas.sandberg@arm.com    void
30010915Sandreas.sandberg@arm.com    set(Addr val)
30110915Sandreas.sandberg@arm.com    {
30210915Sandreas.sandberg@arm.com        Base::set(val);
30310915Sandreas.sandberg@arm.com        nnpc(val + 2 * sizeof(MachInst));
30410915Sandreas.sandberg@arm.com    }
30510915Sandreas.sandberg@arm.com
30610915Sandreas.sandberg@arm.com    DelaySlotPCState() {}
30710915Sandreas.sandberg@arm.com    DelaySlotPCState(Addr val) { set(val); }
30810915Sandreas.sandberg@arm.com
30910915Sandreas.sandberg@arm.com    bool
31010915Sandreas.sandberg@arm.com    branching() const
31110915Sandreas.sandberg@arm.com    {
31210915Sandreas.sandberg@arm.com        return !(this->nnpc() == this->npc() + sizeof(MachInst) &&
31310915Sandreas.sandberg@arm.com                 (this->npc() == this->pc() + sizeof(MachInst) ||
31410915Sandreas.sandberg@arm.com                  this->npc() == this->pc() + 2 * sizeof(MachInst)));
31510915Sandreas.sandberg@arm.com    }
31610915Sandreas.sandberg@arm.com
31710915Sandreas.sandberg@arm.com    // Advance the PC.
31810915Sandreas.sandberg@arm.com    void
31910915Sandreas.sandberg@arm.com    advance()
32010915Sandreas.sandberg@arm.com    {
32110915Sandreas.sandberg@arm.com        Base::_pc = Base::_npc;
32210915Sandreas.sandberg@arm.com        Base::_npc = _nnpc;
32310915Sandreas.sandberg@arm.com        _nnpc += sizeof(MachInst);
32410915Sandreas.sandberg@arm.com    }
32510915Sandreas.sandberg@arm.com
32610915Sandreas.sandberg@arm.com    bool
32710915Sandreas.sandberg@arm.com    operator == (const DelaySlotPCState<MachInst> &opc) const
32810915Sandreas.sandberg@arm.com    {
32910915Sandreas.sandberg@arm.com        return Base::_pc == opc._pc &&
33010915Sandreas.sandberg@arm.com               Base::_npc == opc._npc &&
33110915Sandreas.sandberg@arm.com               _nnpc == opc._nnpc;
33210915Sandreas.sandberg@arm.com    }
33310915Sandreas.sandberg@arm.com
33410915Sandreas.sandberg@arm.com    bool
33510915Sandreas.sandberg@arm.com    operator != (const DelaySlotPCState<MachInst> &opc) const
33610915Sandreas.sandberg@arm.com    {
337        return !(*this == opc);
338    }
339
340    void
341    serialize(CheckpointOut &cp) const override
342    {
343        Base::serialize(cp);
344        SERIALIZE_SCALAR(_nnpc);
345    }
346
347    void
348    unserialize(CheckpointIn &cp) override
349    {
350        Base::unserialize(cp);
351        UNSERIALIZE_SCALAR(_nnpc);
352    }
353};
354
355template <class MachInst>
356std::ostream &
357operator<<(std::ostream & os, const DelaySlotPCState<MachInst> &pc)
358{
359    ccprintf(os, "(%#x=>%#x=>%#x)",
360            pc.pc(), pc.npc(), pc.nnpc());
361    return os;
362}
363
364// A PC with a delay slot and a microcode PC.
365template <class MachInst>
366class DelaySlotUPCState : public DelaySlotPCState<MachInst>
367{
368  protected:
369    typedef DelaySlotPCState<MachInst> Base;
370
371    MicroPC _upc;
372    MicroPC _nupc;
373
374  public:
375
376    MicroPC upc() const { return _upc; }
377    void upc(MicroPC val) { _upc = val; }
378
379    MicroPC nupc() const { return _nupc; }
380    void nupc(MicroPC val) { _nupc = val; }
381
382    MicroPC
383    microPC() const
384    {
385        return _upc;
386    }
387
388    void
389    set(Addr val)
390    {
391        Base::set(val);
392        upc(0);
393        nupc(1);
394    }
395
396    DelaySlotUPCState() {}
397    DelaySlotUPCState(Addr val) { set(val); }
398
399    bool
400    branching() const
401    {
402        return Base::branching() || this->nupc() != this->upc() + 1;
403    }
404
405    // Advance the upc within the instruction.
406    void
407    uAdvance()
408    {
409        _upc = _nupc;
410        _nupc++;
411    }
412
413    // End the macroop by resetting the upc and advancing the regular pc.
414    void
415    uEnd()
416    {
417        this->advance();
418        _upc = 0;
419        _nupc = 1;
420    }
421
422    bool
423    operator == (const DelaySlotUPCState<MachInst> &opc) const
424    {
425        return Base::_pc == opc._pc &&
426               Base::_npc == opc._npc &&
427               Base::_nnpc == opc._nnpc &&
428               _upc == opc._upc && _nupc == opc._nupc;
429    }
430
431    bool
432    operator != (const DelaySlotUPCState<MachInst> &opc) const
433    {
434        return !(*this == opc);
435    }
436
437    void
438    serialize(CheckpointOut &cp) const override
439    {
440        Base::serialize(cp);
441        SERIALIZE_SCALAR(_upc);
442        SERIALIZE_SCALAR(_nupc);
443    }
444
445    void
446    unserialize(CheckpointIn &cp) override
447    {
448        Base::unserialize(cp);
449        UNSERIALIZE_SCALAR(_upc);
450        UNSERIALIZE_SCALAR(_nupc);
451    }
452};
453
454template <class MachInst>
455std::ostream &
456operator<<(std::ostream & os, const DelaySlotUPCState<MachInst> &pc)
457{
458    ccprintf(os, "(%#x=>%#x=>%#x).(%d=>%d)",
459            pc.pc(), pc.npc(), pc.nnpc(), pc.upc(), pc.nupc());
460    return os;
461}
462
463}
464
465#endif
466