mmapped_ipr.hh revision 9897 
1/*
2 * Copyright (c) 2013 Andreas Sandberg
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Andreas Sandberg
29 */
30
31#ifndef __ARCH_GENERIC_MMAPPED_IPR_HH__
32#define __ARCH_GENERIC_MMAPPED_IPR_HH__
33
34#include "base/types.hh"
35#include "mem/packet.hh"
36
37class ThreadContext;
38
39/**
40 * @file
41 *
42 * ISA-generic helper functions for memory mapped IPR accesses.
43 */
44
45namespace GenericISA
46{
47    /** @{ */
48    /**
49     * Memory requests with the MMAPPED_IPR flag are generally mapped
50     * to registers. There is a class of these registers that are
51     * internal to gem5, for example gem5 pseudo-ops in virtualized
52     * mode.
53     *
54     * In order to make the IPR space manageable we always set bit 63
55     * (IPR_GENERIC) for accesses that should be handled by the
56     * generic ISA code. Architectures may use the rest of the IPR
57     * space internally.
58     */
59
60    /** Is this a generic IPR access? */
61    const Addr IPR_GENERIC = ULL(0x8000000000000000);
62
63    /** @{ */
64    /** Mask when extracting the class of a generic IPR */
65    const Addr IPR_CLASS_MASK = ULL(0x7FFF000000000000);
66    /** Shift amount when extracting the class of a generic IPR */
67    const int IPR_CLASS_SHIFT = 48;
68    /** @} */
69
70    /** Mask to extract the offset in within a generic IPR class */
71    const Addr IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF);
72
73    /** gem5 pseudo-inst emulation.
74     *
75     * Read and writes to this class execute gem5
76     * pseudo-instructions. A write discards the return value of the
77     * instruction, while a read returns it.
78     *
79     * @see pseudoInst()
80     */
81    const Addr IPR_CLASS_PSEUDO_INST = 0x0;
82
83    /** @} */
84
85    /**
86     * Generate a generic IPR address that emulates a pseudo inst
87     *
88     * @see PseudoInst::pseudoInst()
89     *
90     * @param func Function ID to call.
91     * @param subfunc Sub-function, usually 0.
92     * @return Address in the IPR space corresponding to the call.
93     */
94    inline Addr
95    iprAddressPseudoInst(uint8_t func, uint8_t subfunc)
96    {
97        return IPR_GENERIC | (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT)  |
98            (func << 8) | subfunc;
99    }
100
101    /**
102     * Check if this is an platform independent IPR access
103     *
104     * Accesses to internal platform independent gem5 registers are
105     * handled by handleGenericIprRead() and
106     * handleGenericIprWrite(). This method determines if a packet
107     * should be routed to those functions instead of the platform
108     * specific code.
109     *
110     * @see handleGenericIprRead
111     * @see handleGenericIprWrite
112     */
113    inline bool
114    isGenericIprAccess(const Packet *pkt)
115    {
116        return pkt->getAddr() & IPR_GENERIC;
117    }
118
119    /**
120     * Handle generic IPR reads
121     *
122     * @param xc Thread context of the current thread.
123     * @param pkt Packet from the CPU
124     * @return Latency in CPU cycles
125     */
126    Cycles handleGenericIprRead(ThreadContext *xc, Packet *pkt);
127    /**
128     * Handle generic IPR writes
129     *
130     * @param xc Thread context of the current thread.
131     * @param pkt Packet from the CPU
132     * @return Latency in CPU cycles
133     */
134    Cycles handleGenericIprWrite(ThreadContext *xc, Packet *pkt);
135
136    /**
137     * Helper function to handle IPRs when the target architecture doesn't
138     * need its own IPR handling.
139     *
140     * This function calls handleGenericIprRead if the accessing a
141     * generic IPR and panics otherwise.
142     *
143     * @param xc Thread context of the current thread.
144     * @param pkt Packet from the CPU
145     * @return Latency in CPU cycles
146     */
147    inline Cycles
148    handleIprRead(ThreadContext *xc, Packet *pkt)
149    {
150        if (!isGenericIprAccess(pkt))
151            panic("Unhandled IPR access\n");
152
153        return handleGenericIprRead(xc, pkt);
154    }
155
156
157    /**
158     * Helper function to handle IPRs when the target architecture
159     * doesn't need its own IPR handling.
160     *
161     * This function calls handleGenericIprWrite if the accessing a
162     * generic IPR and panics otherwise.
163     *
164     * @param xc Thread context of the current thread.
165     * @param pkt Packet from the CPU
166     * @return Latency in CPU cycles
167     */
168    inline Cycles
169    handleIprWrite(ThreadContext *xc, Packet *pkt)
170    {
171        if (!isGenericIprAccess(pkt))
172            panic("Unhandled IPR access\n");
173
174        return handleGenericIprWrite(xc, pkt);
175    }
176
177} // namespace GenericISA
178
179
180
181#endif
182